1 A Power Dissipation Comparison of the R-TDMA and the Slotted-Aloha Wireless MAC Protocols
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HC-MOS Power DissipationIf there is one single characteristic that justifies the existence of CMOS,it is low power dissipation.In the quiescent state,high-speed CMOS draws five to seven orders of magnitude less power than the equivalent LSTTL function.When switching,the amount of power dissipated by both metal gate and high-speed silicon gate CMOS is directly propor-tional to the operating frequency of the device.This is be-cause the higher the operating frequency,the more often the device is being switched.Since each transition requires power,power consumption increases with frequency.First,one will find a description of the causes of power con-sumption in HC-CMOS and LSTTL applications.Next will fol-low a comparison of MM54HC/MM74HC to LSTTL power dissipation.Finally,the maximum ratings for power dissipa-tion imposed by the device package will be discussed.Quiescent Power ConsumptionIdeally,when a CMOS integrated circuit is not switching,there should be no DC current paths from V CC to ground,and the device should not draw any supply current at all.However,due to the inherent nature of semiconductors,a small amount of leakage current flows across all reverse-biased diode junctions on the integrated circuit.These leakages are caused by thermally-generated charge carriers in the diode area.As the temperature of the diode in-creases,so do the number of these unwanted charge carri-ers,hence leakage current increases.Leakage current is specified for all CMOS devices as I CC .This is the DC current that flows from V CC to ground when all inputs are held at either V CC or ground,and all outputs are open.This is known as the quiescent state.For the MM54HC/MM74HC family,I CC is specified at ambi-ent temperatures (T A )of 25˚C,85˚C,and 125˚C.There are three different specifications at each temperature,depend-ing on the complexity of the device.The number of diode junctions grows with circuit complexity,thereby increasing the leakage current.The worst case I CC specifications for the MM54HC/MM74HC family are summarized in Table 1.In ad-dition,it should be noted that the maximum I CC current will decrease as the temperature goes below 25˚C.TABLE 1.Supply Current (I CC )for MM54HC/MM74HCSpecified at V CC =6V T A Gate Buffer MSI Unit 25˚C 2.0 4.08.0µA 85˚C 204080µA 125˚C4080160µATo obtain the quiescent power consumption for any CMOS device,simply multiply I CC by the supply voltage:P DC =I CC V CCSample calculations show that at room temperature the maximum power dissipation of gate,buffer,and MSI circuits at V CC =6V are 10µW,20µW,and 40µW,respectively.Dynamic Power ConsumptionDynamic power consumption is basically the result of charg-ing and discharging capacitances.It can be broken down into three fundamental components,which are:1.Load capacitance transient dissipation 2.Internal capacitance transient dissipation 3.Current spiking during switching.Load Capacitance Transient DissipationThe first contributor to power consumption is the charging and discharging of external load capacitances.Figure 1is a schematic diagram of a simple CMOS inverter driving a ca-pacitive load.A simple expression for power dissipation as a function of load capacitance can be derived starting with:Q L =C L V CC where C L is the load capacitance,and Q L is the charge on the capacitor.If both sides of the equation are divided by the time required to charge and discharge the capacitor (one pe-riod,T,of the input signal),we obtain:Since charge per unit time is current (Q L /T =l)and the in-verse of the period of a waveform is frequency (1/T =f):l L =C L V CC f To find the power dissipation,both sides of the equation must be multiplied by the supply voltage (P =Vl),yielding:P L =C L V CC 2f One note of caution is in order.If all the outputs of a device are not switching at the same frequency,then the power con-sumption must be calculated at the proper frequency for each output:P L =V CC 2(C L1f 1+C L2f 2+...+C Ln f n )Examples of devices for which this may apply are:counters,dual flip-flops with independent clocks,and other integrated circuits containing dual,triple,etc.,independent circuits.AN005021-1FIGURE 1.Simple CMOS Inverter Driving aCapacitive External LoadFairchild Semiconductor Application Note 303February 1984HC-CMOS Power DissipationAN-303©1998Fairchild Semiconductor Corporation AN005021Internal Capacitance Transient DissipationInternal capacitance transient dissipation is similar to load capacitance dissipation,except that the internal parasitic “on-chip”capacitance is being charged and discharged.Fig-ure 2is a diagram of the parasitic nodal capacitances asso-ciated with two CMOS inverters.C 1and C 2are capacitances associated with the overlap of the gate area and the source and channel regions of the P-and N-channel transistors,respectively.C 3is due to the overlap of the gate and source (output),and is known as the Miller capacitance.C 4and C 5are capacitances of the para-sitic diodes from the output to V CC and ground,respectively.Thus the total internal capacitance seen by inverter 1driving inverter 2is:C l =C 1+C 2+2C 3+C 4+C 5Since an internal capacitance may be treated identically to an external load capacitor for power consumption calcula-tions,the same equation may be used:P l =C l V CC 2f At this point,it may be assumed that different parts of the in-ternal circuitry are operating at different frequencies.Al-though this is true,each part of the circuit has a fixed fre-quency relationship between it and the rest of the device.Thus,one value of an effective C l can be used to compute the internal power dissipation at any frequency.More will be said about this shortly.Current Spiking During SwitchingThe final contributor to power consumption is current spiking during switching.While the input to a gate is making a tran-sition between logic levels,both the P-and N-channel tran-sistors are turned partially on.This creates a low impedance path for supply current to flow from V CC to ground,as illus-trated in Figure 3.For fast input rise and fall times (shorter than 50ns for the MM54HC/MM74HC family),the resulting power consump-tion is frequency dependent.This is due to the fact that the more often a device is switched,the more often the input is situated between logic levels,causing both transistors to be partially turned on.Since this power consumption is propor-tional to input frequency and specific to a given device in any application,as is C l ,it can be combined with C l .The result-ing term is called “C PD,”the no-load power dissipation ca-pacitance.It is specified for every MM54HC/MM74HC de-vice in the AC Electrical Characteristic section of each data sheet.It should be noted that as input rise and fall times become longer,the switching current power dissipation becomes more dependent on the amount of time that both the P-and N-channel transistors are turned on,and less related to C PD as specified in the data sheets.Figure 4is a representation of the effective value of C PD as input rise and fall times in-crease for the MM54HC/MM74HC08,MM54HC/MM74HC139,and MM54HC/MM74HC390.To get a fair comparison between the three curves,each is divided by the value of C PD for the particular device with fast input rise and fall times.This is represented by “C PD0,”the value of C PD specified in the data sheets for each part.This comparison appears in Figure 5.C PD remains constant for input rise and fall times up to about 20ns,after which it rises,approaching a linear slope of 1.The graphs do not all reach a slope of 1at the same time because of necessary differences in circuit design for each part.The MM54HC/MM74HC08exhibits the greatest change in C PD ,while the MM54HC/MM74HC139shows less of an increase in C PD at any given frequency.Thus,the power dissipation for most of the parts in the MM54HC/MM74HC family will fall within these two curves.One notable exception is the MM54HC/MM74HCU04.AN005021-2FIGURE 2.Parasitic Internal CapacitancesAssociated with Two InvertersAN005021-3AN005021-4FIGURE 3.Equivalent schematic of a CMOS inverter whose input is between logic levels 2Inputs that do not pull all the way to V CC or ground can also cause an increase in power consumption,for the same rea-son given for slow rise and fall times.If the input voltage is between the minimum input high voltage and V CC ,then the input N-channel transistor will have a low impedance (i.e.,be “turned on”)as expected,but the P-channel transistor will not be completely turned off.Similarly,if the input is between ground and the maximum input low voltage,the P-channel transistor will be fully on and the N-channel transistor will be partially on.In either case,a resistive path from V CC to ground will occur,resulting in an increase in power con-sumption.Combining all the derived equations,we arrive at the follow-ing:P TOTAL =(C L +C PD )V CC 2f+l CC V CC This equation can be used to compute the total power con-sumption of any MM54HC/MM74HC device,as well as any other CMOS device,at any operating frequency.It includes both DC and AC contributions to power usage.C PD and l CC are supplied in each data sheet for the particular device,and V CC and f are determined by the particular application.Comparing HC-CMOS to LSTTLAlthough power consumption is somewhat dependent on frequency in LSTTL devices,the majority of power dissi-pated below 1MHz is due to quiescent supply current.LSTTL contains many resistive paths from V CC to ground,and even when it is not switching,it draws several orders of magnitude greater supply current than HC-CMOS.Figure 6is a bar graph comparison of quiescent power requirements (V CC )x(l CC )between LSTTL and HC-CMOS devices.The reduction in CMOS power consumption as compared to LSTTL devices is illustrated in Figure 7and Figure 8.These graphs are comparisons of the typical supply current (l CC )re-quired for equivalent functions in MM54HC/MM74HC,MM54HC/MM74C,CD4000,and 54LS/74LS logic families.The currents were measured at room temperature (25˚C)with a supply voltage of 5V.Figure 7represents the supply current required for a quad NAND gate with one gate in the package switching.The MM54HC/MM74HC family draws slightly more supply cur-rent than the 54C/74C and CD4000series.This is mainly due to the large size of the output buffers necessary to source and sink currents characteristic of the LSTTL family.Other reasons include processing differences and the larger internal circuitry required to drive the output buffers at high frequencies.The frequency at which the CMOS device draws as much power as the LSTTL device,known as the power cross-over-frequency,is about 20MHz.In Figure 8,which is a comparison of equivalent flip-flops (174)and shift registers (164)from the different logic fami-lies,the power cross-over frequency again occurs at about 20MHz.The power cross-over frequency increases as circuit com-plexity increases.There are two major reasons for this.First,having more devices on an LSTTL integrated circuit means that more resistive paths between V CC and ground will occur,and more quiescent current will be required.In a CMOS in-tegrated circuit,although the supply leakage current will in-AN005021-5FIGURE parison of Typical C PD for MM54HC/MM74HC08,MM54HC/MM74HC139MM54HC/MM74HC390as a Function ofInput Rise and Fall Time.t rise =t fall,V CC =5V,T A =25˚CAN005021-6FIGURE 5.Normalized Effective C PD (Typical)for Slow Input Rise and Fall Times.t rise =t fall,V CC =5V,T A =25˚C AN005021-7FIGURE 6.High Speed CMOS (HC-CMOS)vs.LSTTLQuiescent Power Consumption crease,it is of such a small magnitude (nanoAmps per de-vice)that there will be very little increase in total power consumption.Secondly,as system complexity increases,the precentage of the total system operating at the maximum frequency tends to decrease.Figure 9shows block diagrams of a CMOS and an equivalent LSTTL system.In this abstract system,there is a block of parts operating at the maximum frequency (F max ),a block operating at half F max ,a block op-erating at one quarter F max ,and so on.Let us call the power consumed in the first section P1.In a CMOS system,since power consumption is directly proportional to the operating frequency,the amount of power consumed by the second block will be (P1)/2,and the amount used in the third section will be (P1)/4.If the power consumed over a large number of blocks is summed up,we obtain:P TOTAL =P1+(P1)/2+(P1)/4+...+(P1)/(2n–1)and P TOTAL ≤2(P1)Now consider the LSTTL system.Again,the power con-sumed in the first block is P1.The amount of power dissi-pated in the second block is something less than P1,but greater than (P1)/2.For simplicity,we can assume the best case,that P2=(P1)/2.The power consumption for all system blocks operating at frequencies F max /2and below will be dominated by quiescent current,which will not change with frequency.The power used by blocks 3through n will be ap-proximately equal to the power dissipated by block 2,(P1)/2.The total power consumed in the LSTTL system is:P TOTAL =(P1+(P1)/2+(P1)/2+...+(P1)/2P TOTAL =P1+(N–1)(P1)/2and for n >2,P TOTAL >2(P1)Thus,an LSTTL system will draw more power than an equivalent HC-CMOS system.This effect is further illustrated in Figure 10.An arbitrary sys-tem is composed of 200gates,150counters,and 150full adders,with 50pF loads on all of the outputs.The supply voltage is 5V,and the system is at room temperature.For this system,the worst case power consumption for CMOS is about an order of magnitude lower than the typical LSTTL power requirements.Thus,as system complexity increases,CMOS will save more power.Maximum Power Dissipation LimitsIt is important to take into consideration the maximum power dissipation limits imposed on a device by the package when designing with high-speed CMOS.The plastic small-outline (SO)can dissipate up to 500mW,and the ceramic DIP and plastic DIP can dissipate up to 700mW.Although this limit will rarely be reached in typical high-speed applications,the MM54HC/MM74HC family has such large output current source and sink capabilities that driving a resistive load could possibly take a device to the 500or 700mW limit.This maximum power dissipation rating should be derated,start-ing at 65˚C for the plastic packages and 100˚C for the ce-ramic packages.The derating factor is different for each package.The factor for the plastic small-outline is −8.83mW/˚C;the plastic DIP ,−12mW/˚C;and the ceramic DIP ,−14mW/˚C.This is illustrated in Figures 11,12.Thus,if a device in a plastic DIP package is operating at 70˚C,then the maximum power dissipation rating would be 700mW −(70˚C −65˚C)(12mW/˚C)=640mW.Note that the maxi-mum ambient temperature is 85˚C for plastic packages and 125˚C for ceramic packages.AN005021-8FIGURE 7.Supply Current vs.Input Frequencyfor Equivalent NAND GatesAN005021-9FIGURE 8.Supply Current vs.FrequencyAN005021-10FIGURE parison of Equivalent CMOSand LSTTL Systems AN005021-11FIGURE 10.System Power vs.FrequencyMMHC74HC vs.LSTTL 4AN005021-12 FIGURE11.Plastic Package(MM74HC) High Temperature Power Derating for MM54HC/MM74HC FamilyAN005021-13FIGURE12.Ceramic Package(MM54HC)High Temperature Power Deratingfor MM54HC/MM74HC FamilySummaryThe MM54HC/MM74HC high-speed silicon gate CMOS fam-ily has quiescent (standby)power consumption five to seven orders of magnitude lower than the equivalent LSTTL func-tion.At high frequencies (30MHz and above),both families consume a similar amount of power for very simple systems.However,as system complexity increases,HC-CMOS uses much less power than LSTTL.To keep power consumption low,input rise and fall times should be fast (less than 50to 100ns)and inputs should swing all the way to V CC and ground.There is an easy-to-use equation to compute the power con-sumption of any HC-CMOS device in any application:P TOTAL =(C L +C PD )V CC 2f+l CC V CC The maximum power dissipation rating is 500mW per pack-age at room temperature,and must be derated as tempera-ture increases.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI-CONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or sys-tems which,(a)are intended for surgical implant into the body,or (b)support or sustain life,and (c)whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.2.A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.Fairchild Semiconductor Corporation AmericasCustomer Response Center Tel:1-888-522-5372Fairchild Semiconductor EuropeFax:+49(0)180-5308586Email:**********************Deutsch Tel:+49(0)8141-35-0English Tel:+44(0)1793-85-68-56Italy Tel:+39(0)2575631Fairchild SemiconductorHong Kong Ltd.13th Floor,Straight Block,Ocean Centre,5Canton Rd.Tsimshatsui,Kowloon Hong KongTel:+8522737-7200Fax:+8522314-0061National Semiconductor Japan Ltd.Tel:81-3-5620-6175Fax:81-3-5620-6179A N -303H C -C M O S P o w e r D i s s i p a t i o nFairchild does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.。
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owerbracket下机架limit范围,限制lowerbushes下轴套linear线性的lowerlimit下限liner衬板loweroilcooler下导油冷器link连板lowerslinger下挡油圈linkingplate连板lower较低的loadlosses负载损耗lubricatedistributor润滑配油器loadingoilpressure工作油压lubricate润滑load负荷,负载lubrication润滑油lug吊耳,连接片material材料,物资machine机器,机械加工maximum最大,极大machined加工MCB内存控制块machining加工meanlength平均长magneticparticleexamination磁粉探伤,meanvalue平均值磁粉检查mean中间的,平均的magneticring磁轭measurepoint测点magnitude幅值measure测量值maincircuit主回路measured标准的maincontrolvalve主控阀measurement测量maindistributingvalve主配阀measuringcell测量元件mainshaft大轴measuringstick测量杆maintain维修measuring测量maintenance维护,保持mechanical机械的majorfault主要故障mechanics机械学malfunction故障memorandum备忘录,便笺mallet槌棒message信息man-door进人门metaltemperature瓦温manifold总管metaltube金属软管manualemergencystation紧急手动操作metallicseal金属密封平台methane甲烷manualmode手动方式method手段,方法manually手动micrometer千分尺manual手册,手动的microphone麦克风manufactory制造厂millingmachine铣床manufacture制造minimum最小,极小manufacturing制造minorfault次要故障mark标志,记号,刻度mist油雾master主mixedbed-ionexchanger混床-离子交换match匹配机mode方式neutral中性的modification修正nipper钳子module模件,模块nitrogen氮气moisture潮湿,湿气no-loadlosses空载损耗molten熔化,熔铸的no-load空载momentary-contactswitch接触开关nominaldimension公称尺寸;标称尺寸momentary瞬间的nominal名义,额定的monitoringdevice监测装置nonreturnvalve止回阀monitoring监视non-linear非线性monitor监视器normalDIRC.正向MoS2二硫化钼noseangle蜗壳包角motivation目的nose蜗壳鼻端motor电动机,马达notify通报mounting安装nozzle喷嘴mount装配nudity裸体,赤裸movement动作number数目MPS多用途图形显示系统nut螺母MT(maintransformer)主变OtypeO型multi-meter万用表observer观测者multiplier/hightorquewrench增力扳手observing观察nakedflames明火off-centeredpin偏心销nameplate铭牌official正式的NDE(nondrivenend)非驱动端,立式机组offset偏移量的上端off-voltage无压needle针oilbafflering挡油圈negativedirection负方向oilcircuit油路network网络oilcirculatingpump油循环泵net网,净的oilcolumn油柱neutralpoint中性点oilcontainer油槽neutralizationvalue中和值oilcooler油冷器oildrainingpipe排油管opencircuit开路oilfillingpipe进油管openspanner开口扳手oilfiltrationunit油过滤器operate操作,运行oilguideplate导油板operatingcubicle操作柜oilhouse油槽operatinginstruction运行说明书oillevelindicator油位计operatinglever操作杆oillevel油位operatingpane操l作面板oilmistPollutionfilter油雾吸收过滤器operatingring控制环oilmistsuctiondevice油雾吸收装置operatingvalve操作阀oilpot油槽operating运行的,工作的oilpressuresupply油压装置operation运转oilpump油泵opticallevel光学水平仪oilreservoir油箱,油槽optical光学的oilretainingpipe挡油管orangeyellowpaint橘黄色漆oilreturntank回油箱ordering订货oilsample(sampling)油样orientedglasstape无碱玻璃丝带oilseparator油水分离器orifice孔oilsupplyline操作油管O-ringO型圈oiltemperature油温oscilloscope示波器oilwelltube挡油管outage停电oilwettedairfilter油浸空气过滤器outerdiameter外径oil油outerlug外舌oil/watercooler油/水冷却器outlet出口oil-feedinghole注油孔output产量,输出oil-immersedtransformer油浸变压器outsidemicrometergauge外径千分尺oil-levelgage油位计outside外部,外面oil-proof耐油overexcitation过励磁onload加载overspeed过速onsite现场overTEMP.超温openbase无底overtime超时overtorque过力矩permanent永久的overvoltage过电压permissible允许的overlapping覆盖,重叠perpendicular垂直度overload过载,过重per每,一oversize尺寸过大phaseangle相角over-speed过速phaseresistance相电阻oxygen氧气phasesequenceindicato相r序表packinglist装箱单phasesequenc相e序packing包装phaseshifting调相pad瓦块,衬垫phasetoneutra相l对地e间paint油漆,刷漆,喷漆phasetophas线panellight面板照明phase相,形式panel配电盘,仪表盘phenolic酚醛parallelresistor并联电阻phosphorizedprimer磷化底漆parallel并联的,平行的pilotvalve控制阀,引导阀parameter参数pinion小齿轮partialdischarge局部放电pin销钉partial局部pipebended弯管parts零部件pipeclamp管夹path支路pipeclip管夹Pb-washer铅垫圈pipeelement管路元件pedestal支柱pipehanger管道支架pelableshim可撕垫pipesystem管路系统pendulum飞摆pipeline管线penetrant渗透剂pipe管路perchlorovinyl过氯乙烯piping管路performance性能pistonring活塞环perform履行pistonrod活塞杆periodical定期的pistonvalve活塞阀period时间段pitliner机坑里衬pitchfactor短矩系数,短距比polyamidescrew聚酰胺螺栓pitchoffins叶片距port端口pitch节,间距positionsensor位置传感器pit坑positivedirection正方向pivot支柱螺钉post-weld焊后plasticfoil塑料薄片potentialtransformer电压互感器plastic塑料potential电势platsteelplate扁钢potiersreactance保梯电抗platweld平焊powerangle功角platevalve盘型阀powerfactor功率因数plate板powerfeedback功率反馈pluginmonitoring插拔监视powerhouse厂房plugsock塞孔powerloss功率损耗,失电plug插头,插销powerregulatingrate功率调节速度plumblossomshaped梅花型powersupply电源plumb铅锤power力,能力,动力,功率plunger活塞pre-analysis预分析point点precaution预防polarity极性preceding在前的,前述的poleendplate磁极压板precisionlevel精密水准仪polefixing磁极固定precisionsquare精密角尺polejumper极间连接线preheattemperature预热温度polekey磁极键premierpaint底漆polepunching磁极冲片preparation准备poleshoe极靴preparing准备polestacked叠成的磁极pre-press预压紧polesupport磁极挡块pressfinger压指polewedging磁极楔入pressring压圈pole磁极pressing压紧polish抛光pressuredrop压降pressuregauge压力计pullrod推拉杆pressuremeasuringhole测压孔pulsation震动pressureoil压力油pulsetransformers脉冲变压器pressureswitch压力开关pulseschanne脉l冲通道pressuretank压油罐pulse脉冲pressuretap测压孔pumpcharacteristic水泵特性曲线pressuretest压力试验pumpping泵环pressuretransducer压力传感器pump泵pressuretype压力式punchingpoint样冲点pressure压力purchaser买方press压purewatersupplyunit纯水供应系统)水系统presume假设purewatersystem(PWS纯previous先前的,以前的purewater纯水primary一次绕组pure纯净的probe探针purificationfilter净化装置,过滤器procedure步骤,程序pursuant依照的productgroup生产组pushbutton按钮productionsite生产地putty腻子prohibit禁止,阻止Q-slope无功调差project工程quadrantaxis交轴proof证明quadrant正交propane丙烷quality质量property财产quantity数量propylene丙烯quickfallinletgate快速落进水口闸门protection保护quit退protect保护radialplate径向板prove证明radial半径的provision预备,防备,规定radius半径,径向PSS电力系统安全装置raiseto升至Pt-thermalresistor铂热电阻raise提起,提升ramp斜坡referencevaluelower减给定range行程;量程;范围referencevalue参考值ratedpower额定功率reference参考ratedvoltageratio额定电压比REG.CH1调节器通道1rated额定regular定期的rate比例,速度,估价regulatingrange调节范围ratingplate标牌,铭牌regulationmode调节模式rating分配,估价,额定regulation调节ratio比率,比例,比regulator调节器rawwater生水,二次冷却水rejectload甩负荷reactanceleakage漏抗relay继电器reactance电抗release释放reactivepower无功功率relevant有关的,相应的reactive电抗的remanence剩磁reactor电抗器remarks附注ready准备好的remedialmeasure补救措施ream铰remotecontrol远方控制reboundvalve返回阀remote远方recirculation再循环,再流通repair修理recommendrequest请求,要求reconnect再合require命令,需求rectangularity直角度reseal重新决定rectifier整流器reserve储备,预定recurrent-surge-generator周期涌流发生器reservoir油箱,水库recurrent周期的resistancethermaldevice热电阻reduce减少resistancethermometer电阻温度计redundant冗余的resistance电阻reemergingtool扩孔工具resistance电阻referenceNo.参考号resistivity抵抗力,电阻率referencevaluehigher增给定response回答,响应responsibility责任roundnessmeasuringdevice测圆架result结果roundness圆度retainblock挡块routinetest定期测试retain止动RP=RatedPower额定功率reversepower逆功率rubberfiller橡皮垫reverse反转,反向rubberhose橡胶管rib筋板rubberstrip橡皮条rimstamping磁轭冲片rule规则rim磁轭runawayspeed飞逸转速ringpipe环管runaway飞逸ringpipe环管runnerbandseal下止漏环ringspanner圆扳手runnerband转轮下环ring轮,环,环带runnerboos转轮体,轮毂rise上升,起身runnerbucket转轮叶片rod螺栓runnerchamber转轮室Roebel罗贝尔runnercrownseal上止漏环roller转轴runnercrown转轮上冠rotaryvalve球阀runnertip转轮泄水锥rotary旋转的runner转轮rotatingring镜板runoff径流(量)rotation旋转run-out摆度rotorfieldspider转子支架run运行rotorhub转子中心体rustproofoil防锈油rotorrim转子磁轭rust生锈rotorspider转子支架RWS(rawwatersystem)生水系统rotor转子safetybelt安全带roughness粗糙度safetydevice安全装置roundnut圆螺帽safetyrope安全绳roundpin圆柱销safetyvalve安全阀roundseal圆盘根samplingtime取样时间WOED格式sampling取样seal密封sandblasting喷砂处理seamlesstube无缝钢管sandpaper砂纸Seamless无缝saponificationvalue皂化值seat支撑座satisfy满足secondcoatprimer二道底漆saturation饱和secondarycircuit二次电路scaffolding脚手架secondarywiring二次绕组scaffold脚手架securingkey卡键scalefactor刻度系数segmentincircle整圆扇形片schematic图解的,segmentspindle承重螺栓scopecover责任范围segment片断,支臂,部分,瓣scopeface显示屏selectorswitch选择开关scope指示器,观测设备,范围self-oiling自润滑scraper刮刀self-priming自起注油screen屏蔽semi-automode半自动模式screwdriver螺丝刀semicircletop半圆头screwfixedtype固定螺纹式semiconductor半导体screwpipe丝管senseorgan传感器,敏感元件screwpump螺杆泵,螺旋泵sensitivity灵敏度screwstud全牙螺纹sensor传感器screwthread螺纹separate分离的,单独的screw螺杆,螺孔,螺钉separating间隔screw螺丝钉,拧,旋separation分隔,间隔scriber划针sequence次序,顺序,序列sealring密封圈seriallink串行连接sealedcover密封盖serialNo.系列号sealingagent密封剂service维护,保养,检修sealingprofile密封条servovalve伺服阀sealingring密封圈servomotorpiston接力器活塞sealing密封servomotorstroke接力器行程servomotor伺服电动机,接力器signal信号setreferencepoint放样点sign标记,签名setting安装,装配silverbrazepiece银焊片shaftseal主轴密封silverstrip银焊片shaftvoltage轴电压silverweldwire银焊丝shaft轴silver银,镀银sharp尖角simplexfilter单路过滤器shearpin剪断销simulation模拟shear剪切,剪切力simulator模拟器shearingforce剪切力simultaneously同时地shearingstress剪应力singlethickness单边厚度sheetiron硅钢片,冲片single一个的,单独的sheet一张,纸张,片,冲片sinusoidal正弦曲线shell&tubeheatexchanger薄壳/管道热site位置,地点交换器sixanglebolt六角螺栓shim垫片slantingendcoilspacer斜边垫块shipment出货slantingjoiningbox并头套shippingandlifting运输和吊装slanting斜shippingweight运输重量slave从动设备shoe鞋靴sleevespanner套筒扳手shop止动sleeve套筒shortthrustbearing止推块slideresistor滑动电阻器short-circuitratio短路比slidevalve活动阀short-circuit短路slide下滑shrinkhose热缩软管slipringhousing集电环室shrinkageshim热套垫片slipringleads励磁引线shutoff断流,关断slipring集电环shutdown落门slotcontroldevice通槽棒signalvoltage信号电压slotcurrent槽电流signaling信号传输slotendspacer槽口垫块slotkey槽样棒spearvalve针阀slotmouth槽口specialflange特殊法兰slotopening槽开口specialtool专用工具slotplate槽板specification规格,说明书,规范slotsignal复归信号specify规定slotwedge槽楔speedcounter转速表slot缝,槽speeddetector测速元件sluicevalve闸阀speedgoverningdevice调速装置smokedetector烟雾探测仪speedgovernor调速器smoke烟speed转速,速度snapthinspanner开口薄扳手spider蜘蛛,支架socketbend管节弯头spigot栓,龙头,套管socketbulb卡口灯泡spindlesupport支柱螺栓支座socketcapscrew圆柱头内六角螺钉spindle轴,杆,心轴socketwrench套筒扳手spiralcaseaccess蜗壳进人门socket槽,插口,套节spiralcase蜗壳softCu-plate软铜板spiral蜗壳的softmetalpipe金属软管spoke轮辐softwarepackage软件包spray喷射,喷雾solderingcopperconnection锡铜连接springpipe波纹管solenoidvalve电磁阀springwasher弹簧垫圈sole基础springwedge弹簧楔soundpressureleve声l压级spring弹簧spacerforslanting斜边垫块square方形spacerstrip间隔垫条stability稳定性spacer垫片,垫块stacking叠压系数spanner扳手stack堆,堆积span跨度,范围stainlesssteel不锈钢spareparts备品stainless不锈的spare备用的,备件stamping冲片standby备用suctionline进油管start-up起动suctionoilstrainer进油过滤器state状态suction吸入,吸收,抽(吸)station站suitability适宜性stationary固定的sumofvalues总量statorborediameter定子内径sumptank回油箱statorcomplete定子组装supervoltage超高压statorcurrentlimitation定子电流限制supervision监视器statorgrounding定子接地supplementary附加的,补加的stator定子supplier供货人status状态supply供给stay-ring座环support支架,支撑stay支撑,支柱surfaceequal-pressure等压面steeltapemeasure钢卷尺surfacepaint面漆steelthread钢丝线surface表面,表面积steprespons阶e跃响应surge涌流stopstatus停止状态suspect可疑的storagetank储油罐suspend悬挂store存储switchto切换straightedge直尺switchingimpulse操作冲击strainer过滤网switchover切换strap短线段switch开关streamline流线型的symbol符号strength强度,力量symmetrically对称地stressratio安全系数,应力比synchronization同期stress压力,应力synchronizingimpulse同步脉冲strip条synchronizingvoltage同步电压stud双头螺栓synchronousmotor同步电动机subcontractor分包商synchronous同步的,同期的sub-transient超瞬变syphon弯管,吸水管system系统temperaturesensor温度传感器tachometer转速装置temperature温度tagpiece标号片temporarily临时地tailchopped截波temporary临时tamper搭子tension张力,拉力,拉伸tangential切线的tensioner拉紧器tankleakagetest箱体泄漏测试tensioning拉伸tank箱terminalbox接线盒tanδ介质损耗terminalclamp线夹tapchanger换档开关terminalpiece接头片tapercover锥形罩terminal接线端,端子taperend锥端terminator终结器taperpin锥销terylene涤纶taper丝锥testcertificate试验证明tape卷尺testhead打压闷头tapping攻丝testmode试验模式tap-position分接位置testpiece试块tap塞子,丝锥test-run试运行tarpaulin防水油布test试验technicaldata技术参数theodolite经纬仪technicalinstruction技术指导theorem原理technicalpersonnel技术人员thermaldevice温度计technical技术的thermalreplica热复制technology工艺,技术thermometer测温计teetube三通管thickness厚度teethclamping压板thiniron薄铁皮tee三通threadtube攻丝管TEMP.detector测温器thread螺纹temperaturemonitoring温度监视仪threadedbolt全丝扣螺栓temperaturerisethreadedpin螺纹销钉threadedrod螺杆torque扭矩,转矩thread线torsion力矩threephasetransformer三相变压器totalClearance总间隙three-phaseSquirrel-cage-Motors三相鼠total总计的,全体,总数笼式电动机touchscreen触摸屏three-waycontrolvalve三向控制阀track锁钩throttleplate节流板train培训throttlevalve节流阀transducer传感器,变换器throttling节流transferredsurgemeasurement thrustandlowerguidebearing推力下导transfer转换thrustbearingpads推力瓦transformer变压器thrustbearing推力轴承transient瞬变thrustblock推力头transmission传动thrust推力transmitter传感器thunderandlightning雷电transverse横向的,横断的thyristorbridge可控硅整流桥trigger触发thyristor半导体闸流管tripcircuit跳闸电路tightening上紧,固定tripfieldbreaker跳灭磁开关tight不漏tripping平稳的timeconstant时间常数trip跳闸tolerance公差T-shapedpipe三通管toluene甲苯tubeplate管板toothpitch齿距tube管,套管tooth齿T-unionT型接头topcoat面漆turbinebearing(metal)水轮机轴承toplayer上层turbineguidebearing水导轴承topview俯视图turbineshaft水轮机轴top-up修改turbine水轮机top上部,顶部turninsulation匝间绝缘torquespanner/wrench扭力扳手turn转,转动,一圈,一匝type方式,型号vane叶片U/F幅/频variable变量的U-boltclamppipeU型管架various不同的under(lower)下面的,下部的varistorvoltage变阻器电压underexcitation欠励磁vectorgroup连接组undervoltage欠压vehicle交通工具,车辆unearthed未接地的velocity速度unloadvalve卸载阀vendor卖主un-saturation不饱和的ventilationsegment通风槽片upguidebearing上导轴承ventilation通风,流通空气upto至vent通风孔,通风upperbearing(metal)上导轴承verify核实upperbracket上机架verniercaliper游标卡尺upperbushes上轴套verticalrib立筋uppercoverplate上盖板vertical垂直的uppercoveringcomplete上挡风板via经,通过,经由upperguidebearingsegment/pad上导瓦vibration振动upperguidebearing上导轴承view视图upperlimit上限viscosity粘性,粘度upperoilcooler上导油冷器visualcheck外观检查,目视检查uppersealchamber上密封罩voltagelevel电压等级uppershaft上端轴voltageregulationmode电压调节模式upperslinger上挡油圈voltagetransformer电压互感器upper上面的voltage电压upstream上游Voltmeter电压表usualcoil普通线圈volume体积,容积V/FlimitationV/F限制wafer圆片vacuumtest抽真空试验warrant授权valid有效的,有根据的,正当的,正确的washer垫圈valve阀门wateralarmunit油混水waterflow水流量workingtemperature工作温度waterinlet进水worksorderNo.工厂订货号wateroutlet出水wrapofspiralcase蜗壳包角waterpiping水管路wrench扳钳,扳手waterpressure水压yield产生watertank水箱Zener齐纳击穿(在半导体中的一种非破waveform波形坏性击穿)e序WE=waterequivalent水当量zerosequenc零wearingring抗磨环zero-sequenceimpedance wedgecarriers键槽板zinc-plating镀锌wedgeliner楔子板zinc锌wedgeplate楔子板wedge楔子,槽楔weight重量weld焊接weldingplate焊接板weldingrod焊条welding焊接wicketgatelever导叶拐臂wicketgateposition导叶开度wicketgate活动导叶width宽度,阔windductsheet通风槽片wind-age风阻损耗windingspannertool压线工具winding绕组wiring配线withstand承受woodenplug木塞woolenfelt工业毛毡。
Application Note No. 077 Thermal Resistance CalulationEdition 2007-01-08Published byInfineon Technologies AG81726 München, Germany© Infineon Technologies AG 2007.All Rights Reserved.LEGAL DISCLAIMERTHE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. INFINEON TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND (INCLUDING WITHOUT LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY) WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE.InformationFor further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office ().WarningsDue to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustainApplication Note No. 077Revision History: 2007-01-08, Rev. 2.0Previous Version:Page Subjects (major changes since last revision) All Document layout changeThermal Resistence1Thermal ResistenceThe heat caused by the power loss P tot in the active semiconductor region during operation results in an increased temperature of the component. The heat is dissipated from its source (junction J or channel Ch) via the chip, the case and the substrate (pc board) to the heat sink (ambient A). The junction temperature T J at an ambient temperature T A is determined by the thermal resistance R thJA and the power dissipation P tot.(1) (with R thJA in K/W or °C/W)Figure1Package on substrate2RF and AF Transistors an Diodes in SMD PackagesIn SMD packages the heat is primarily dissipated via the pins. The total thermal resistance in this case is made up of the following components:(2)(3)Table1RthJAThermal resistance between junction and ambient (total thermal resistance)R thJS Thermal resistance between junction and soldering pointT J T A P tot+R thJA×=AN077_package_substrate.vsdR thJa R thJT R thJS R thSA++=R thJS R thJT R thTS+=R thJS contains all type-dependent quantities. For a given power dissipation P tot it is possible to use it to precisely determine the component temperature if the temperature T S of the hottest soldering point is measured (for bipolar transistors typically the collector, for FETs the source lead).(4)The temperature of the soldering point T S is determined by the application, i.e. by the substrate, heat produced by external component and the ambient temperature T A . These components combine to form the substrate thermal resistance R thSA that is circuit-dependent and can be influenced by heat dissipation measures.(5)If measurement of the temperature of the soldering point T S is not possible, or if estimation of the junction temperature is suffecient, R thSA can be read from diagrams below. Here we give an approximate value of the thermal resistance between the soldering point on an epoxy or ceramic substrate and still air as a function of the area of the collector mounting or ceramic. The parameter is the dissipated power, i.e. the heat T S-T A of the pc board. So in this case for the operating temperature:(6)In the data sheets R thJS is stated as a thermal reference quantity of the heat dissipation. The total thermal resistance R thJA is started for comparison purposes. Depending on the typical component application, substrates of the following kinds are used for reference:•AF applications epoxy circuit board: collector mounting area in cm 2 Cu (see data sheet), thickness 35 µm Cu.•RF applications ceramic substrate: 15 mm × 16.7 mm × 0.7 mm (alumina) or epoxy circuit board with collectormounting area corresponting to 80 K/W.The two diagrams below show, to an approxmation, the thermal resistance as a function of the substrate area,assuming that the test device is located in the center of a virtually square substrate.R thJTThermal resistance between junction and chip base (chip thermal resistance)R thTSThermal reistance between chip base and soldering point (package/alloy)R thSA Termal resistance between soldering point and ambient (substrate thermal resistance)Table 1T J T S P tot R trhJS×+=T S T A P tot R thSA×+=T J T A P tot R thJS (R thSA )+×+=Figure 2Heat Dissipation from PC Board to Ambient Air (mounting pad Cu 35µm / substrate: epoxy1.5mm)Figure 3Heat Dissipation from AI 2O 3-Substrate to Ambient Air (substrate in still air, vertical 0.6 mmthick)2.1Temperature Measuring og Components Leads2.1.1Measuring with temperature indicators (e.g. thermopaper)Temperature indicators do not cause heat dissipation and thus allow an almost exact determination of temperature. A certain degree of deviations can only result from roughgrade indication of the temperature indicators. This method is quite easy and provides suffecient accuracy. It is particularly suitable for measurement in pc boards.2.1.2Measuring with thermocouple elementsMeasurement with thermocouple elements is not advisable because the functioning of the circuit can be influenced by electrical conduction and heat dissipation at the soldering point. This corrupts the results of the measurement,unless the measurement is carried out with appropriate effort.AN077_RthSA(Collector-pad).vsdAN077_RtfSA(Substrate).vsd2.2Permissible Total Dissipation in DC OperationThe total power dissipation P tot defines the maximum thermal gradient in the component. As a result of the heating of components, the maximum total power dissipatiopn P tot max stated in the data sheets is only permissible up to limits of T S max or T A max . These critical temperatures describe the point at which the maximum permissible junction temperature T J max is reached. The maximum permissible ambient or soldering-point temperature is calculated as follows:(7)(8)In diodes the power dissipation is for the most part caused by internal resistance. So the diagram has to be translated into the form I F =f (T S ; T A ), resulting in the bent shape of the curve. For R thJA the appropriate standard substrate was taken in each case. The diagrams shown here are intended as examples. For the application the curve given in the data sheet is to be taken. Exceeding the thermal max. ratings is not permissible because this could mean lasting degradation of the component’s characteristics or even its destruction.1) AI 2O 3-Subtrate 15 mm × 16.7 mm × 0.7 mm / Package mounted on alumina 15 mm × 16.7 mm × 0.7 mm Total Power Dissipation P tot =f (T S ;T A 1))Forward Current I F =f (T S ;T A 1))T Smax T Jmax P totmax R thJS×–=T Amax T Jmax P totmax R thJA×–=AN077_Ptot(TA).vsdAN077_If(TA).vsd2.3Permissible Total Power Dissipation in Pulse OperationIn pulse operation, under certain circumstances, higher total power dissipation than in DC operation can be permitted. This will be the case when the pulse duration t P, i.e. the length of time that power is applied, is small compared to the thermal time constant of the system. This time constant, i.e. the time until the final temperature is reached, depends on the thermal capacitances and resistances of the component’s chip, case and substrate. The thermal capacitance utilized in the component is a function of the pulse duration.Here we describe this through the transient thermal resistance. The pulse-load thermal resistance, or the permissible increase in P tot that can be derived from it, is shown by way of examples in the following curves. For the application the particular data sheet should be taken.(9) The duty factor t P/T is given as a parameter for periodic pulse load with a priod of T. For long pulse durations the factor P tot max/P tot DC approaches a value of 1, i.e. P tot in pulsed operation can be equated with the DC value. At extremely short pulse widths, on the other hand, the increase in temperature as a result of the pulse (residual ripple) becomes negligible and a mean temperature is created in the system that corresponds to DC operation with average pulse power.Permissible Pulse LoadR thJS = f(t P)Permissible Pulse LoadPtot maxIPtot DC= f(t P)P totmax P totDC⁄f t P)(=AN077_RthJS(TP).vsd AN077_Ptotmax-PtotDC(TP).vsd。
L IN F INITY Application NoteAN-8 Hiccup Mode CurrentLimitingApplication NoteI NTRODUCTIONHiccup-mode is a method of operation in a power supply whose purpose is to protect the power supply from being damaged during an over-current fault condition. It also enables the power supply to restart when the fault is removed. There are other ways of protecting the power supply when it is over-loaded, such as the maximum current limiting or current foldback methods.One of the problems resulting from over current is that excessive heat may be generated in power devices, especially MOSFET’s and Schottky diodes and the temperature of those devices may exceed their specified limits. A protection mechanism has to be used to prevent those power devices from being damaged.A LTERNATE O VER C URRENTP ROTECTION M ECHANISMSMaximum Current LimitingIn this method, the load current is limited to a set maximum value when the load current demand is higher than that value. As result, the output voltage will drop. The output voltage and load current relationship is shown in Figure 1. Power dissipation in the power supply is usually higher in the current limiting stage than in normal operation, i.e. the power dissipation at point B, as shown in Figure 1, is larger than that at point A. In order to protect the power supply, the system must be designed to handle the worst case thermal dissipation at point C.Current FoldbackCurrent foldback protection reduces the load current when the over-current fault occurs. The IV curve is shown in Figure 2. Because of the current foldback, the worst power dissipation is at point A, hence, the heat sink in this case is smaller than that in the maximum current limiting case. The drawback, however, is that it provides less current at start up, hence the output rises slower, or the power supply may not start up at all if the load current during start up is larger than the foldback current.H ICCUP M ODE O PERATIONThe operation of hiccup is as follows. When the current-sense circuit sees an over-current event, the controller shuts off the power supply for a given time and then tries to start up the power supply again. If the over-load condition has been removed, the power supply will start up and operate normally; otherwise, the controller will see another over-current event and shut off the power supply again, repeating the previous cycle. Hiccup operation has none of the drawbacks of the other two protection methods, although its circuit is more complicated because it requires a timing circuit. The excess heat due to overload lasts for only a short duration in the hiccup cycle, hence the junction temperature of the power devices is much lower.The hiccup operation can be done in various ways. For example, one can start hiccup operation any time an over-current event is detected; or prohibit hiccup during a designated start-up interval (usually a few milliseconds). The reason for the latter operation is that during start-up, the power supply needs to provide extra current to charge up the output capacitor. Thus the current demand during start-up is usually larger than during normal operation and it is easier for an over-current event to occur. If the power supply starts to hiccup once there is an over-current, itFigure 1: I-V curve for a power supply with maximumcurrent limitingFigure 2: I-V curve of a power supply with current foldbackcontroller, hiccup mode is inhibited during start up. Figure 3 shows the equivalent hiccup circuit of LX1668. The external soft-start capacitor C SS is used as the timing capacitor for hiccup. C SS will be discharged by R2 (200kΩ -10 times larger than R SS of 20kΩ) during the hiccup operation. During normal operation, any over-current event will produce a current-reset (C RESET) signal to reset the flip-flop and starts discharging C SS through R2. When the voltage of C SS is less than 95% of V SET, however, the C reset signal is prohibited by the AND gate. The inductor current in the buck power stage is limited by the current comparator (refer to the LX1668 data sheet). The C SS voltage and the inductor current waveforms are the ones shown in Figure 4.T HERMAL R EQUIREMENTSThe following section analyzes the thermal requirements of a buck converter with hiccup-mode over-current protection and compares it with the current limiting and the current examine the thermal model of a MOSFET.Thermal Model of a MOSFETFigure 5 shows the thermal model of a MOSFET. The top block represents the junction, which is the source of the heat. The second block is the case of the MOSFET. The third one is the heat sink or the PCB if the MOSFET is surface-mounted. The bottom one is the ambient. Between these blocks are “thermal resistors” (whose values are specified in MOSFET and heat sink data sheets). The heat generated in the junction is dissipated through the thermal resistors to ambient and temperature differences are established between the blocks. The capacitors in Figure 5 represent the thermal capacitance of the case and heat sink. The objective of thermal design is to choose the overall thermal resistance in the heat dissipation path, mainly R3 in Figure 5, so that the temperature in the junction is within certain limit. Of course, this design is done with specified heat power in the junction. The smaller the power dissipated, the smaller the heat sink required.The temperature can be calculated using the electrical equivalent model shown in Figure 6. The counterpart of the temperature in electrical model is the voltage and the heat power in the thermal model is equivalent to a current source in the electrical model. Figure 6 also gives the typical values for the thermal resistors, where R3 = 50Ω(the unit of thermal resistance is °C/W) is the thermal resistance of the PCB with one square inch of copper. C1 is neglected and C2 is selected to be 0.02 because the thermal time constant of the heat sink is in the order of one second. The ambient temperature is usually constant therefore is represented by a voltage source V1. When a steady heat is generated in the junction, the junction temperature can be found as,∑=+⋅=31iA ih jT RP T (1)where T j is the junction temperature, P h is the heat power, and T A is the ambient temperature. For example, if 1W heat is generated in the junction, the ambient temperature is 50 °C, then the temperature at the junction is T j = 1W*(2+0.5+50)°C/W +50°C = 102.5°C.C OMPARISON OF P ROTECTIONM ECHANISMSA standard buck converter is used as an example to demonstrate the thermal requirement for each method. Assume that the buck converter is designed for maximum load current of 20A, 5V input, and 2.5V output. The Schottky diode has 0.4V forward voltage drop. Then the worst-case power loss on the diode under normal operation isWVADVIP DOh45.04.020max,=⋅⋅=⋅⋅= (2)where D = 0.5 is the duty ratio for the diode. Therefore, the heat sink should be selected to dissipate 4W heat. Assume that the maximum ambient is 50°C and the maximum temperature at the junction is 125°C to operate safely, then the overall thermal resistance is (125-50)/4 = 18.75°C/W. One needs to select a heat sink with thermal resistance of 18.75-2.5 = 16°C/W for the diode. If the load current increases further, so will the temperature. Thus, the current has to be limited to prevent any further temperature rise.Hiccup Mode OperationAny further current increase will lead to shutting off of the converter. In this case, no further temperature rise will occur and the heat sink mentioned above is sufficient.Maximum Current LimitingWith current limiting, any further increase in load current will cause the output voltage to drop. As an extreme case, when the output is short-circuited, the output voltage will drop to zero. The on duty ratio of the MOSFET for this case is 0% and the on duty ratio for the Schottky diode is 100%. The current, determined by the limiting value, is constant. The heat power in this case is,WVADVIP DOh80.14.020max,=⋅⋅=⋅⋅= (3)In order for the heat sink to accommodate this worst case, the heat sink needs a thermal resistance of (125-50)/8 -2.5 = 6.875°C/W – a much larger heat sink!Current FoldbackAs shown in Figure 2, this method reduces the output current as the output load increases. Assuming the foldback current is only 1/3 of the maximum current when the output voltage is zero, the heat generated when the output is short-circuited isDVIP DOh××=max,31 (4)JunctionCasePCB/Heat sinkAmbientC1WV A P h 67.20.14.02031=×××=The worst case condition, from a thermal standpoint, is still the 4W required for normal operation at maximum current, so the same heat sink is required operation for heat dissipation as would be needed in a circuit with hiccup mode protection. The drawback for the foldback method is that at start up, the current is only one third of the maximum current. Therefore, the power supply will start up much more slowly or may possibly be unable to start up if the load demands a current larger than the foldback current.The three methods are summarized in the following table.MethodStart up Current Max. Heat Sink Power DissipationCircuit Complexity CommentsHiccupI max 4W High Best performance Current Limiting I max 8W Low Simplest circuitCurrent Foldback I max /34WMediumCan not start up with a constant current loadC ONCLUSIONHiccup mode protection will give the best protection for a power supply against over current situations, since it will limit the average current to the load at a low level, so reducing power dissipation and case temperature in the power devices. Its complexity is higher, requiring some extra silicon in the controller IC. However, to the system designer, the added complexity is negligible and provides significant circuit protection benefits.The LX1668 programmable switching regulator from Linfinity uses hiccup mode protection to guard against excessive currents.F URTHER INFORMATIONFor datasheets and other application notes, please visit Linfinity’s web site at or use Linfinity’s Fax Back service at 1 (714) 372-3848.Evaluation kits for the LX1668 and other devices are available upon request from Linfinity’s representatives and distributors.。
电源管理芯片测试方法标准英文回答:Power Management IC (PMIC) Testing Methodology Standards.PMICs are essential components in electronic devices, responsible for regulating and managing power distribution efficiently. To ensure the reliability and performance of PMICs, a standardized testing methodology is crucial. This methodology outlines the procedures and techniques used to evaluate the various aspects of PMICs, including their electrical, thermal, and functional characteristics.Functional Testing.Functional testing verifies the basic functionality of a PMIC, such as its ability to generate and regulate voltages, switch between different power modes, and protect against over-current and over-voltage conditions. Thistesting involves applying specific input signals and observing the corresponding output responses.Electrical Testing.Electrical testing evaluates the PMIC's electrical characteristics, such as its efficiency, power dissipation, and output voltage regulation. This testing involves measuring various electrical parameters under different operating conditions and comparing them with the specified limits.Thermal Testing.Thermal testing assesses the PMIC's ability todissipate heat effectively and maintain its temperature within acceptable limits. This testing involves subjecting the PMIC to increased power loads and monitoring its temperature using thermal sensors.Other Testing Methods.In addition to the above-mentioned testing methods, PMICs may also undergo other tests, such as:Environmental testing: Exposing the PMIC to different environmental conditions, such as extreme temperatures, humidity, and vibration, to assess its robustness.Failure analysis: Analyzing failed PMICs to identify the root cause of failures and improve future designs.Statistical testing: Performing statistical analysis on PMIC samples to determine their yield, reliability, and manufacturing consistency.Standardization.Standardizing PMIC testing methodologies ensures that different laboratories and manufacturers use the same procedures and equipment, leading to consistent and reliable test results. This enables the comparison of different PMIC products and facilitates the development of more efficient and reliable power management solutions.中文回答:电源管理芯片(PMIC)测试方法标准。
电工翻译词汇D235digital feedback system,数字反馈系统digital filter,数字滤波器digital fluxmeter,数字磁通表digital frequency meter,数字频率表digital information processing system,数字信息处理系统digital input,数字输入digital integrating fluxmeter,数字积分式磁通表digital logging instrument,数字测井仪digital magnetic tape record type strong-motion instrument, 数字磁带记录强震仪 digitalmagnetic telluro sounding instrument,数字大地电磁测深仪digital measuring instrument,数字式测量仪器仪表digital multimeter,数字万用表;数字复用表digital ohmmeter,数字电阻表digital ouput,数字输出digital phase meter,数字相位表digital position transmitter,数字式位置发送器digital positioner,数字式定位器digital power driver,数字功率表digital pressure gauge,数字压力表digital readout,数字读出digital representation of a physical quantity,物理量的数字表示digital seismic recoridng system,数字地震仪digital signal,数字信号digital signal analyzer,数字信号分析仪digital signal processing,数字信号处理digital simulation,数字仿真digital simulation computer,数字仿真计算机digital strain indicator,数字应变仪digital system,数字系统digital telemetering system,数字遥测系统digital transducer[sensor],数字传感器digital valve,数字阀digital voltmeter,数字电压表digital-analog conversion,楼模转换(digital-analog)hybrid computer,(数字模拟)混合计算机digital-analog simulator,数字模拟仿真器digital-analogue converter;D/A converter,数-模转换器;D/A 转换器digitalization error,数字化误差digitization,数字化digitization error,数字化误差digitizer,数字化仪dilatometry,膨胀法diluent gas,稀释气dilution factor,稀释因数36dilution methods,稀释法dilution ratio[rate],稀释比[率]dimension,尺度dimension transducer[semsor],尺度传感器Dines anemometer,达因风速表diopter,视度dip logger,地层倾角测井仪direct acting instrument,直接作用仪表direct acting recording instrument,直流作用记录仪direct action,正作用direct action solenoid valve,直动式电磁阀direct actuator,正作用执行机构direct-comparison method of measurement,直接比较测量法direct control layer,直接控制层direct-current linear variable differential transformer(DC-DC LVDT), 直流差动变压器 directdigital control station ,直接数字控制站direct digital control,直接数字控制direct heated type thermistor,直热式热敏电阻器direct-imaging mass analyser,直接成象质量分析仪direct injection burner,直接注入燃烧器direct injector,直流进样器direct method of measurement,直接测量法direct mounting gauge,直接安装压力表direct-operated regulator,直接作用式调节阀;自力式调节阀direct probe inlet,直接探头进样direct reading current meter,直读式海流计direct reading instrument,直读式仪器direct record strong-motion instrument,直接记录式强震仪direct resistance heating,直接电阻加热direction focusing,方向聚焦direction indicator,中心指示器direction mark meter,方位标仪directional frequency response of microphone,传声器指向性频率响应directional pattern of microphone,传声器指向性图案directivity,指向性directivity index of microphone,传声器指向性指数directly controlled system,直接被控系统directly controlled variable,直接被控变量director,指挥站disappearing-filament optical pyrometer,隐丝式光学高温计disc,阀板disc plug,盘形阀芯disc recorder,圆盘(形)记录仪discharge coefficient,流出系数37discharge lamp,放电灯discontinuous control,不连续控制discontinuous control system,不连续控制系统discontinuous simultaneous techniques,间歇联用技术;不连续同时串用技术discrete control system,离散控制系统discrete signal,离散信号discrete system model,离散系统模型discrete system simulation,离散系统仿真discrete system simulation language,离散系统仿真语言discriminant function,判别函数discrimination,鉴别力discrimination threshold,鉴别力阀diskette,软磁盘dispersion dose,散射剂量dispersion power,色散本领dispersive crystal,分光晶体dispersive infra-red gas analyzer,色散红外线气体分析器displacement,位移displacement divelopment,顶替展开法displacement pickup,位移传感器displacement transducer[sensor],位移传感器displacement,velocity and acceleration shock response spectrum, 位移、速度和加速度冲击响应谱display attribute,显示属性display console,显示控制台display device,显示器;显示设备display element,显示元件display unit,显示单元dissipation constant,耗散常数dissipation power,耗散功率dissolved oxygen analyzer,溶解氧分析器dissolved oxygen analyzer for seawater,海水溶解氧测定仪dissolved oxygen of seawater,海水中的溶解氧distance amplitude compensation,距离振幅补偿distance amplitude curve,距离振幅曲线distance constant,距离常数distance factor,距离系数distance marder,距离刻度distance meter,测距仪distance of centre of gravity,重心距distorted peak,畸峰distortion,失真;畸变distributed computer-control SDAS,分布式遥测型数字地震仪distributed computer control system, 分散型计算机控制系统;分布式计算机控制系统38distributed control,分散控制;分布控制distributed control system,分散型控制系统;分布式控制系统distributed data base,分布式数据库distributed intelligence,分散智能 distributed networkm,分布式网络distributed parameter control system,分散[分布]能数控制系统distributed telemetry SDAS,分布式遥测型数字地震仪distribution temperature,分布温度disturbance,扰动dither,颤振dithering,颤动diverging three way valve,三通分流阀diverter,换向器diving bell,潜水钟document.文件;文献document.tion,文件管理;文件集domestic package,内销包装dominant frequency,优势频率;主频率Doppler current meter,多普勒海流计Doppler effect,多普勒效应Doppler flowmeter,多普勒流量计Doppler radar,多普勒雷达Doppler sonar,多普勒声纳dose,剂量dose rate,剂量率dose rate meter,剂量率计dosementer,剂量计dot matrix printer,点阵式打印机dot printer,点阵印刷机;点阵打印机dotted line recorder,断续线记录仪dotting time,打点时间double acting positioner,双作用定位器double-beam mass spectrometer,双束质谱计double beam spectrum radiator,双光束光谱福射计double bounce technique,二次反射法double collectors,双接收器double-cone viscometer,双锥粘度计double crystal probe,双振子探头double-dry calorimeter,双干式热量计double-focusing mass spectroscope,双聚焦质谱仪器double-focus X-ray tube,双焦点X 射线管double focusing,双聚焦double focusing analyzer,双聚焦分析器double focusing at all masses,全质量双聚焦double-image tacheometer,双像速测仪。
The Power of Comparative AnalysisComparative analysis is a valuable tool that enables us to gain a deeper understanding of subjects by comparing and contrasting them. This approach is widely used in various fields, including literature, science, history, and even daily life.In literature, for instance, comparative analysis can be employed to compare and contrast different works of the same author, or works from different authors, periods, or genres. By doing so, readers can appreciate the unique stylistic choices, themes, and motifs that authors employ, and how they contribute to the overall effect of the work.In science, comparative analysis is equally important. Scientists often compare and contrast different species, theories, or experiments to gain insights into the natural world. By identifying similarities and differences, they can make informed predictions, test hypotheses, and refine their understanding of scientific phenomena.In daily life, we also make use of comparative analysis unconsciously. For example, when shopping for a new car, we might compare and contrast different models, brands, and features to find the best fit for our needs. Similarly, when considering career options, we might compare job requirements, salaries, and potential growth opportunities to make an informed decision.The power of comparative analysis lies in its ability to help us see patterns, trends, and connections that might not be apparent at first glance. By comparing and contrasting different subjects, we can gain a more comprehensive understanding of the world and make more informed decisions. Whether in literature, science, or daily life, comparative analysis is a critical skill that can enhance our understanding and appreciation of the world around us.对比法是一种有价值的工具,它使我们能够通过比较和对比不同的事物来更深入地理解它们。
a r X i v :c o n d -m a t /9910062v 3 [c o n d -m a t .m e s -h a l l ] 27 A p r 2000Decoherence of the Superconducting Persistent Current Qubit Lin Tian 1,L.S.Levitov 1,Caspar H.van der Wal 4,J.E.Mooij 2,4,T.P.Orlando 2,S.Lloyd 3,C.J.P.M.Harmans 4,J.J.Mazo 2,51Dept.of Physics,Center for Material Science &Engineering,2Dept.of Electrical Engineering and Computer Science,3Dept.of Mechanical Engineering,Massachusetts Institute of Technology;4Dept.of Applied Physics and Delft Institute for Microelectronics and Submicron Technologies,Delft Univ.of Technology;5Dept.de F´ısica de la Mataeria Condensada,Universidad de Zaragoza (February 1,2008)Decoherence of a solid state based qubit can be caused by coupling to microscopic degrees of freedom in the solid.We lay out a simple theory and use it to estimate decoherence for a recently proposed superconducting persistent current design.All considered sources of decoherence are found to be quite weak,leading to a high quality factor for this qubit.I.INTRODUCTION The power of quantum logic [1]depends on the degree of coherence of the qubit dynamics [2,3].The so-called “quality factor”of the qubit,the number of quantum operations performed during the qubit coherence time,should be at least 104for the quantum computer to allow for quantum error correction [4].Decoherence is an especially vital issue in solid state qubit designs,due to many kinds of low energy excitations in the solid state environment that may couple to qubit states and cause dephasing.In this article we discuss and estimate some of the main sources of decoher-ence in the superconducting persistent current qubit proposed recently [3].The approach will be presented in a way making it easy to generalize it to other sys-tems.We emphasize those decoherence mechanisms that illustrate this approach,and briefly summarize the results of other mechanisms.The circuit [3]consists of three small Josephson junctions which are connected in series,forming a loop,as shown in Fig.1.The charging energy of the qubits E C =e 2/2C 1,2is ∼100times smaller than the Josephson energy E J =¯h I 0/2e ,where I 0is the qubit Josephson critical current.The junctions discussed in [3]are 200nm by 400nm,and E J ≈200GHz.1FIG. asbyε0≈is≃The theH0=−ε0/2t(q1,q2)t∗(q1,q2)ε0/2,(1)where t(q1,q2)is a periodic function of gate charges q1,2.In the tight binding approximation[3],t(q1,q2)=t1+t2e−iπq1/e+t2e iπq2/e,where t1is the amplitude of tunneling between the nearest energy minima and t2is the tunneling between the next nearest neighbor minima in the model[3].Both t1and t2depend on the energy barrier height and width exponentially.With the parameters of our qubit design,t2/t1<10−3,the effect offluctuations of q1,2should be small.Below we consider a number of decoherence effects which seem to be most rele-vant for the design[3],trying to keep the approach general enough,so that it can be applied to other designs.2II.BASIC APPROACHWe start with a Hamiltonian of a qubit coupled to environmental degrees of freedom in the solid:H total=H Q( σ)+H bath({ξα}),where H Q=H0+H coupling:¯hH Q=∆· σby going to the frame rotating around the z−axis with the Larmor 2frequency∆=| ∆|.In the rotating frame the Hamiltonian(2)becomes:3H Q=¯hη (−ω)η (ω) (6)2πω2|φ⊥(t)|2 = dω|1−e iωt|2In thermal equilibrium,by virtue of the Fluctuation–Dissipation theorem,the noise spectrum in the RHS of (6)and (7)can be expressed in terms of the out-of-phase part of an appropriate susceptibility.III.ESTIMATES FOR PARTICULAR MECHANISMSHere we discuss the above listed decoherence mechanisms and use the expressions(6)and (7)to estimate the corresponding decoherence times.We start with the effect of charge fluctuations on the gates due to electromagnetic coupling to the environment modeled by an external impedance Z ω(see Fig.1),taken below to be of order of 400Ω,the vacuum impedance.The dependence of the qubit Hamiltonian on the gate charges q 1,2is given by (1),where q 1,2vary in time in response to the fluctuations of gate voltages,δq 1,2≈C g δV g (1,2),where the gate capacitance is much smaller than the junction capacitance:C g ≪C 1,2.The gate voltage fluctuations are given by the Nyquist formula: δV g (−ω)δV g (ω) =2Z ω¯h ωcoth ¯h ω/kT .In our design,|t (q 1,q 2)|≪ε0,and therefore fluctuations of q 1,2generate primar-ily transverse noise η⊥in (3),η⊥(t )≃(2π/¯h e )t 2C g δV g (t ).In this case,according to(7),we are interested in the noise spectrum of δV g shifted by the Larmor frequency ∆.Our typical ∆≃10GHz is much larger than the temperature k B T/h =1GHz at T =50mK,and thus one has ω≃∆≫kT/¯h in the Nyquist formula.The Nyquist spectrum is very broad compared to Larmor frequency and other relevant frequency scales,and thus in (7)we can just use the ω=∆value of the noise power.Evaluating |(1−e iωt )/ω|2dω=2πt ,we obtainR (t )= |φ⊥(t )|2 =2te t 2C g 2∆Z ω=∆(8)Rewriting this expression as R (t )=t/τ,we estimate the decoherence time asτ=∆−1¯h 2πC g t 2 2(9)where ¯h /2e 2≃4kΩ.In the qubit design e 2/2C g ≃100GHz,and t 2≃1MHz when t 2/t 1≤10−3.With these numbers,one has τ=0.1s.The next effect we consider is dephasing due to quasiparticles on supercon-ducting islands .At finite temperature,quasiparticles are thermally activated above the superconducting gap ∆0,and their density is ∼exp(−∆0/kT ).The contribution of quasiparticles to the Josephson junction dynamics can be modeled as a shunt resistor,as shown in Fig.1.The corresponding subgap resistance is inversely proportional to the quasiparticle density,and thus increases exponen-tially at small temperatures:R qp ≈R n exp ∆0/kT ,where R n is the normal state5resistance of the junction.For Josephson current I 0=0.2µA,R n ≈1.3kΩ.At lowtemperaturesthe subgap resistance is quite high,and thus difficult to measure[5].For estimates below we take R qp =1011Ωwhich is much smaller than what follows from the exponential dependence for T =50mK.The main effect of the subgap resistance in the shunt resistor model is generat-ing normal current fluctuations which couple to the phase on the junction.The Hamiltonian describing this effect isH qp coupling =i¯h 2¯h ∆ ε02kT (12)Taking R qp =1011Ω,T =50mK,and ε0/t 1=100,the decoherence times are τ =1ms and τ⊥=10ms.The decoherence effect of nuclear spins on the qubit is due to their magnetic field flux coupling to the qubit inductance.Alternatively,this coupling can be viewed as Zeeman energy of nuclear spins in the magnetic field B(r )due to the qubit.The two states of the qubit have opposite currents,and produce magnetic field of opposite sign.The corresponding term in (2)isH coupling =−σzr =r iµ B (r )· s (r )(13)where r i are positions of nuclei,µis nuclear magnetic moment and s (r i )are spin operators.Nuclei are in thermal equilibrium,and their spin fluctuations can be related to the longitudinal relaxation time T 1by the Fluctuation-Dissipation theorem.Assuming that different spins are uncorrelated,one hass ω(r )s −ω(r ) =2k B T χ′′(ω)1+ω2T 21,(14)6whereχ0=1/k B T is static spin susceptibility.The spectrum(14)has a very narrow width set by the long relaxation time T1.This width is much less then k B T and∆.As a result,only longitudinal fluctuationsη survive in(6)and(7).One hasφ2 (t) = dω|1−e iωt|2τ20 |t|−T1+T1e−|t|/T1 ,(16)τ0= 2µ2A similar theory can be employed to estimate the effect due to magnetic im-purities.The main difference is that for impurity spins the relaxation time T1is typically much shorter than for nuclear spins.If T1becomes comparable to the qubit operation time,the ensemble averaged quantities will describe a real dephas-ing of an individual qubit,rather than effects of inhomogeneous broadening,like for nuclear spins.IV.OTHER MECHANISMSSome sources of decoherence are not amenable to the basic approach considered above,such as radiation losses which we estimate to haveτ≃103s.Another such source of decoherence is caused by the magnetic dipole interaction between the qubits.This interaction between qubits is described byH coupling= i,j¯hλijσ(i)z⊗σ(j)z,¯hλij≈µiµjcan be made at least1ms which for f Rabi=100MHz gives a quality factor of105, passing the criterion for quantum error correction.In addition to the effects we discussed,some other decoherence sources are worth attention,such as low frequency chargefluctuations resulting from electron hopping on impurities in the semiconductor and charge configuration switching near the gates[8].These effects cause1/f noise in electron transport,and may contribute to decoherence at low frequencies.Also,we left out the effect of the acfield coupling the two low energy states of the qubit to higher energy states. Results of our numerical simulations of the coupling matrix in the qubit[3]show that Rabi oscillations can be observed even in the presence of the ac excitation mixing the states(to be published elsewhere).ACKNOWLEDGMENTSThis work is supported by ARO grant DAAG55-98-1-0369,NSF Award 67436000IRG,Stichting voor Fundamenteel Onderzoek der Materie and the New Energy and Industrial Technology Development Organization.[8]T.Henning et al.,Eur.Phys.J.B8.627(1999);V.A.Krupenin et al.,J.Appl.Phys.84,3212(1998);N.Zimmerman et al.,Phys.Rev.B56,7675(1997);E.H.Visscher et al,Appl.Phys.Lett.66,305(1995).10。
A Power Dissipation Comparison of the R-TDMAand the Slotted-Aloha Wireless MAC ProtocolsGeorge R.J. LinnenbankUniversity of Twente, Department of Computer ScienceP.O.Box 217, 7500 AE Enschede, the Netherlandslinnenba@cs.utwente.nlAbstractIn this paper two wireless multiple-access protocols are compared by theirpower dissipation for the uplink traffic of a wireless networks. After brieflydiscussing the behaviour of the Slotted Aloha protocol (Abramson, 1985)and the R-TDMA protocol (Linnenbank, 1995), we estimate the energy thatis dissipated by the protocols to trasmit a packet. We will show that for gen-eral loads, the power dissipation of the R-TDMA protocol is far less than thatof the Slotted Aloha protocol.1 IntroductionIn recent years more and more mobile wireless equipment is being used. Starting with the mobile wireless telephone and followed by the portable computer, emphasis is made on miniaturizing com-ponents to make devices lighter. One of the bottlenecks appears to be the battery that provides the device with energy. The amount of energy stored in the battery must be sufficient to make it worth-while to carry a mobile communication device with you. However, the smaller the device, the smaller the battery. Therefore, less energy can be provided. Power managent is one of the research areas of the Moby Dick project (Mullender, 1995). In this project several research fields are covered: security, network architecture, data consistency, environment awareness and power management. In this paper we focus on the power management.Research is focusing on power-efficient components and power-efficient algorithms to expand the time that a wireless device can be used. Using low-power components is one approach that helps to save scarce battery energy. Reducing the overhead of the multiple-access protocol is another way to reduce energy consumption.In this paper we will investigate the power dissipation of two multiple-access protocols: the Slotted Aloha protocol and the R-TDMA protocol. For each multiple-access protocol we briefly describe the model of the protocol and then we analyse the power dissipation of that protocol. Finally, we will compare the results and draw some conclusions.To obtain sensible results, it is necessary to fill in some properties and parameters of the wireless sys-tem. We have made the following assumptions:•The accuracy of the clock crystals is assumed to be perfect.•The channel bit rate is 1Mbps and the channel is assumed to be perfect (No noise present).•A data message is an ATM cell of 53 bytes or 424 bits long.•The activation time of the transmitter or receiver is neglected.•A single frequency channel is used.•The receiver and transmitter are switched off as much as possible to save energy.•We assume 1 that the transmitter consumes 10W and the receiver 1W .•Analyses are made from the view point of a single station.2 Slotted AlohaIn Slotted Aloha, time is divided into slots (Abramson, 1985). We use a slotsize such that a data mes-sage and its associated acknowledgement fit in a slot. Since mobile stations need to know that they are in a cell of a base station, the base station sends identification messages regularly. These mes-sages can be sent in a time slot that has not been used for a data transmission by a mobile station. I.e.the base station does not detect a carrier signal in the beginning of a slot. When the base station sends an identification message in every free slot, then a mobile station can detect a base station very fast (within a free slot time) and synchronise to that base station.Each slot is accessed with probability p by each mobile station. The aggregated load G = n*p , where n is the number of mobile stations. When the same assumptions are made that are often found in the literature, i.e. the aggregate network load does not change when a single station goes in back-off (asymptotically true for an infinite number of stations generating the aggregate load G ), then we can state that whether or not backoff is used, the probability of success of each data transmission does not change. The number of transmission attempts needed to send a data message remains unchanged but is only spread over a longer time period when back-off is used. Therefore, a backoff procedure is of no concern in the analysis of power dissipation.The Slotted Aloha protocol timing is as follows:•An acknowledgement is 1/8*424 = 53 bits large or 53µs long.•An identification message is 1/2 * 424 = 212 bits large or 212µs long.• A slot contains room for a data message and its associated acknowledgement and is 424+53=477bit times or 477µs long.1.In near-field radio experiments, the power dissipation was determined to be 10.0W for the transmitter and 1.0W for the receiver. During these experiments, no optimizations were made to make the transmitter or receiver more power efficient. These measurements are indicative for dissipation comparison of protocols.The analysis that we give is general and when more efficient dissipation figures are determined, these can easily be substituted in the equations.Figure 1.Slotted Aloha protocol timing2.1 Transmission dissipationThe energy dissipated through transmission is determined by the time that the transmitter has been transmitting. When a wireless station sends a message, the probability that it is successfully received at the base station is given by the formula(EQ 1)Where n is the number of active stations and p is the probability that a station sends a message in a slot. Then the average number of transmissions υ needed to send a message successfully is given by(EQ 2)For a single mobile station (n=1),υ=1 for all access probabilities p . Thus there is no transmission overhead in the case that there is only a single mobile station. Transmission overhead only occurs when there are more than one mobile stations. Using υ the average time T Tx that the transmitter is active per packet is easily determined to be(EQ 3)2.2 ReceptionThe receiver of a mobile station must be on in order to receive the identification message of a base station for base station detection and for time synchronisation. Also it must be on to receive possible acknowledgements after attempting to transmit a data message. We assume that a mobile station waits for an identification message only once. Therefore, the power dissipated to receive an identifi-cation message can be neglected.Every time the mobile station attempts to send a data message, the receiver of the mobile station is switched on to see if an acknowledgement is transmitted by the base station. After the time it requires to receive an acknowledgement (T ack ), the receiver is switched off until another data trans-mission attempt is made. Since the average number of transmissions attempts to send a single data message is known to be υ, the time T RxOn per packet that the receiver is switched on in order to detect an acknowledgement is given by(EQ 4)However, only the last of the υ transmission attempts was successful. Only after that data transmis-sion, the receiver successfully receives an acknowledgement. Therefore, the time per packet that a station is really receiving acknowledgements (T Rx ) is(EQ 5)Thus T Rx is a constant with the value 53µs.P succ ()1p –()n 1–=υ11p –()n 1–------------------------------1p –()1n –==T Tx υT data ⋅=T RxOn υT ack ⋅=T Rx T ack =2.3 DissipationThe total dissipation (measured in Watts or Joules) is given by the time that the transmitter is on, the receiver is on and the receiver is receiving a message, multiplied by the power dissipations of each of these functions. The total energy dissipation per packet P total is given by(EQ 6)Since the processing of the actually received information can be performed using low power compo-nents (in the order of microwatts), we can neglect P Rx . We apply the measured values to the formula of P total giving the graphs in Figure 2.3 Request-TDMAIn the R-TDMA protocol (Linnenbank, 1995), time is divided into fixed size frames. A frame con-tains S time slots for communication. The frame structure is shown in Figure 3. There are two special slot types in each frame, the Clear To Send (CTS) and the Request To Send (RTS) slots. The first slot in the frame is the CTS slot. The base station uses this slot to inform the mobile stations to which connections the data slots are allocated in the current frame . Somewhere in the frame is the RTS slot,where mobile stations can use minislots to request data slots for the next frame . The remaining S-2=D slots are the data slots which can be used for data communication.The timing used in the following analysis is as follows:•T slot = T data = T CTS = 53*8 = 424µs•T RTS = 3*8 = 24µs (17 minislots fit in a slot)•T frame = S * Tslot = 20*424 = 8480µs = 8.48msP total T Tx P Tx ⋅T RxOn P RxOn ⋅T Rx P Rx ⋅++=Figure 2.Slotted Aloha power dissipation per packet for 1..5 stations 0.000.010.020.030.040.050.00.20.40.60.8 1.0load (p)Slotted Aloha: PTx=10.0, PRxOn=1.0, PRx is neglected n=2n=3n=4n=5n=1P t o t a l (J o u l e s)Figure 3.The R-TDMA frame structureSince connections are set up only once at the start of a communication session, their contribution to the average energy dissipation per packet is neglectable. Therefore the connection setups are not included in the analysis.3.1 Transmission dissipationWhen the packet generation rate is p packets per slot, and the frame size is S , then the average number of packets generated per frame is pS . We assume that an RTS is only transmitted when a sta-tion has data to transmit. As the probability that a packet is generated is p per slottime, the probabil-ity that no packets are created in a frame is (1-p)S . Thus the probability P(RTS) that an RTS is transmitted is P(RTS)=1-(1-p)S .Per frame pS*T data + P(RTS)*T RTS time is used for transmission on average. Since there are pS packets per frame, the transmission time T Tx per packet is(EQ 7)As we assume that the channel is perfect and no collisions occur due to the contentionless protocol,this is all the time that energy is used for transmission. The transmission overhead in time per packet is given by P(RTS)*T RTS /(pS ). This overhead has a maximum of T RTS per packet for p =0 and decreases fast for higher loads.3.2 ReceptionIn a frame the CTS needs to be received to determine the slot allocation in the current frame. How-ever, when no RTS was transmitted, there is no need to receive the CTS message and the receiver can be left switched-off. Therefore, the probability P(CTS) that an CTS needs to be received is equal to the probability that an RTS was transmitted. Thus P(CTS)=P(RTS). On average P(CTS)*T data sec-onds is spent receiving per frame. Put against the number of packets per frame (pS ), the reception overhead becomes P(CTS)*T data /(pS)per packet. Expressing the reception overhead T RxOn in time per packet is given by(EQ 8)Again the overhead has a maximum for low values of p . The maximum reception overhead is T data for p=0 and decreases fast for higher values of p .3.3 Total dissipationAgain assuming that P Rx is outweighed by P RxOn by using very low-power processing components,the total dissipation P total per packet is given by the sum of the transmitter dissipation per packet and the receiver dissipation per packet.(EQ 9)T Tx pS T data ⋅P RTS ()T RTS +pS --------------------------------------------------------------------T data P RTS ()T RTS pS -----------------------------------+==T RxOn P CTS ()T data pS ------------------------------------=P total P Tx T Tx ⋅P RxOn T RxOn ⋅+=Applying the same values for transmission and reception dissipation as in Figure 2 (10W for trans-mission and 1W for reception), the following power dissipation graph is obtainedNote that it takes 424.0/106 seconds to send a single packet, thus the optimal dissipation per packet would be transmitting that packet only which gives 10W * 424.0/106s = 0.00424J per packet in the 10W transmitter and 1W receiver dissipation case. The graph shows that for all loads the dissipation is close to this optimum.4 ConclusionFirst of all we conclude that for the R-TDMA case, the power dissipation is independent of the activ-ity of other users, where in the Slotted Aloha case the power dissipation depends strongly on the activity of other users. Assuming that the network is not saturated, the performance of R-TDMA is also indepent of the number of users. In the Slotted Aloha case the number of users that generate a certain load influences the performance.Comparing the R-TDMA protocol to the Slotted Aloha protocol shows that the power efficiency is much better in the R-TDMA case. The overhead in R-TDMA is only relatively high under very low loads while the overhead of Slotted Aloha is ever increasing with higher loads (except for the opti-mal situation with 1 mobile station). Estimating the power dissipation when setting P Tx and P Rx both to 1W gives similar results.From the analyses we can conclude that R-TDMA outperforms Slotted Aloha under all but the low-est loads, except for the single user situation. In that case Slotted Aloha has the better performance.Figure 4.R-TDMA power dissipation per packet 0.000.010.020.030.040.050.00.20.40.60.8 1.0load (p)RTDMA: PTx=10.0, PRxOn=1.0, PRx is neglected RTDMA_Ptotal(x)P t o t a l (J o u l e s )Figure 5.Power dissipation per packet for equal receiver and transmitter dissipation 0.0000.0010.0020.0030.0040.0050.00.20.40.60.8 1.0load (p)Slotted Aloha: PTx=1.0, PRxOn=1.0, PRx is neglected P t o t a l (J o u l e s )0.0000.0010.0020.0030.0040.0050.00.20.40.60.8 1.0P t o t a l (J o u l e s )load (p)RTDMA: PTx=1.0, PRxOn=1.0, PRx is neglected5 References(Abramson, 1985)Abramson, N., Development of the ALOHANET, IEEE Transactions on Information Theory, vol. IT-31, pp. 119-123, March 1985. (Linnenbank, 1995)Linnenbank, G.R.J., et al.,Request-TDMA: A Multiple-Access Protocol for Wireless Multimedia Networks, Proceedings IEEE Third Symposium onCommunications and Vehicular Technology in the Benelux, Eindhoven, TheNetherlands, 1995.(Mullender, 1995)Mullender, S.J, Corsini, P., Hartvigsen, G., Moby Dick - The Mobile Digital Companion, LTR 20422, Annex I - Project Programme, December 1995.。