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浙江大学远程教育学院05-06年夏考试场安排表
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#include "ILI9163.h"//端口定义sbit CS =P2^0;sbit RST=P2^1;sbit RW =P2^2;sbit RS =P2^3;#define TFT_DATA P0//颜色定义unsigned int color[]={0xf800,0xffe0,0x07e0,0x07ff,0x001f,0xf81f,0x0000,0xffff,0x7bef};// 红黄绿青蓝紫黑白灰/******************************************************延时，小于0.5ms******************************************************/void delayms(unsigned int count) // x 10ms{unsigned int i;unsigned char j;for(i=0;i<count;i++)for(j=0;j<255;j++);}/******************************************************写寄存器ID的子程序******************************************************/void WriteCOM(unsigned char ID){RS=0;CS=0;TFT_DATA=0x00;RW=0;RW=1;TFT_DATA=ID;RW=0;RW=1;RS=1;CS=1;}/******************************************************写数据的子程序******************************************************/void WriteDAT(unsigned char HD,unsigned char LD) //写16位数据{RS=1;TFT_DATA=HD;RW=0;RW=1;TFT_DATA=LD;RW=0;RW=1;RS=0;CS=1;}void WriteDAT_8(unsigned char ddate) //写8位数据{RS=1;CS=0;TFT_DATA=ddate;RW=0;RW=1;RS=0;CS=1;}/****************************************************** 用于写字符，图线等*****************************************************/ void Write_Data_U16(unsigned int y){unsigned char m,n;m=y>>8; //高8位n=y; //低8位WriteDAT(m,n);}/****************************************************** IC ILI9163初始化******************************************************/ void ILI9163_init(void){RST=1;delayms(10);delayms(10);RST=1;delayms(10);WriteCOM(0x11);//退出睡眠模式delayms(10);WriteCOM(0x26);// Gammut format 伽马曲线设置WriteDAT_8(0x04);/* 04h GC3 Gammut 2.2，01h GC1 Gammut 1.0 , 02h GC2 gammut 1.8, 08h GC3 Gammut 2.5 */delayms(10);WriteCOM(0xB1); //帧频控制WriteDAT_8(0x06);WriteDAT_8(0x08);WriteDAT_8(0x09);WriteCOM(0xC0); //电源控制WriteDAT_8(0x04);WriteDAT_8(0x00);WriteCOM(0xC1); //电源控制WriteDAT_8(0x07);WriteCOM(0xC5); //偏压控制WriteDAT_8(0x4c); //vcom control 0x48,0x24 34 //2bWriteDAT_8(0x38); //vcom control 0x48,0x24 50 //47WriteCOM(0xC7); //偏压控制WriteDAT_8(0x40); //C4delayms(10);WriteCOM(0x3A); // Interface Pixel modeWriteDAT_8(0x05);/*0x05 16 bit/Pixel RGB 53-35 Twice per pixel for 80-8bits parallel0x06 18 bit/Pixel RGB 6-6-6 Three times per pixel for 80-8bits parallel */WriteCOM(0x36); //扫描方向控制WriteDAT_8(0xA8); //WriteCOM(0xB7);WriteDAT_8(0x00); //WriteCOM(0xF2);WriteDAT_8(0x01);delayms(10);// t Gamma,伽马曲线设置WriteCOM(0xE0);// Positive 05WriteDAT_8(0x09);//1WriteDAT_8(0x16);//2WriteDAT_8(0x09);//3WriteDAT_8(0x27);//4WriteDAT_8(0x2e);//5WriteDAT_8(0x25);//6WriteDAT_8(0x1c);//7WriteDAT_8(0x20);//8WriteDAT_8(0x1e);//9WriteDAT_8(0x1a);//10WriteDAT_8(0x24);//11WriteDAT_8(0x2d);//12WriteDAT_8(0x04);//13WriteDAT_8(0x05);//14WriteDAT_8(0x02);//15WriteDAT_8(0x0e);//16WriteCOM(0xE1); // NegativeWriteDAT_8(0x0b);//1WriteDAT_8(0x14);//2WriteDAT_8(0x09);//3WriteDAT_8(0x26);//4WriteDAT_8(0x27);//5WriteDAT_8(0x22);//6WriteDAT_8(0x1c);//7WriteDAT_8(0x20);//8WriteDAT_8(0x1d);//9WriteDAT_8(0x1a);//10WriteDAT_8(0x25);//11WriteDAT_8(0x2d);//12WriteDAT_8(0x06);//13WriteDAT_8(0x06);//14WriteDAT_8(0x02);//15WriteDAT_8(0x0f);//16WriteCOM(0x29); //Display ondelayms(10);WriteCOM(0x2C); //write to RAM }/******************************************************地址设置******************************************************/void add_rst(void) //地址重置{WriteCOM(0x2a); //Colulm addRSTs setWriteDAT_8(0x00);WriteDAT_8(0x00);WriteDAT_8(0x00);WriteDAT_8(159);WriteCOM(0x2b); //Colulm addRSTs setWriteDAT_8(0x00);WriteDAT_8(0x00);WriteDAT_8(0x00);WriteDAT_8(128);WriteCOM(0x2C); //Write Data to GRAM}static void LCD_SetPos(unsigned int x0,unsigned int x1,unsigned int y0,unsigned int y1) {WriteCOM(0x2A); //Colulm addRSTs setWriteDAT_8(x0>>8); //取x0的高8位WriteDAT_8(x0); //取x0的低8位WriteDAT_8(x1>>8);WriteDAT_8(x1);WriteCOM(0x2B); //Colulm addRSTs setWriteDAT_8(y0>>8);WriteDAT_8(y0);WriteDAT_8(y1>>8);WriteDAT_8(y1);WriteCOM(0x2C); //Write Data to GRAM}/*****************************************************函数名：display()功能：显示整屏颜色，颜色由d1,d2决定******************************************************/void display(unsigned int colour){unsigned int c,s;add_rst();for(c=0;c<128;c++) //横向扫描{for(s=0;s<160;s++){WriteDAT(colour>>8,colour);}}delayms(200);}/******************************************************函数名：LCD_ico功能：在起始位置为xs、ys，宽x、高y的区域内写入大小为x*y的图像ico******************************************************/void LCD_ico(unsigned char xs,unsigned char ys,unsigned char x,unsigned char y,unsigned char ico[]){unsigned int i;LCD_SetPos(xs,xs+x-1,ys,ys+y-1);for(i=0;i<x*y*2-1;i=i+2) //{WriteDAT(ico[i],ico[i+1]); //}}/******************************************************函数名：LCD_clear功能：在起始位置为xs、ys，宽x、高y的区域内写白色*****************************************************/void LCD_clear(unsigned char xs,unsigned char ys,unsigned char x,unsigned char y){unsigned int i;LCD_SetPos(xs,xs+x-1,ys,ys+y-1);for(i=0;i<x*y*2-2;i=i+2) //{WriteDAT(0xff,0xff); //}}/******************************************************函数名：LCD_write_kong功能：写空白显示在编号x位置******************************************************/void LCD_write_kong(unsigned char y){unsigned char m,n;LCD_SetPos((y%3)*42+y%3,(y%3)*42+42-1+y%3,(y/3)*42+y/3,(y/3)*42+42-1+y/3); //ram readyfor(n=0;n<42;n++) //for(m=0;m<42;m++){WriteDAT(0xFF,0xEE); //暂定为色}}/******************************************************函数名：LCD_write_part功能：从图片数组中取出对应于x的部分显示在编号y位置上每一小部分大小暂定为42x42。

593066-3 Product DetailsHome | Customer Support | Suppliers | Site Map | Privacy Policy | Browser Support© 2008 Tyco Electronics Corporation All Rights Reserved SearchProducts Documentation Resources My Account Customer SupportHome > Products > By Type > Pin & Socket Connectors > Product Feature Selector > Product Details593066-3Active Subminiature D Pin/Socket Connectors forMIL-C-24308 and MIL-C-39029Not reviewed for RoHS ComplianceProduct Highlights:?Connector?Product Series = 90?Density = Standard?Terminate To Wire?Number of Positions = 44View all Features | Find SimilarProductsCheck Pricing &AvailabilitySearch for ToolingProduct FeatureSelectorContact Us AboutThis ProductQuick LinksDocumentation & Additional InformationProduct Drawings:?AMPLIMITE NONMAGNETIC PLUG ASSY WITH SIZE 22 CRIMP P...(PDF, English)Catalog Pages/Data Sheets:?None AvailableProduct Specifications:?None AvailableApplication Specifications:?None AvailableInstruction Sheets:?None AvailableCAD Files:?None AvailableList all Documents Additional Information:?Product Line InformationRelated Products:?ToolingProduct Features (Please use the Product Drawing for all design activity)Product Type Features:?Product Type = Connector?Product Series = 90?Number of Positions = 44?Gender = Plug?Shell Size = 3?Shell Material = Brass?Wire Termination Type = CrimpBody Related Features:?Insert Arrangement = MS18275-2?Blindmate = No?Non-Magnetic = Yes?Pins = With?Rear Grommet = No?Power/Signal/Coax Combination = No?Shell Plating = Cadmium over Copper?Mount Style = Floating BushingContact Related Features:?Contact Size = 22?Contact Style = Crimp Snap-in?Contact Material = Copper Alloy?Contact Mating Area Plating Material = Goldover Nickel Configuration Related Features:?Density = StandardIndustry Standards:?Government/Industry Qualification = Yes?Government/Industry Part Number = M24308/8-309F?RoHS/ELV Compliance = Not reviewed forELV/RoHS compliance?Lead Free Solder Processes = Not reviewed forlead free solder process?NASA Qualification = NoConditions for Usage:?Terminate To = WireOther:?Brand = AMPProvide Website Feedback | Contact Customer Support。

Preliminary 1M X 16 Bit X 4 Banks Synchronous DRAMDocument Title1M X 16 Bit X 4 Banks Synchronous DRAMRevision HistoryDate Remark Rev. No. History Issue issue November 30, 2004 Preliminary0.0 InitialA43L2616APreliminary1M X 16 Bit X 4 Banks Synchronous DRAMFeatureJEDEC standard 3.3V power supplyLVTTL compatible with multiplexed address Four banks / Pulse RAS MRS cycle with address key programs - CAS Latency (2,3)- Burst Length (1,2,4,8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Clock Frequency: 166MHz @ CL=3 143MHz @ CL=3Burst Read Single-bit Write operationDQM for masking Auto & self refresh 64ms refresh period (4K cycle) Commercial Temperature Operation : 0°C~70°C Industrial Temperature Operation : -40°C~85°C for –U grade 54 Pin TSOP (II) and 54 Balls CSP (8mm x 8mm)General DescriptionThe A43L2616A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 X 1,048,576 words by 16 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock.I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.Pin ConfigurationTSOP (II)V S SD Q 15V S S QD Q 14D Q 13V D D QD Q 12D Q 11V S S QD Q 10D Q 9V D D QD Q 8V S SU D Q MC KC K EN CA 9A 8A 7A 6A 5A 4V S SV D DD Q 0V D D QD Q 1D Q 2V S S QD Q 3D Q 4V D D QD Q 5D Q 6V S S QD Q 7V D DL D Q MW EC A SR A SC SA 10/A PB S 1B S 0A 0A 1A 2A 3V D DA 11N CPin Configuration (continued)54 Balls CSP (8 mm x 8 mm)Top ViewBlock DiagramCLKADDDQiPin DescriptionsAbsolute Maximum Ratings*Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V Voltage on VDD supply relative to VSS (VDD, VDDQ ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to +4.6V Storage Temperature (T STG ) . . . . . . . . . . -55°C to +150°C Soldering Temperature X Time (T SLODER ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec Power Dissipation (P D ) . . . . . . . . . . . . . . . . . . . . . . . . .1W Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA *CommentsPermanent device damage may occur if “Absolute Maximum Ratings” are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.Capacitance (T A =25°C, f=1MHz)DC Electrical CharacteristicsRecommend operating conditions (Voltage referenced to VSS = 0V, T A = 0ºC to +70ºC or T A = -40ºC to +85ºC)Parameter Symbol Min Typ Max Unit NoteSupply Voltage VDD,VDDQ 3.0 3.3 3.6 VInput High Voltage V IH 2.0 3.0 VDD+0.3 VInput Low Voltage V IL -0.3 0 0.8 V Note 1 Output High Voltage V OH 2.4 --V I OH = -2mAOutput Low Voltage V OL - - 0.4 V I OL = 2mA Input Leakage Current I IL -5 - 5 µA Note 2 Output Leakage Current I OL -5 - 5 µANote 3Output Loading ConditionSee Figure 1Note: 1. V IL (min) = -1.5V AC (pulse width ≤ 5ns).2. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V3. Dout is disabled, 0V ≤ Vout ≤ VDDDecoupling Capacitance Guide LineRecommended decoupling capacitance added to power line at board.Parameter Symbol Value UnitDecoupling Capacitance between VDD and VSS C DC1 0.1 + 0.01 µF Decoupling Capacitance between VDDQ and VSSQC DC20.1 + 0.01µFNote: 1. VDD and VDDQ pins are separated each other.All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each otherAll VSS pins are connected in chip. All VSSQ pins are connected in chip.DC Electrical Characteristics(Recommended operating condition unless otherwise noted, T A = 0°C to 70°C T A = -40ºC to +85ºC) Note: 1. Measured with outputs open. Addresses are changed only one time during t CC (min).2. Refresh period is 64ms. Addresses are changed only one time during t CC (min).3. I CC6 normal version: A43L2616AV-6, A43L2616AV-7.4. I CC6 low self refresh current version: A43L2616AV-6V, A43L2616AV-7V.AC Operating Test Conditions(VDD = 3.3V ±0.3V, T A = 0°C to +70°C or T A = -40ºC to +85ºC)Parameter ValueAC input levelsV IH /V IL = 2.4V/0.4V Input timing measurement reference level 1.4VInput rise and all time (See note3)tr/tf = 1ns/1ns Output timing measurement reference level 1.4V Output load conditionSee Fig.2Output(Fig. 1) DC Output Load Circuit ΩTT =1.4V (Fig. 2) AC Output Load CircuitAC Characteristics(AC operating conditions unless otherwise noted)-6 -7Symbol Parameter CAS Latency Min Max Min MaxUnit Notet CC CLK cycle time 6 1000 7 1000 ns 1t SACCLK to valid Output delay- 5 - 5.4 ns 1,2 t OH Output data hold time 2.5-2.7-ns2t CH CLK high pulse width 32.5 - 2.5 - ns 3 t CL CLK low pulse width 2.5 - 2.5 - ns 3 t SS Input setup time 2 - 2 - ns 3 t SH Input hold time 1 - 1 - ns 3 t SLZ CLK to output in Low-Z 1-1-ns2t SHZCLK to output In Hi-Z3- 5.5 - 6 ns*All AC parameters are measured from half to half.Note : 1. Parameters depend on programmed CAS latency.2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.3. Assumed input rise and fall time (tr & tf) = 1ns.If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.Operating AC Parameter(AC operating conditions unless otherwise noted)Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.2. Minimum delay is required to complete write.Simplified Truth Table(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low) Note : 1. OP Code: Operand CodeA0~A11, BS0, BS1: Program keys. (@MRS)2. MRS can be issued only at both banks precharge state.A new command can be issued after 2 clock cycle of MRS.3. Auto refresh functions as same as CBR refresh of DRAM.The automatical precharge without Row precharge command is meant by “Auto”.Auto/Self refresh can be issued only at both precharge state.4. BS0, BS1 : Bank select address.If both BS1 and BS0 are “Low” at read, write, row active and precharge, bank A is selected.If both BS1 is “Low” and BS0 is “High” at read, write, row active and precharge, bank B is selected.If both BS1 is “High” and BS0 is “Low” at read, write, row active and precharge, bank C is selected.If both BS1 and BS0 are “High” at read, write, row active and precharge, bank D is selected.If A10/AP is “High” at row precharge, BS1 and BS0 is ignored and all banks are selected.5. During burst read or write with auto precharge, new read write command cannot be issued.Another bank read write command can be issued at every burst length.6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0) butmasks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)Mode Register Filed Table to Program ModesRegister Programmed with MRS AddressBS0, BS1A11, A10A9A8A7A6A5A4A3A2A1A0FunctionRFURFU W.B.L TM CAS Latency BT Burst Length(Note 1)(Note 2)Test ModeCAS LatencyBurst TypeBurst LengthA8 A7TypeA6 A5 A4Latency A3TypeA2A1 A0 BT=0BT=10 0 Mode Register Set0 0 0Reserved0Sequential 00 0 1 1 0 1 0 0 1- 1Interleave 00 1 2 2 1 0 0 1 0 2 0 1 0 4 4 1 1Vendor Use Only0 1 1 3 0 1 188 Write Burst Length 1 0 0Reserved 10 0 Reserved Reserved A9 Length 1 0 1Reserved10 1 ReservedReserved0 Burst 1 1 0Reserved 1 1 0 Reserved Reserved 1 Single Bit 1 1 1Reserved11 1 256(Full)ReservedPower Up Sequence1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.2. Maintain stable power, stable clock and NOP input condition for a minimum of 200µs.3. Issue precharge commands for all banks of the devices.4. Issue 2 or more auto-refresh commands.5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 may be changed.The device is now ready for normal operation.Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.Burst Sequence (Burst Length = 4)Initial addressSequential Interleave A1 A00 0 0 1 2 3 0 1 2 30 1 1 2 3 0 1 0 3 21 023 0 1 2 3 0 11 1 3 0 123 2 1 0Burst Sequence (Burst Length = 8)Initial addressSequential Interleave A2 A1 A00 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 70 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 60 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 50 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 41 0 0 4 5 6 7 0 1234567 0 1 2 31 0 1 5 6 7 0 12345 4 76 1 0 3 21 1 0 6 7 0 1234567 4 5 2 3 0 11 1 1 7 0 1234567 6 5 4 3 2 1 0Device OperationsClock (CLK)The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V IL and V IH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of set up and hold time around positive edge of the clock for proper functionality and ICC specifications.Clock Enable (CLK)The clock enable (CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended form the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When both banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode form the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least “t SS + 1 CLOCK” before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands.Bank Select (BS0, BS1)This SDRAM is organized as 4 independent banks of 1,048,576 words X 16 bits memory arrays. The BS0, BS1 inputs is latched at the time of assertion of RAS and CASto select the bank to be used for the operation. The bank select BS0, BS1 is latched at bank activate, read, write mode register set and precharge operations.Address Input (A0 ~ A11)The 20 address bits required to decode the 262,144 word locations are multiplexed into 12 address input pins (A0~A11). The 12 bit row address is latched along with RAS, BS0 and BS1 during bank activate command. The 8 bit column address is latched along with CAS, WE, BS0 and BS1during read or write command.NOP and Device DeselectWhen , CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS and WE, and all the address inputs are ignored.Power-UpThe following sequence is recommended for POWER UP 1. Power must be applied to either CKE and DQM inputs topull them high and other pins are NOP condition at the inputs before or along with VDD (and VDDQ) supply.The clock signal must also be asserted at the same time.2. After VDD reaches the desired voltage, a minimumpause of 200 microseconds is required with inputs in NOP condition.3. Both banks must be precharged now.4. Perform a minimum of 2 Auto refresh cycles to stabilizethe internal circuitry.5. Perform a MODE REGISTER SET cycle to program theCAS latency, burst length and burst type as the default value of mode register is undefined.At the end of one clock cycle from the mode register set cycle, the device is ready for operation.When the above sequence is used for Power-up, all the out-puts will be in high impedance state. The high impedance of outputs is not guaranteed in any other power-up sequence.cf.) Sequence of 4 & 5 may be changed.Mode Register Set (MRS)The mode register stores the data for controlling the various operation modes of SDRAM. It programs the CAS latency, addressing mode, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS,RAS, CAS,(The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0~A11, BS0 and BS1 in the same cycle as CS,,CAS,WE going low is the data written in the mode register. One clock cycle is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as both banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length field uses A0~A2, burst type uses A3, addressing mode uses A4~A6, A7~A8, A11, BS0 and BS1 are used for vendor specific options or test mode. And the write burst length is programmed using A9. A7~A8, A11, BS0 and BS1 must be set to low for normal SDRAM operation.Refer to table for specific codes for various burst length, addressing modes and CAS latencies.Device Operations (continued)Bank ActivateThe bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank addresses, a row access is initiated. The read or write operation can occur after a time delay of t RCD(min) from the time of bank activation. t RCD(min) is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t RCD(min) with cycle time of the clock and then rounding off the result to the next higher integer. The SDRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of both banks immediately. Also the noise generated during sensing of each bank of SDRAM is high requiring some time for power supplies recover before the other bank can be sensed reliably. t RRD(min) specifies the minimum time required between activating different banks. The number of clock cycles required between different bank activation must be calculated similar to t RCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t RAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by t RAS(max). The number of cycles for both t RAS(min) and t RAS(max) can be calculated similar to t RCD specification.Burst ReadThe burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least t RCD(min) before the burst read command is issued. The first output appears CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length. Burst WriteThe burst write command is similar to burst read command, and is used to write data into the SDRAM consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS,CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. The writing can not complete to burst length. The burst write can be terminated by issuing a burst read and DQM for blocking data inputs or burst write in the same or the other active bank. The burst stop command is valid only at full page burst length where the writing continues at the end of burst and the burst is wrap around. The write burst can also be terminated by using DQM for blocking data and precharging the bank “t RDL” after the last data input to be written into the active row. See DQM OPERATION also.DQM OperationThe DQM is used to mask input and output operation. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in the read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock, therefore the masking occurs for a complete cycle. The DQM signal is important during burst interrupts of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required.PrechargeThe precharge operation is performed on an active bank by asserting low on CS,RAS,WE and A10/AP with valid BA of the bank to be precharged. The precharge command can be asserted anytime after t RAS(min) is satisfied from the bank activate command in the desired bank. “t RP” is defined as the minimum time required to precharge a bank. The minimum number of clock cycles required to complete row precharge is calculated by dividing “t RP” with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by t RAS(max). Therefore, each bank has to be precharged within t RAS(max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again.Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc, is possible only when both banks are in idle state.Device Operations (continued)Auto PrechargeThe precharge operation can also be performed by usingauto precharge. The SDRAM internally generates thetiming to satisfy t RAS(min) and “t RP” for the programmedburst length and CAS latency. The auto prechargecommand is issued at the same time as burst read or burstwrite by asserting high on A10/AP. If burst read or burstwrite command is issued with low on A10/AP, the bank isleft active until a new command is asserted. Once autoprecharge command is given, no new commands arepossible to that particular bank until the bank achieves idlestate.Four Banks PrechargeBoth banks can be precharged at the same time by using Precharge all command. Asserting low on CS,RAS and WE with high on A10/AP after both banks have satisfied t RAS(min) requirement, performs precharge on both banks.At the end of tRP after performing precharge all, bothbanks are in idle state.Auto RefreshThe storage cells of SDRAM need to be refreshed every64ms to maintain data. An auto refresh cycle accomplishesrefresh of a single row of storage cells. The internalcounter increments automatically on every auto refreshcycle to refresh all the rows. An auto refresh command is issued by asserting low on CS,RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with both banks being in idle state and the deviceis not in power down mode (CKE is high in the previouscycle). The time required to complete the auto refresh operation is specified by “t RC(min)”. The minimum number of clock cycles required can be calculated by driving “t RC” with clock cycle time and then rounding up to the next higher integer. The auto refresh command must be followed by NOP’s until the auto refresh operation is completed. Both banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms.Self RefreshThe self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption.The self refresh mode is entered from all banks idle state by asserting low on CS,RAS,CAS and CKE with high on WE. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the self refresh.The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP’s for a minimum time of “t RC” before the SDRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to used burst 4096 auto refresh cycles immediately after exiting self refresh.Basic feature And Function Descriptions1. CLOCK SuspendNote: CLK to CLK disable/enable=1 clock2. DQM Operation* Note : 1. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”.2. DQM masks both data-in and data-out.3. CAS Interrupt (I)Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst.By “CAS Interrupt”, to stop burst read/write by CAS access; read, write and block write.2. t CCD : CAS to CAS delay. (=1CLK)3. t CDL : Last data in to new column address delay. (= 1CLK).4. CAS Interrupt (II) : Read Interrupted Write & DQM* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.5. Write Interrupted by Precharge & DQMNote : 1. To inhibit invalid write, DQM should be issued.2. This precharge command and burst write command should be of the same bank, otherwise it is not prechargeinterrupt but only another bank precharge of dual banks operation.6. Precharge7. Auto Precharge* Note : 1. The row active command of the precharge bank can be issued after t RP from this point.The new read/write command of other active bank can be issued from this point.At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.8. Burst Stop & Interrupted by Precharge9. MRSNote : 1. t RDL : 1CLK 2. t BDL : 1CLK; Last data in to burst stop delay.Read or write burst stop command is valid at every burst length.3. Number of valid output data after row precharge or burst stop: 1,2 for CAS latency = 2, 3 respectively.4. PRE: All banks precharge if necessary.MRS can be issued only when all banks are in precharged state.10. Clock Suspend Exit & Power Down Exit11. Auto Refresh & Self Refresh* Note : 1. Active power down : one or more bank active state.2. Precharge power down : both bank precharge state.3. The auto refresh is the same as CBR refresh of conventional DRAM.No precharge commands are required after Auto Refresh command.During t RC from auto refresh command, any other command can not be accepted.4. Before executing auto/self refresh command, both banks must be idle state.5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.6. During self refresh mode, refresh interval and refresh operation are performed internally.After self refresh entry, self refresh mode is kept while CKE is LOW.During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.During t RC from self refresh exit command, any other command can not be accepted.Before/After self refresh mode, burst auto refresh cycle (4K cycles ) is recommended.12. About Burst Type ControlSequential counting At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8) BL=1,2,4,8 and full page wrap around.BasicMODEInterleave counting At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8) BL=4,8 At BL=1,2 Interleave Counting = Sequential CountingRandom MODE Random column Accesst CCD = 1 CLKEvery cycle Read/Write Command with random column address can realizeRandom Column Access.That is similar to Extended Data Out (EDO) Operation of convention DRAM.13. About Burst Length ControlPower On Sequence & Auto RefreshCKECSRASCASADDRBS0, BS1A10/APWEDQMDQ(A-Bank)Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1CLOCKCKECSRASCASADDRBS0, BS1A10/APWEDQMDQ* Note : 1. All inputs can be don’t care when CS is high at the CLK high going edge.2. Bank active & read/write are controlled by BS0, BS1.BS1 BS0 Active & Read/WriteA0 0 BankB0 1 BankC1 0 BankD1 1 Bank3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.A10/AP BS1 BS0Operation0 0 Disable auto precharge, leave bank A active at end of burst.0 1 Disable auto precharge, leave bank B active at end of burst.1 0 Disable auto precharge, leave bank C active at end of burst.1 1 Disable auto precharge, leave bank D active at end of burst.0 0 Enable auto precharge, precharge bank A at end of burst.0 1 Enable auto precharge, precharge bank B at end of burst.11 0 Enable auto precharge, precharge bank C at end of burst.1 1 Enable auto precharge, precharge bank D at end of burst.4. A10/AP and BS0, BS1 control bank precharge when precharge command is asserted.A10/AP BS1 BS0 PrechargeA0 0 0 BankB0 0 1 BankC0 1 0 BankD0 1 1 BankBanks1 X X All。

Enterprise Development专业品质权威Analysis Report企业发展分析报告无锡玖炎精密制造有限公司免责声明:本报告通过对该企业公开数据进行分析生成，并不完全代表我方对该企业的意见，如有错误请及时联系;本报告出于对企业发展研究目的产生，仅供参考，在任何情况下，使用本报告所引起的一切后果，我方不承担任何责任:本报告不得用于一切商业用途，如需引用或合作，请与我方联系:无锡玖炎精密制造有限公司1企业发展分析结果1.1 企业发展指数得分企业发展指数得分无锡玖炎精密制造有限公司综合得分说明：企业发展指数根据企业规模、企业创新、企业风险、企业活力四个维度对企业发展情况进行评价。

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Freescale Semiconductor Technical DataFreescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its Document Number: MC13201Rev. 1.1, 03/2007MC13201Package InformationPlastic Package Case 1311-03QFN -32Ordering InformationDevice Device MarkingPackage MC1320113201QFN-321IntroductionThe MC13201 is a short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) bandtransceivers. The MC13201 contains a complete packet data modem which is compliant with the IEEE ®802.15.4 Standard PHY (Physical) layer. This allows the development of proprietary point-to-point and star networks based on the 802.15.4 packet structure and modulation format. For full 802.15.4 Standardcompliance, the MC13202/203 and Freescale's 802.15.4 MAC software are required.When combined with an appropriate microcontroller (MCU), the MC13201 provides a cost-effective solution for short-range data links and networks. Interface with the MCU is accomplished using a four wire serial peripheral interface (SPI) connection and an interrupt request output which allows for the use of a variety of processors. The software and processor can be scaled to fit applications ranging from simple point-to-point systems to star networks.MC132012.4 GHz Low Power Transceiver for the IEEE ® 802.15.4 StandardContents1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 12Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 44Data Transfer Mode . . . . . . . . . . . . . . . . . . . . 55Electrical Characteristics . . . . . . . . . . . . . . . 76Functional Description . . . . . . . . . . . . . . . . 107Pin Connections . . . . . . . . . . . . . . . . . . . . . . 148Crystal Oscillator Reference Frequency . . 189Packaging Information . . . . . . . . . . . . . . . . . 27For more detailed information about MC13201 operation, refer to the MC13201 Reference Manual, (MC13201RM).Applications include, but are not limited to, the following:•Residential and commercial automation—Lighting control—Security—Access control—Heating, ventilation, air-conditioning (HVAC)—Automated meter reading (AMR)•Industrial Control—Asset tracking and monitoring—Homeland security—Process management—Environmental monitoring and control—HVAC—Automated meter reading•Health Care—Patient monitoring—Fitness monitoring•Consumer—Human interface devices (keyboard, mice, etc.)—Remote control—Wireless toysThe transceiver includes a low noise amplifier, 1.0 mW power amplifiers (PA), onboard RFtransmit/receive (T/R) switch for single port use, PLL with internal voltage controlled oscillator (VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with5.0 MHz channel spacing per the 802.15.4 Standard. The SPI port and interrupt request output are used for receive (RX) and transmit (TX) data transfer and control.2Features•Recommended power supply range: 2.0 to 3.4 V•Fully compliant 802.15.4 Standard transceiver supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode•Operates on one of 16 selectable channels in the 2.4 GHz band•-1 to 0 dBm nominal output power, programmable from -27 dBm to +3 dBm typical•Receive sensitivity of <-91 dBm (typical) at 1% PER, 20-byte packet, much better than the 802.15.4 Standard of -85 dBm•Integrated transmit/receive switch•Dual PA output pairs which can be programmed for full differential single port or dual port operation that supports an external LNA and/or PA•Three power down modes for increased battery life—< 1 µA Off current—1.0 µA Typical Hibernate current—35 µA Typical Doze current (no CLKO)•Programmable frequency clock output (CLKO) for use by MCU•Onboard trim capability for 16 MHz crystal reference oscillator eliminates need for external variable capacitors and allows for automated production frequency calibration •Four internal timer comparators available to supplement MCU timer resources•Buffered transmit and receive data packets for simplified use with low cost MCUs•Seven GPIO to supplement MCU GPIO•Operating temperature range: -40 °C to 85 °C•Small form factor QFN-32 Package—Meets moisture sensitivity level (MSL) 3—260 °C peak reflow temperature—Meets lead-free requirements2.1Software SupportFreescale provides a software suite to complement the MC13201 hardware which is called the Freescale Simple MAC (SMAC):•Simple proprietary wireless connectivity.•Small memory footprint (about 3 Kbytes typical)•Supports point-to-point and star network configurations•Proprietary networks•Source code and application examples provided3Block DiagramsFigure1 shows a simplified block diagram of the MC13201 which is an 802.15.4 Standard compatible transceiver that provides the functions required in the physical layer (PHY) specification.Figure1. 802.15.4 modem Simplified Block DiagramFigure2 shows the basic system block diagram for the MC13201 in an application. Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request line. The media access control (MAC), drivers, and network and application software (as required) reside on the host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor depending on application requirements.4Data Transfer ModeThe MC13201 has a data transfer mode called Packet Mode where data is buffered in on-chip Packet RAMs. There is a TX Packet RAM and an RX Packet RAM, each of which are 64 locations by 16 bits wide.4.1Packet StructureFigure3 shows the packet structure of the MC13201 which is consistent with the 802.15.4 Standard. Payloads of up to 125 bytes are supported. The MC13201 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A Frame Check Sequence (FCS) is calculated and appended to the end of the data.4 bytes 1 byte 1 byte125 bytes maximum 2 bytesPreamble SFD FLI Payload Data FCSFigure3. MC13201 Packet Structure4.2Receive Path DescriptionIn the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon the baseband energy integrated over a specific time interval. The digital backend performs Differential Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data.The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured over a 64 µs period after the packet preamble and stored in RAM.The MC13201 uses a packet mode where the data is processed as an entire packet and stored in Rx Packet RAM. The MCU is notified that an entire packet has been received via an interrupt.Figure4 shows CCA reported power level versus input power. Note that CCA reported power saturates at about -57 dBm input power which is well above 802.15.4 Standard requirements. Figure5 shows energy detection/LQI reported level versus input power.NOTEFor both graphs, the required 802.15.4 Standard accuracy and range limitsare shown. A 3.5 dBm offset has been programmed into the CCA reportinglevel to center the level over temperature in the graphs.Figure5. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator4.3Transmit Path DescriptionFor the transmit path, the TX data that was previously stored in TX Packet RAM is retrieved, formed into packets per the 802.15.4 PHY, spread, and then up-converted to the transmit frequency.Because the MC13201 is used in packet mode, data is processed as an entire packet. The data is first loaded into the TX buffer. The MCU then requests that the MC13201 transmit the data. The MCU is notified via an interrupt when the whole packet has successfully been transmitted.5Electrical Characteristics5.1Maximum Ratings5.2Recommended Operating ConditionsTable 1. Maximum RatingsRatingSymbol Value Unit Power Supply Voltage V BATT, V DDINT-0.3 to 3.6VdcDigital Input Voltage Vin -0.3 to (V DDINT + 0.3)RF Input Power P max 10dBm Junction Temperature T J 125°C Storage Temperature RangeT stg-55 to 125°C Note:Maximum Ratings are those values beyond which damage to the device may occur.Functional operation should be restricted to the limits in the Electrical Characteristics or Recommended Operating Conditions tables.Note:Meets Human Body Model (HBM) = 2 kV. RF input/output pins have no ESD protection.Table 2. Recommended Operating ConditionsCharacteristic SymbolMin Typ Max Unit Power Supply Voltage (V BATT = V DDINT )11If the supply voltage is produced by a switching DC-DC converter, ripple should be less than 100 mV peak-to-peak.V BATT, V DDINT 2.0 2.7 3.4Vdc Input Frequencyf in 2.405- 2.480GHz Ambient Temperature Range T A -402585°C Logic Input Voltage Low V IL 0-30% V DDINT V Logic Input Voltage High V IH 70% V DDINT-V DDINT V SPI Clock Rate f SPI --8.0MHz RF Input PowerP max --10dBmCrystal Reference Oscillator Frequency (±40 ppm over operating conditions to meet the 802.15.4 Standard.)f ref16 MHz Only5.3DC Electrical CharacteristicsTable 3. DC Electrical Characteristics(V BATT , V DDINT = 2.7 V, T A = 25 °C, unless otherwise noted)Characteristic SymbolMin Typ Max Unit Power Supply Current (V BATT + V DDINT )Off 1Hibernate 1Doze (No CLKO)1 2IdleTransmit Mode (0 dBm nominal output power)Receive Mode 1To attain specified low power current, all GPIO and other digital IO must be handled properly. See Section 8.3, “Low Power Considerations .2CLKO frequency at default value of 32.786 kHz.I leakage I CCH I CCD I CCI I CCT I CCR ------0.21.0355003037 1.06.010********µA µA µA µA mA mA Input Current (V IN = 0 V or V DDINT ) (All digital inputs)I IN --±1µA Input Low Voltage (All digital inputs)V IL 0-30% V DDINT V Input High Voltage (all digital inputs)V IH 70% V DDINT -V DDINT V Output High Voltage (I OH = -1 mA) (All digital outputs)V OH 80% V DDINT-V DDINT V Output Low Voltage (I OL = 1 mA) (All digital outputs)V OL-20% V DDINTV5.4AC Electrical CharacteristicsTable 4. Receiver AC Electrical Characteristics(V BATT , V DDINT = 2.7 V, T A = 25 °C, f ref = 16 MHz, unless otherwise noted.)Characteristic SymbolMin Typ Max Unit Sensitivity for 1% Packet Error Rate (PER) (-40 to +85 °C)SENS per--91-dBm Sensitivity for 1% Packet Error Rate (PER) (+25 °C)--91-82dBm Saturation (maximum input level)SENS max-10-dBm Channel Rejection for 1% PER (desired signal -82 dBm)+5 MHz (adjacent channel)-5 MHz (adjacent channel)+10 MHz (alternate channel)-10 MHz (alternate channel)>= 15 MHz -----3130434153-----dB dB dB dB dB Frequency Error Tolerance --200kHz Symbol Rate Error Tolerance--80ppmTable 5. Transmitter AC Electrical Characteristics(V BATT , V DDINT = 2.7 V, T A = 25 °C, f ref = 16 MHz, unless otherwise noted.)Characteristic SymbolMin Typ Max Unit Power Spectral Density (-40 to +85 °C) Absolute limit --47-dBmPower Spectral Density (-40 to +85 °C) Relative limit -47-Nominal Output Power 11SPI Register 12 programmed to 0x00BC which sets output power to nominal (-1 dBm typical).P out-5-1-dBm Maximum Output Power 22SPI Register 12 programmed to 0x00FF which sets output power to maximum.4dBmError Vector Magnitude EVM -2045 %Output Power Control Range -30-dB Over the Air Data Rate -250-kbps 2nd Harmonic -TBD -dBc 3rd Harmonic-TBD-dBcTable6. Digital Timing Specifications(VBATT, VDDINT = 2.7 V, TA = 25 °C, frequency = 16 MHz, unless otherwise noted.SPI timing parameters are referenced to Figure8.Symbol Parameter Min Typ Max Unit T0SPICLK period125nST1Pulse width, SPICLK low50nST2Pulse width, SPICLK high50nST3Delay time, MISO data valid from falling SPICLK15nST4Setup time, CE low to rising SPICLK15nST5Delay time, MISO valid from CE low15nST6Setup time, MOSI valid to rising SPICLK15nST7Hold time, MOSI valid from rising SPICLK15nS RST minimum pulse width low (asserted)250nS Figure6 shows a typical AC parameter evaluation circuit.Figure6. RF Parametric Evaluation Circuit6Functional DescriptionThe following sections provide a detailed description of the MC13201 functionality, including operating modes, and the Serial Peripheral Interface (SPI).6.1MC13201 Operational ModesThe MC13201 has a number of operational modes that allow for low-current operation. Transition from the Off to Idle mode occurs when RST is negated. Once in Idle, the SPI is active and is used to control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are summarized, along with the transition times, in Table7. Current drain in the various modes is listed in Table3, DC Electrical Characteristics.6.2Serial Peripheral Interface (SPI)The host microcontroller directs the MC13201, checks its status, and reads/writes data to the device through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction between the host and the MC13201 occurs as multiple 8-bit bursts on the SPI. The SPI signals are:1.Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.2.SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13201. Data is clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out changes state on the trailing (falling) edge of SPICLK.NOTEFor Freescale microcontrollers, the SPI clock format is the clock phase control bit CPHA = 0 and the clock polarity control bit CPOL = 0.3.Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.4.Master In/Slave Out (MISO) - The MC13201 presents data to the master on the MISO output.A typical interconnection to a microcontroller is shown in Figure 7.Table 7. MC13201 Mode Definitions and Transition TimesMode DefinitionTransition Time To or From Idle Off All IC functions Off, Leakage only. RST asserted. Digital outputs are tri-stated including IRQ10 - 25 ms to IdleHibernate Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is retained.7 - 20 ms to Idle DozeCrystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9 = 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to ATTN and can be programmed to enter Idle Mode through an internal timer comparator. (300 + 1/CLKO) µs to Idle Idle Crystal Reference Oscillator On with CLKO output available. SPI active.Receive Crystal Reference Oscillator On. Receiver On.144 µs from Idle TransmitCrystal Reference Oscillator On. Transmitter On.144 µs from IdleFigure7. SPI InterfaceAlthough the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock (CLK core), derived from the crystal reference oscillator, to communicate from the SPI registers to internal registers and memory.6.2.1SPI Burst OperationThe SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master (MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the master on the MISO line. Although an MC13201 transaction is three or more SPI bursts long, the timing of a single SPI burst is shown in Figure8.SPI digital timing specifications are shown in Table6.6.2.2SPI Transaction OperationAlthough the SPI port of an MCU transfers data in bursts of 8 bits, the MC13201 requires that a complete SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The assertion of CE to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to the transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and identifies the access as being a read or write operation. In this context, a write is data written to theMC13201 and a read is data written to the SPI master. The following SPI bursts will be either the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid).Although the SPI bus is capable of sending data simultaneously between master and slave, the MC13201 never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can extend to a larger number depending on the type of access. The number of payload bytes sent will always be an even integer. After the final SPI burst, CE is negated to high to signal the end of the transaction. Refer to the MC13201 Reference Manual, (MC13201RM) for more details on SPI registers and transaction types. An example SPI read transaction with a 2-byte payload is shown in Figure9.Figure9. SPI Read Transaction Diagram7Pin ConnectionsTable8. Pin Function DescriptionPin #Pin Name Type Description Functionality1RFIN_M RF Input RF input/output negative.When used with internal T/R switch, this isa bi-directional RF port for the internal LNAand PA2RFIN_P RF Input RF input/output positive.When used with internal T/R switch, this isa bi-directional RF port for the internal LNAand PA3CT_Bias Control voltage Bias voltage/control signal forexternal RF components When used with internal T/R switch, provides RX ground reference and TX VDDA reference for use with external balun. Can also be used as a control signal for external LNA, PA, or T/R switch.4NC Tie to Ground.5PAO_P RF Output /DC Input RF Power Amplifier Output Positive.Open drain. Connect to VDDA through abias network when used with an externalbalun. Not used when internal T/R switch isused.6PAO_M RF Output/DC Input RF Power Amplifier Output Negative.Open drain. Connect to VDDA through abias network when used with an externalbalun. Not used when internal T/R switch isused.7SM Input Test mode pin.Must be grounded for normal operation.8GPIO41Digital Input/ Output General Purpose Input/Output 4.See Footnote 19GPIO3Digital Input/ Output General Purpose Input/Output 3.10GPIO2Digital Input/ Output General Purpose Input/Output 2.When gpio_alt_en, Register 9, Bit 7 =1, GPIO2 functions as a “CRC Valid”indicator.11GPIO1Digital Input/ Output General Purpose Input/Output 1.When gpio_alt_en, Register 9, Bit 7 =1, GPIO1 functions as an “Out of Idle”indicator.12RST Digital Input Active Low Reset. While held low, theIC is in Off Mode and all internalinformation is lost from RAM and SPIregisters. When high, IC goes to IDLEMode, with SPI in default state.13RXTXEN 2Digital InputActive High. Low to high transition initiates RX or TX sequencedepending on SPI setting. Should be taken high after SPI programming to start RX or TX sequence and should be held high through the sequence. After sequence is complete, return RXTXEN to low. When held low, forces Idle Mode.See Footnote 214ATTN 2Digital InputActive Low Attention. Transitions IC from either Hibernate or Doze Modes to Idle.See Footnote 215CLKO Digital OutputClock output to host MCU. Programmable frequencies of:16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 62.5 kHz, 32.786+ kHz (default),and 16.393+ kHz.16SPICLK 2Digital Clock Input External clock input for the SPI interface.See Footnote 217MOSI 2Digital Input Master Out/Slave In. Dedicated SPI data input.See Footnote 218MISO 3Digital Output Master In/Slave Out. Dedicated SPI data output.See Footnote 319CE 2Digital Input Active Low Chip Enable. Enables SPI transfers.See Footnote 220IRQDigital OutputActive Low Interrupt Request.Open drain device.Programmable 40 k Ω internal pull-up. Interrupt can be serviced every 6 µs with <20 pF load.Optional external pull-up must be >4 k Ω.21VDDD Power Output Digital regulated supply bypass.Decouple to ground.22VDDINT Power Input Digital interface supply & digital regulator input. Connect to Battery. 2.0 to 3.4 V. Decouple to ground.23GPIO51Digital Input/Output General Purpose Input/Output 5.See Footnote 124GPIO6Digital Input/Output General Purpose Input/Output 6.25GPIO7Digital Input/Output General Purpose Input/Output 7.26XTAL1InputCrystal Reference oscillator input.Connect to 16 MHz crystal and load capacitor.Table 8. Pin Function Description (continued)Pin #Pin Name TypeDescriptionFunctionality27XTAL2Input/OutputCrystal Reference oscillator output Note:Do not load this pin by using it as a 16 MHz source. Measure 16 MHz output at Pin 15, CLKO, programmed for 16 MHz. See the MC13201 Reference Manual for details.Connect to 16 MHz crystal and load capacitor.28VDDLO2Power Input LO2 VDD supply. Connect to VDDA externally.29VDDLO1Power Input LO1 VDD supply. Connect to VDDA externally.30VDDVCO Power Output VCO regulated supply bypass.Decouple to ground.31VBATT Power Input Analog voltage regulators Input. Connect to Battery.Decouple to ground.32VDDAPower OutputAnalog regulated supply Output. Connect to directly VDDLO1 and VDDLO2 externally and to PAO± through a bias network.Note : Do not use this pin to supply circuitry external to the chip.Decouple to ground.EPGround External paddle / flag ground.Connect to ground.1The transceiver GPIO pins default to inputs at reset. There are no programmable pullups on these pins. Unused GPIO pins should be tied to ground if left as inputs, or if left unconnected, they should be programmed as outputs set to the low state.2During low power modes, input must remain driven by MCU.3By default MISO is tri-stated when CE is negated. For low power operation, miso_hiz_en (Bit 11, Register 07) should be set to zero so that MISO is driven low when CE is negated.Table 8. Pin Function Description (continued)Pin #Pin Name TypeDescriptionFunctionalityFigure10. Pin Connections (Top View)8Crystal Oscillator Reference FrequencyThis section provides application specific information regarding crystal oscillator reference design and recommended crystal usage.8.1Crystal Oscillator Design ConsiderationsThe 802.15.4 Standard requires that several frequency tolerances be kept within ± 40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MC13201 transceiver provides onboard crystal trim capacitors to assist in meeting this performance.The primary determining factor in meeting this specification is the tolerance of the crystal oscillator reference frequency. A number of factors can contribute to this tolerance and a crystal specification will quantify each of them:1.The initial (or make) tolerance of the crystal resonant frequency itself.2.The variation of the crystal resonant frequency with temperature.3.The variation of the crystal resonant frequency with time, also commonly known as aging.4.The variation of the crystal resonant frequency with load capacitance, also commonly known aspulling. This is affected by:a)The external load capacitor values - initial tolerance and variation with temperature.b)The internal trim capacitor values - initial tolerance and variation with temperature.c)Stray capacitance on the crystal pin nodes - including stray on-chip capacitance, stray packagecapacitance and stray board capacitance; and its initial tolerance and variation withtemperature.5.Whether or not a frequency trim step will be performed in productionFreescale requires the use of a 16 MHz crystal with a <9 pF load capacitance. The MC13201 does not contain a reference divider, so 16 MHz is the only frequency that can be used. A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its performance. The crystal manufacturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. The oscillator amplifier configuration used in the MC13201 requires two balanced load capacitors from each terminal of the crystal to ground. As such, the capacitors are seen to be in series by the crystal, so each must be <18 pF for proper loading.In the Figure11 crystal reference schematic, the external load capacitors are shown as 6.8 pF each, used in conjunction with a crystal that requires an 8 pF load capacitance. The default internal trim capacitor value (2.4 pF) and stray capacitance total value (6.8 pF) sum up to 9.2 pF giving a total of 16 pF. The value for the stray capacitance was determined empirically assuming the default internal trim capacitor value and for a specific board layout. A different board layout may require a different external load capacitor value. The on-chip trim capability may be used to determine the closest standard value by adjusting the trim value via the SPI and observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately 5 pF in 20 fF steps.Initial tolerance for the internal trim capacitance is approximately ±15%.Since the MC13201 contains an on-chip reference frequency trim capability, it is possible to trim out virtually all of the initial tolerance factors and put the frequency within 0.12 ppm on a board-by-board basis. Individual trimming of each board in a production environment allows use of the lowest cost crystal, but requires that each board go through a trimming procedure. This step can be avoided byusing/specifying a crystal with a tighter stability tolerance, but the crystal will be slightly higher in cost.A tolerance analysis budget may be created using all the previously stated factors. It is an engineering judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if the various factors can be statistically rationalized using RSS (Root-Sum-Square) analysis. The aging factor is usually specified in ppm/year and the product designer can determine how many years are to be assumed for the product lifetime. Taking all of the factors into account, the product designer can determine the needed specifications for the crystal and external load capacitors to meet the 802.15.4 Standard.Figure 11. MC13201 Modem Crystal Circuit8.2Crystal RequirementsThe suggested crystal specification for the MC13201 is shown in Table 10. A number of the stated parameters are related to desired package, desired temperature range and use of crystal capacitive load trimming. For more design details and suggested crystals, see application note AN3251, Reference Oscillator Crystal Requirements for MC1319x, MC1320x, and MC1321x .Table 9. MC13201 Crystal Specifications 11User must be sure manufacturer specifications apply to the desired package.ParameterValue Unit ConditionFrequency16.000000MHz Frequency tolerance (cut tolerance)22A wider frequency tolerance may acceptable if application uses trimming at production final test.± 10ppm at 25 °CFrequency stability (temperature drift)3± 15ppm Over desired temperature range Aging 4± 2ppm max Equivalent series resistance 543ΩmaxLoad capacitance 6 5 - 9pF Shunt capacitance <2pFmax Mode of oscillationfundamental。

COM90C66Data Sheet with Erratas forRev. B and Rev. D devices ARCNET® Controller/Transceiver withAT® Interface and On-Chip RAMFEATURES• ARCNET LAN Controller/Transceiver/ Support Logic/Dual-Port RAM• Integrates SMSC COM90C65 with 16-Bit Data Bus, Dual-Port RAM, and EnhancedDiagnostics Circuitry• Includes IBM® PC/AT® Bus Interface Circuitry• Supports 8- and 16-Bit Data Buses• Full 2K x 8 On-Chip Dual-Port Buffer RAM • Zero Wait State Arbitration for Most AT Buses• SMSC COM90C26 Software Compatible • Command Chaining Enhances Performance • Supports Memory Mapped and Sequential I/O Mapped Access to the Internal RAMBuffer • Compatible with the SMSC HYC9058/68/ 88 (COAX and Twisted Pair Drivers)• Token Passing Protocol with SelfReconfiguration Detection• Variable Data Length Packets• 16 Bits CRC Check/Generation• Includes Address Decoding Circuitry for On-Chip RAM, PROM and I/O• Supports up to 255 Nodes• Contains Software Accessible Node ID Register• Compatible with Various Topologies (Star, Tree, Bus, ...)• On-Board Crystal Oscillator and Reset Circuitry• Low Power CMOS, Single +5V SupplyGENERAL DESCRIPTIONThe SMSC COM90C66 is a special purpose communications controller for interconnecting processors and intelligent peripherals using the ARCNET Local Area Network. The COM90C66 is unique in that it integrates the core ARCNET logic found in Standard Microsystems' original COM90C26 and COM90C32 with an on-chip 2K x 8 RAM, as well as the 16-bit data bus interface for the IBM PC/AT. Because of the inclusion of the RAM buffer in the COM90C66, a complete ARCNET node can be implemented with only one or two additional ICs (8- or 16-bit applications, respectively) and a media driver circuit. The ARCNET core remains functionally untouched, eliminating validation and compatibility concerns. The enhancements exist in the integration and the performance of the device. Maximum integration has been achieved by including the 2K x 8 RAM buffer on the chip, providing the immediate benefits of a lower device pin count and less board components. The performance is enhanced in four ways: a 16-bit data bus for operation with the IBM PC/AT;a zero wait state arbitration mechanism, due partly to the integration of the RAM buffer on-chip; the ability of the device to do consecutive transmissions and receptions via the Command Chaining operation; and improved diagnostics, allowing the user to control the system more efficiently. For most AT compatibles, the device handles zero wait state transfers.ARCNET is a registered trademark of Datapoint Corporation IBM, AT, PC/AT and Micro Channel are registered trademarks ofInternational Business Machines Corporation1TABLE OF CONTENTS FEATURES (1)GENERAL DESCRIPTION (1)PIN CONFIGURATION (3)DESCRIPTION OF PIN FUNCTIONS (4)PROTOCOL DESCRIPTION (9)NETWORK PROTOCOL (9)NETWORK RECONFIGURATION (9)BROADCAST MESSAGES (10)EXTENDED TIMEOUT FUNCTION (10)LINE PROTOCOL (10)SYSTEM DESCRIPTION (12)MICROPROCESSOR INTERFACE (12)TRANSMISSION MEDIA INTERFACE (13)FUNCTIONAL DESCRIPTION (13)MICROSEQUENCER (13)ADDRESS DECODING (19)INTERNAL REGISTERS (22)INTERNAL RAM (29)SOFTWARE INTERFACE (29)SOFTWARE COMPATIBILITY CONSIDERATIONS (31)COMMAND CHAINING (32)RESET DETAILS (34)READ AND WRITE CYCLES (35)NODE ID LOGIC (43)TRANSMIT/RECEIVE LOGIC (43)IMPROVED DIAGNOSTICS (43)OSCILLATOR (45)OPERATIONAL DESCRIPTION (46)MAXIMUM GUARANTEED RATINGS (46)DC CHARACTERISTICS (46)TIMING DIAGRAMS (49)Please see Addendum 1 entitled Data Sheet Errata for Revision B COM90C66, which discusses changes to this data sheet which apply to the Revision B device, on Page 62.Please see Addendum 2 entitled Data Sheet Errata for Revision D COM90C66, which discusses changes to this data sheet which apply to the Revision D device, on Page 64.80 Arkay DriveHauppauge, NY 11788(516) 435-6000FAX (516) 273-31232For other machines, the IOCHRDY signal may be briefly negated to give the device the extra time necessary to support the faster machines. Aside from the implementation of a 16-bit data bus interface, the remaining bus interface logic is identical to that found in the SMSC COM90C65, which contains all the support logic circuitry.The ARCNET Local Area Network is a token passing network which operates at a 2.5 Mbps data rate. A token passing protocol provides predictable response times because each network event occurs within a known time interval. Throughput can be reliably predeter-mined based upon the number of nodes and their expected traffic.The COM90C66 establishes the network configuration and automatically reconfigures the token passing order as new nodes are added or deleted from the network.The COM90C66 performs address recognition, CRC checking and generation, packet acknowledgement, and other network management functions. The C0M90C66 interfaces directly to the IBM PC/AT or compatibles. The internal 2K x 8 RAM buffer is used to hold up to four data packets with a maximum length of 508 bytes each.DESCRIPTION OF PIN FUNCTIONSPLCCPIN SYMBOL DESCRIPTIONPROCESSOR INTERFACE75-84, 2-11Address 0-19A0-A19Input. These signals are connected to the address linesof the host processor and are used to access memoryand I/O locations of the COM90C66, as well as to accessthe external ROM through the COM90C66.13-20, 22-29Data 0-15D0-D15Input/Output. These signals are used by the host totransmit data to and from the internal registers and buffermemory of the COM90C66 and are connected to weakinternal pull-up resistors.63, 62nTransceiverDirectionControl nTOPL,nTOPHOutput. These active low signals control the data bustransceiver. When these signals are high, data gets sentfrom the PC to the COM90C66. When these signals arelow, data gets sent from the COM90C66 to the PC, orfrom the PROM to the PC if the PROM signal is also low.71I/O ChannelReady IOCHRDY Output. This signal, when low, is optionally used by the COM90C66 to extend host cycles. This is an open-drainsignal. An external pull-up resistor is typically providedby the system.12AddressEnable AEN Input. This signal, when low, acts as a qualifier for I/O Address Selection. When the signal is high, I/Odecoding is disabled. This signal has no effect onMemory Address Selection.74Address LatchEnable BALE Input. The falling edge of this signal is used by the COM90C66 to latch the A0-A19 lines and the nSBHEsignal via an internal transparent latch. This signal isconnected to a weak internal pull-up resistor.64nI/O Read nIOR Input. This active low signal is issued by the hostmicroprocessor to indicate an I/O Read operation. A lowlevel on this pin when the COM90C66 is accessedenables data from the internal registers of theCOM90C66.65nI/O Write nIOW Input. This active low signal is issued by the hostmicroprocessor to indicate an I/O Write operation. A lowpulse on this pin when the COM90C66 is accessedenables data from the Data Bus into the internal registersof the COM90C66.4DESCRIPTION OF PIN FUNCTIONSPLCCPIN SYMBOL DESCRIPTION 66nMemory Read nMEMR Input. This active low signal is issued by the hostmicroprocessor to indicate a Memory Read operation. Alow level on this pin when the COM90C66 is accessedenables data from the internal RAM of the COM90C66 orthe PROM onto the data bus to be read by the host.67nMemoryWrite nMEMW Input. This active low signal is issued by the host microprocessor to indicate a Memory Write operation. Alow pulse on this pin when the COM90C66 is accessedenables data from the data bus into the internal RAM ofthe COM90C66.52Reset In RESETIN Input. This active high signal is the power on reset signalfrom the host. It is used to activate the internal resetcircuitry within the COM90C66.53nROM Enable nENROM Input. This active low signal enables the decoding of theexternal PROM. This signal also affects the timing ofIOCHRDY and the number of address lines used todecode nMEMCS16. This signal is connected to a weakinternal pull-up resistor.54nROM Select nPROM Output. This active low signal is issued by theCOM90C66 to enable the external 8-bit wide PROM orthe external register of the COM90C66.30InterruptRequest INTR Output. This active high signal is generated by the COM90C66 when an enabled interrupt condition occurs.INTR returns to its inactive state when the interruptstatus condition or the corresponding interrupt mask bitis reset.72nZero WaitState n0WS Output. This active low signal is used to force zero wait state access cycles on the IBM PC Bus. This is an open-drain signal. An external pull-up resistor is typicallyprovided by the system.70nMemory16-Bit ChipSelect nMEMCS16Output. This active low signal is used to indicate that the present data transfer is a 16-bit memory cycle. TheCOM90C66 can be configured to use A19-A17 or A19-A11 to generate nMEMCS16. This is an open-drainsignal. An external pull-up resistor is typically providedby the system.5DESCRIPTION OF PIN FUNCTIONSPLCCPIN SYMBOL DESCRIPTION69nI/O 16-BitChip Select nIOCS16Output. This active low signal is used to indicate that the present data transfer is a 16-bit I/O cycle. A15-A2 areused to generate nIOCS16. This is an open-drain signal.An external pull-up resistor is typically provided by thesystem.73nSystem BusHigh Enable nSBHE Input. This active low signal is used to enable the COM90C66 to transfer data on D8-D15 of the Data Bus. TRANSMISSION MEDIA INTERFACE56, 55nPulse 2,nPulse 1nPULSE 2,nPULSE 1Output. These active low signals carry the transmit datainformation, encoded in pulse format, from theCOM90C66 to the LAN Driver.57Receive In RXIN Input. This signal carries the receive data informationfrom the LAN Driver to the COM90C66.MISCELLANEOUS51-47Memory BaseAddress Select MS0-MS4Input. These signals are generated by external switches.They are used by the memory decoder to select a blockof memory. These signals are connected to weakinternal pull-up resistors.46-44I/O BaseAddress Select IOS0-IOS2Input. These signals are generated by external switches.They are used by the I/O decoder to select a block of 16I/O locations. These signals are connected to weakinternal pull-up resistors.35-42Node ID Select NID0-NID7Input. These signals are generated by external switches.The Node ID code represents the node identification ofthis particular COM90C66. These signals are connectedto weak internal pull-up resistors.32nTransmitActivity LED nTXLED Output. This active low signal is used for direct connection to an LED through a resistor to V cc to indicatetransmit activity. This signal has 12mA sink capability.31nBoard SelectActivity LED nnBSLED Output. This active low signal is used for direct connection to an LED through a resistor to V cc to indicateboard activity. This signal has 12mA sink capability.6DESCRIPTION OF PIN FUNCTIONSPLCCPIN SYMBOL DESCRIPTION33, 34CrystalOscillator XTAL1,XTAL2An external parallel resonant 20 MHz crystal should beconnected to these pins. If an external 20 MHz TTL clockis used instead, it must be connected to XTAL1 with a390Ω pull-up resistor and XTAL2 should be left floating.59CA Clock CACLK Output. This is the start/stop CA clock and should be leftfloating for typical operation.58Clock CLK Output. This is a general purpose 5 MHz clock andshould be left floating for typical operation.1, 43Power Supply V cc+5 Volt Power Supply pin.21, 68Ground GND Ground pins.60-61No Connect NC Make no connection to these pins.7FIGURE 1 - COM90C66 OPERATION8PROTOCOL DESCRIPTIONNETWORK PROTOCOLCommunication on the network is based on a token passing protocol. Establishment of the network configuration and management of the network protocol are handled entirely by the COM90C66's internal microcoded sequencer. A processor or intelligent peripheral transmits data by simply loading a data packet and its destination ID into the RAM buffer and issuing a command to enable the transmitter. When the COM90C66 next receives the token, it verifies that the receiving node is ready by first transmitting a FREE BUFFER ENQUIRY message. If the receiving node transmits an ACKnowledge message, the data packet is transmitted followed by a 16-bit CRC. If the receiving node cannot accept the packet (typically its receiver is inhibited), it transmits a Negative AcKnowledgement message and the transmitter passes the token. Once it has been established that the receiving node can accept the packet and transmission is complete, the receiving node will verify the packet. If the packet is received successfully, the receiving node transmits an ACKnowledge message (or nothing if it is received unsuccessfully) allowing the transmitter to set the appropriate status bits to indicate successful or unsuccessful delivery of the packet. An interrupt mask permits the COM90C66 to generate an interrupt to the processor when selected status bits become true. Figure 1 is a flow chart illustrating the internal operation of the COM90C66.NETWORK RECONFIGURATIONA significant advantage of the COM90C66 is its ability to adapt to changes on the network. Whenever a new node is activated or deactivated, a NETWORK RECONFIGURATION is performed. When a new COM90C66 is turned on (creating a new active node on the network), or if the COM90C66 has not received an INVITATION TO TRANSMIT for 840 mS, or if a software reset occurs, the device causes aNETWORK RECONFIGURATION by sending a RECONFIGURE BURST consisting of eight marks and one space repeated 765 times. The purpose of this burst is to terminate all activity on the network. Since this burst is longer than any other type of transmission, the burst will interfere with the next INVITATION TO TRANSMIT, destroy the token and keep any other node from assuming control of the line.When any COM90C66 senses an idle line for greater than 82 µS, which will only occur when the token is lost, each COM90C66 starts an internal timeout equal to 146 µS times the quantity 255 minus its own ID. It also sets the internally-stored NID (next ID representing the next possible ID node) equal to its own ID. If the timeout expires with no line activity, the COM90C66 starts sending INVITATION TO TRANSMIT with the Destination ID (DID) equal to the currently-stored NID. Within a given network, only one COM90C66 will timeout (the one with the highest ID number). After sending the INVITATION TO TRANSMIT, the COM90C66 waits for activity on the line. If there is no activity for 74.7µS, the COM90C66 increments the NID value and transmits another INVITATION TO TRANSMIT using the NID equal to the DID. If activity appears before the 74.7µS timeout expires, the COM90C66 releases control of the line. During NETWORK RECONFIGURATION, INVITATIONS TO TRANSMIT will be sent to all 256 possible IDs. Each COM90C66 on the network will finally have saved a NID value equal to the ID of the COM90C66 that it released control to. At this point, control is passed directly from one node to the next with no wasted INVITATIONS TO TRANSMIT being sent to IDs not on the network until the next NETWORK RECONFIGURATION occurs. When a node is powered off, the previous node will attempt to pass it the token by issuing an INVITATION TO TRANSMIT. Since this node will not respond, the previous node will timeout and transmit another INVITATION TO TRANSMIT to an incremented ID and eventually a response will be received.9The time required to do a NETWORK RECONFIGURATION depends on the number of nodes in the network, the propagation delay between nodes, and the highest ID number on the network, but will be in the range of 24 to 61 mS.BROADCAST MESSAGESBroadcasting gives a particular node the ability to transmit a data packet to all nodes on the network simultaneously. ID zero is reserved for this feature and no node on the network can be assigned ID zero. To broadcast a message, the transmitting node's processor simply loads the RAM buffer with the data packet and sets the DID equal to zero. Figure 9 illustrates the position of each byte in the packet with the DID residing at address 01 HEX of the current page selected in the TRANSMIT command. Each individual node has the ability to ignore broadcast messages by setting the most significant bit of the ENABLE RECEIVE TO PAGE nn command (see Table 7) to logic "0".EXTENDED TIMEOUT FUNCTIONThere are three timeouts associated with the COM90C66 operation:Response TimeThe Response Time is equal to the round trip propagation delay between the two furthest nodes on the network plus the maximum turn around time (the time it takes a particular COM90C66 to start sending a message in response to a received message), which is approximately 12.7 µS. The round trip propagation delay is a function of the transmission media and network topology. For a typical system using RG62 coax in a baseband system, a one-way cable propagation delay of 31µS translates to a distance of about four miles. The flow chart in Figure 1 uses a value of 74.7µS (31 + 31 + 12.7) to determine if any node will respond.Idle TimeThe Idle Time is associated with a NETWORK RECONFIGURATION. Figure 1 illustrates that during a NETWORK RECONFIGURATION, one node will continually transmit INVITATIONS TO TRANSMIT until it encounters an active node.Every other node on the network must distinguish between this operation and an entirely idle line.During NETWORK RECONFIGURATION, activity will appear on the line every 82 µS. This82 µS is equal to the Response Time of 74.7 µSplus the time it takes the COM90C66 to retransmit another message (usually another INVITATION TO TRANSMIT).Reconfiguration TimeIf any node does not receive the token within the Reconfiguration Time, the node will initiate a NETWORK RECONFIGURATION.The ET2 and ET1 bits (bits 3 and 4 of the Configuration Register) allow the network to operate over longer distances than the four miles stated earlier. The logic levels on these bits control the maximum distances over which the COM90C66 can operate by controlling the three timeout values described above. See the description of the ET1 and ET2 bits, found in Table 8, for the table containing the combinations of these bits. It should be noted that for proper network operation, all COM90C66s connected to the same network must have the same Response Time, Idle Time, and Reconfiguration Time.LINE PROTOCOLThe ARCNET line protocol can be described as isochronous because each byte is preceded by a start interval and ended with a stop interval.Unlike asynchronous protocols, there is a constant amount of time separating each data byte. Each byte takes up exactly 11 clock intervals with a single clock interval being 400 nS in duration. As a result, one byte is10transmitted every 4.4 µS and the time to transmit a message can be precisely determined. The line idles in a spacing (logic "0") condition. A logic "0" is defined as no line activity and a logic "1" is defined as a negative pulse of 200 nS duration.A transmission starts with an ALERT BURST consisting of six unit intervals of mark (logic "1"). Eight-bit data characters are then sent with each character preceded by two unit intervals of mark and one unit interval of space. Five types of transmission can be performed as described below:Invitations To TransmitAn Invitation To Transmit is used to pass the token from one node to another and is sent by the following sequence:• An ALERT BURST• An EOT (End Of Transmission--ASCII code04 HEX)• Two (repeated) DID (Destination IDentification) charactersALERTBURST EOT DID DIDFree Buffer EnquiriesA Free Buffer Enquiry is used to ask another node if it is able to accept a packet of data and is sent by the following sequence:• An ALERT BURST• An ENQ (ENQuiry--ASCII code 85 HEX)• Two (repeated) DID (Destination IDentification) charactersData PacketsA Data Packet consists of the actual data being sent to another node and is sent by the following sequence:• An ALERT BURST• An SOH (Start Of Header--ASCII code 01 HEX)• An SID (Source IDentification) character • Two (repeated) DID (Destination IDentification) characters• A single COUNT character which is the 2's complement of the number of data bytes to follow if a short packet is being sent or 00 HEX followed by a COUNT character which is the 2's complement of the number of data bytes to follow if a long packet is being sent • N data bytes where COUNT = 256-N (or 512-N for a long packet)• Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is X16 + X15 + X2 + 1.ALERTBURST ENQ DIDDID11AcknowledgementsAn Acknowledgement is used to acknowledge reception of a packet or as an affirmative response to FREE BUFFER ENQUIRIES and is sent by the following sequence:• An ALERT BURST• An ACK (ACKnowledgement--ASCII code86 HEX) character Negative AcknowledgementsA Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the following sequence:• An ALERT BURST• A NAK (Negative AcKnowledgement--ASCII code 15 HEX) characterSYSTEM DESCRIPTIONThe System Block Diagram shown in Figure 2 illustrates a typical implementation of an ARCNET node using the COM90C66. The only external components required to complete an ARCNET node design are one or two bus transceivers (for 8-bit or 16-bit applications, respectively) and the LAN Driver, making the COM90C66 the most highly-integrated ARCNET solution. The COM90C66 provides for simple interfacing to both sides of the ARCNET system, namely the microprocessor and the transmission media.MICROPROCESSOR INTERFACEThe left half of Figure 2 illustrates a typical COM90C66 interface to the PC. The sections outlined in dotted lines represent the portion which distinguishes the 16-bit interface, while the remaining interface exists for both 8-bit and 16-bit applications. The interface consists of a 20-bit address bus, a 16-bit data bus and a control bus. All accesses to the internal RAM, the optional PROM and the internal registers are controlled by the COM90C66.The microprocessor's address lines are directly connected to the COM90C66. The address decoding circuitry of the COM90C66 monitors the address bus to determine valid accesses to the device.Figure 2 shows octal bus transceivers utilized as the interface between the microprocessor's data lines and the COM90C66. The transceivers are only necessary when interfacing to a high current drive data bus such as the IBM PC data bus, and may otherwise be omitted. The COM90C66 provides the nTOPL and nTOPH signals which control the direction of the external transceiver(s). The nTOPL signal is also activated during PROM Read Cycles.The microprocessor's control bus is directly connected to the COM90C66 and is used in access cycle communication between the device and the microprocessor. All accesses support zero wait state arbitration in most machines. The Control Bus has been optimized to support the intricacies of the IBM AT Bus and the EISA Bus.ALERTBURST ACK ALERTBURST NAK12TRANSMISSION MEDIA INTERFACEThe right half of Figure 2 illustrates the COM90C66 interface to the transmission media used to connect the node to the network. The HYC9058/68/88 may be used to drive the media. During transmission, the COM90C66 transmits a logic "1" by generating two 100 nS non-overlapping negative pulses, nPULSE1 and nPULSE2. These signals are sent to the LAN Driver, which in turn creates a 200 nS dipulse signal on the media. A logic "0" is transmitted by the absence of the two negative pulses, that is, the nPULSE1 and nPULSE2 outputs remain high, therefore there is an absence of a dipulse. During reception the 200 nS dipulse appearing on the media is coupled through the RF transformer of the LAN Driver. A positive pulse at the RXIN pin of the COM90C66 is interpreted as a logic "1". Again, if no dipulse is present, the COM90C66 interprets a logic "0".Typically, RXIN pulse occur at multiples of 400 nS. The COM90C66 can tolerate distortion of plus or minus 100 nS and still correctly capture the RXIN pulses.During Reset, the transmitter portion of the COM90C66 is disabled and the nPULSE1 and nPULSE2 pins are inactive high.The COM90C66 includes the nTXLED and nBSLED signals which, when tied to LEDs, provide indication of transmit and board access activity. In addition, it is possible for the user to completely disable the transmitter through software. These two unique features represent two of the improvements made in the diagnostics of the device. Please see the Improved Diagnostics section of this document for further detail.FUNCTIONAL DESCRIPTIONMICROSEQUENCERThe COM90C66 contains an internal microsequencer which performs all of the control operation necessary to carry out the ARCNET protocol. It consists of a clock generator, a 554 x 8 ROM, a program counter, two instruction registers, an instruction decoder, a no-op generator, jump logic, and reconfiguration logic.The COM90C66 derives a 5 MHz and a 2.5 MHz clock from the external crystal. These clocks provide the rate at which the instructions are executed within the COM90C66. The 5 MHz clock is the rate at which the program counter operates, while the 2.5 MHz clock is the rate at which the instructions are executed. The microprogram is stored in the ROM and theinstructions are fetched and then placed into the instruction registers. One register holds the op code, while the other holds the immediate data.Once the instruction is fetched, it is decoded by the internal instruction decoder, at which point the COM90C66 proceeds to execute the instruction. When a no-op instruction is encountered, the microsequencer enters a timed loop, in which case the program counter is temporarily stopped until the loop is complete.When a jump instruction is encountered, the program counter is loaded with the jump address from the ROM. The COM90C66 contains an internal reconfiguration timer which interrupts the microsequencer if it has timed out.At this point the program counter is cleared, after which the MYRECON bit of the Diagnostic Status Register is set.13FIGURE 2 - SYSTEM BLOCK DIAGRAM14FIGURE 3 - INTERNAL BLOCK DIAGRAM15FIGURE 4 – MEMORY SELECTORFIGURE 5 – PROM SELECTORFIGURE 6 – I/O SELECTOR16FIGURE 9 – RAM BUFFER PACKET CONFIGURATION17Table 1 – User Configuration of Memory Map18ADDRESS DECODINGThe COM90C66 includes address decoding circuitry that compares the value of the Address Bus to the address range selected by the Memory Select (MS0-MS4) and I/O Select (IOS0-IOS2) pins in order to determine processor accesses to the on-board PROM, the on-chip RAM, and I/O locations. By placing switches on the MS0-MS4 and the IOS0-IOS2 pins, the user configures the Memory Map and I/O Map according to the possible address ranges shown in Tables 1 and 2.Table 2 - User Configuration of I/O Map IOS2I0S1IOS0I/O ADDRESS RANGE 0000260-026F 0010290-029F 01002E0-02EF 01102F0-02FF 1000300-030F 1010350-035F 1100380-038F 11103E0-03EFMemory Address DecodingThe Memory Address Decoding circuitry is used to select a block from the memory map of the processor for PROM and RAM accesses. Figure 4 illustrates how the memory selection works. The MS4-MS0 pins are decoded through a 5 to 9 Decoder to generate a 9-bit value. These nine bits are compared to the A19-A11 lines of the Address Bus in order to select a particular 16K memory segment. Figure 7 illustrates a 16K block of memory that has been selected by the MS4-MS0 pins. The PROM occupies the upper 8K area of the selected 16K segment and is accessed when A13 = 1. The RAM occupies one of four selectable 2K areas of the selected 16K segment and is accessed when A13 = 0. A11 and A12 are used to determine which 2K segment of the lower 8K area will be used for the RAM buffer.Figure 5 illustrates how the external PROM selection works. The MS4-MS0 pins aredecoded through a 5 to 7 Decoder to generate a 7-bit value. These seven bits are compared to the A19-A13 lines of the Address Bus in order to select an 8K memory range. Figure 7 illustrates an 8K block of memory for the PROM. In I/O 16K x 8 Mode only a 16K memory range is selected for the PROM. Figure 8 illustrates a 16K block of memory for the PROM.The nENROM pin is used to enable decoding for the on-board PROM. If nENROM is connected to a logic "1", the COM90C66 will not generate the nPROM signal, the nTOPL signal, or the IOCHRDY signal for accesses to the PROM. In this configuration, the COM90C66 will only occupy a 2K segment of memory.I/O Address DecodingThis section is used to select a block of 16 I/O locations from the I/O map of the processor.Figure 6 illustrates how the I/O selection19。