基于单片机和TEA5767HN的FM收音机系统的设计

大学物理与电子学院课程设计报告基于TEA5767的数字调频收音机报告人：王世威专业：通信工程设计小组成员：王世威、何康目录前言 (3)一、主要器材介绍 (4)1.1 STC89C52单片机 (4)1.2 TEA5767收音模块儿 (4)1.3 1602LCD显示屏 (5)1.4 LM386音频功率放大器 (6)二、系统原理及功能介绍 (7)2.1数字FM收音机基本原理 (7)2.2系统功能介绍 (7)三、元件清单 (9)四、制作过程 (10)4.1 前期准备 (10)4.2 实物图 (10)4.3焊接过程中遇到的问题和注意事项 (12)五、程序 (13)六、结论 (23)前言十九世纪无线电通讯技术的发明，使通信摆脱了依赖导线的传统方式，是通信技术上的一次飞跃，也是人类科技史上的一个重要成就。

作为无线电通信的的杰出成果，收音机的发明极改变了人们的生活方式，给人们的生活带来了无穷的乐趣。

随着科技的发展，技术不断地更新换代，收音机也沿着矿石收音机、电子管收音机、晶体管收音机、集成电路收音机的轨道不断进步着。

近年来，随着DSP技术的发展，采用DSP技术研发的收音机芯片的出现，“硬件无线电”由“软件无线电”代替，大大降低了收音机制造业的门槛。

2006年凯隆电子与美国芯科实验室合作，开发出世界上第一台数字收音机。

数字技术收音机的问世，标志着传统模拟收音机将逐渐退出历史舞台。

收音机的数字时代已经到来。

数字调频收音机就是无线电模拟信号由天线感应后接收后，在同一块儿芯片里放大，然后转化为数字信号，再对数字信号进行处理，然后还原成模拟音频信号输出。

数字调频收音机体积小、重量轻、寿命长、频率稳定、操作简便等优点，使其在市场上越来越受欢迎。

本次项目设计，我们对数字调频收音机的原理在理论上进行了充分的了解，基于其基本理论，我们制作了一台数字调频收音机。

一、主要器材介绍本系统主要由STC89C52单片机、1602LCD显示屏、LM386音频功率放大器、TEA5767收音模块儿、电阻电容等组成。

[分享]单片机控制的TEA5767高性能FM收音机DIY（含原理图，源代码)Post By：2007-10-10 11:41:57本帖向大家介绍新型FM收音机的设计及制作。

想想当年我们是什么做收音机的。

高放混频，解调，立体声解码，锁相等好几个芯片，线路焊好了，但痛苦才开始。

有设备还好些，没有更苦。

为了找谐振点，不停的调电容电感，不停的换电容电感······终于有声音，但始终都没那么好。

现在，痛苦终于过去。

因为有了新一代的芯片TEA5767。

TEA5767 ，零调整。

线路又极其简单。

一个晶振，一个电感，几个电容完了。

通过I2C 接口送几个字节的数据进去就ok。

此主题相关图片如下：此主题相关图片如下：源代码：可以存台的版本。

本文用到的收音模块可到：/参考// WINAVR GCC// ATmega8// clock: internal 1Mhz#include <avr/io.h>#include <avr/interrupt.h>#include <avr/signal.h>#include <avr/delay.h>#include <avr/eeprom.h>#include '3310LCD_function.c'#define uchar uint8_t#define uint uint16_t#define SLA_W 0b11000000 #define SLA_R 0b11000001uchar senddata[5] ;uchar readdata[5] ;uchar search = 0;uchar search_up = 0;uchar mode = 1;uchar station = 0;uint pll = 0x29da; // 88Mhz uint fre = 8750;//-------------------------------// 延时void delay_ms(uint ms){uint i;for(i=0;i<ms;i++)_delay_loop_2(250);}//I2C主机模式输出void set5767(void){uchar i = 0;TWCR = (1<<TWINT)|(1<<TWSTA)|(1<<TWEN); // SEND START SIGNAL while (!(TWCR & (1<<TWINT))); // WAIT FOR START SIG//if ((TWSR & 0xF8) != START) ERROR();TWDR = SLA_W; // send addressTWCR = (1<<TWINT) | (1<<TWEN);while (!(TWCR & (1<<TWINT)));//if ((TWSR & 0xF8) !=MT_SLA_ACK) ERROR();for ( i = 0; i < 5; i++ ){TWDR = senddata;TWCR = (1<<TWINT) | (1<<TWEN); // send datawhile (!(TWCR & (1<<TWINT)));// if ((TWSR & 0xF8) != MT_DATA_ACK) ERROR();}TWCR = (1<<TWINT)|(1<<TWEN)|(1<<TWSTO); //SEND STOP SIGNAL//LCD_write_english_string(60,3,'sOK');}//I2C主机模式输入void read5767(void){uchar i = 0;TWCR = (1<<TWINT)|(1<<TWSTA)|(1<<TWEN); // SEND START SIGNAL while (!(TWCR & (1<<TWINT))); // WAIT FOR START SIG//if ((TWSR & 0xF8) != START) ERROR();TWDR = SLA_R; // send addressTWCR = (1<<TWINT) | (1<<TWEN);while (!(TWCR & (1<<TWINT)));for ( i = 0; i < 5; i++ ){TWCR = (1<<TWINT) | (1<<TWEN); // read datawhile (!(TWCR & (1<<TWINT)));readdata = TWDR ;// if ((TWSR & 0xF8) != MT_DATA_ACK) ERROR();}TWCR = (1<<TWINT)|(1<<TWEN)|(1<<TWSTO); //SEND STOP SIGNAL//LCD_write_english_string(10,3,'rOK');}void show_frequency(void){uint32_t nPLL =0; //Decuint32_t frequency = 0; //Khzuchar display_bit[5];uchar tbTmp1=readdata[1];uchar tbTmp2=readdata[0];tbTmp2&=0x3f;nPLL=pll ;//tbTmp2*256+tbTmp1;// calculate searched station frequencyif(senddata[2]&0x10)frequency =(unsigned long)(nPLL*82/10-225);elsefrequency =(unsigned long)(nPLL*82/10+225);display_bit[0] = frequency / 100000 ;if ( display_bit[0] == 0 ) display_bit[0] = 0x20;else display_bit[0] += 0x30;display_bit[1] = (frequency / 10000)%10 +0x30;display_bit[2] = (frequency / 1000)%10 +0x30;display_bit[3] = (frequency / 100)%10 +0x30; display_bit[4] = (frequency / 10)%10 +0x30; LCD_write_english_string(0,2,' ' );LCD_write_char(display_bit[0]);LCD_write_char(display_bit[1]);LCD_write_char(display_bit[2]);LCD_write_english_string(30,2,'.' );LCD_write_char(display_bit[3]);LCD_write_char(display_bit[4]);LCD_write_english_string(48,2,' MHz' );}void show_frequency2(void){uchar display_bit[5];display_bit[0] = fre / 10000 ;if ( display_bit[0] == 0 ) display_bit[0] = 0x20; else display_bit[0] += 0x30;display_bit[1] = (fre / 1000)%10 +0x30; display_bit[2] = (fre / 100)%10 +0x30;display_bit[3] = (fre/10) %10 +0x30;display_bit[4] = fre%10+0x30;LCD_write_english_string(0,2,' ' );LCD_write_char(display_bit[0]);LCD_write_char(display_bit[1]);LCD_write_char(display_bit[2]);LCD_write_english_string(30,2,'.' );LCD_write_char(display_bit[3]);LCD_write_char(display_bit[4]);LCD_write_english_string(48,2,' MHz' );}void show_rx_power(void){uchar temp;temp = (readdata[3]>>4);LCD_write_english_string(60,0,' ');LCD_write_char((temp/10)%10 + 0x30 ); LCD_write_char(temp%10 + 0x30 );}void show_rx_power_blank(void){LCD_write_english_string(60,0,' ');}void calculate_pll(void){uint32_t temp;temp = fre;pll = (uint)( ( (temp*10-225)*4000)/32768);}void init(void){DDRB = 0XFF;PORTB = 0XFF;DDRD = 0B11100000;PORTD = 0XFF;DDRC = 0B00000000;PORTC = 0Xff; // IO initdelay_nms(250);delay_nms(250);delay_nms(250);delay_nms(250);//TWITWBR = 12;TWCR = (1<<TWEN); //SEND STOP SIGNALOSCCAL=0x9d; // 8M系统内部时钟校准//设置MCU的I/O口DDRB |= LCD_RST | LCD_DC | LCD_CE | SPI_MOSI | SPI_CLK;SPSR |= (1<<SPI2X); // 设置SPI时钟倍速SPCR |= (1<<SPE)|(1<<MSTR); // 使能SPI接口，主机模式，4M时钟LCD_init(); //初始化液晶}//////////////////////////////////////////////////////////////////int main(void){init();uint x;senddata[0] = pll/256; //load 100MHz pllsenddata[1] = pll%256; // away's low side injection senddata[2] = 0b00100000;senddata[3] = 0b10010000;senddata[4] = 0b01000000;readdata[0] = senddata[0];readdata[1] = senddata[1];LCD_write_english_string(0,0,'FM STEREO' );//LCD_write_english_string(0,5,' stereo' );//LCD_write_english_string(0,2,' 99.1Mhz' );show_frequency();LCD_write_inverse_string(0,5,' UP ');LCD_write_inverse_string(48,5,' DOWN ');station = eeprom_read_byte(22);fre = eeprom_read_word( station *2);calculate_pll();show_rx_power_blank();senddata[0] = pll/256;senddata[1] = pll%256;set5767();delay_nms(200);//delay_nms(200);read5767();show_frequency2();show_rx_power();LCD_write_english_string(0,4,'CH' );LCD_write_char(station/10 +0x30);LCD_write_char(station%10 +0x30);while(1){start:if ( (PIND&0x0c) == 0x04){delay_nms(50);if ( (PIND&0x0c) == 0x04){LCD_write_english_string(48,5,' DOWN ' );delay_nms(200);x= 0;while(bit_is_clear(PIND, 3)){x++;if ( x > 65530 ) //判断是否长按{if ( mode ){mode = 0; //改变模式LCD_write_english_string(0,4,'SET CH' );LCD_write_char(station/10 +0x30);LCD_write_char(station%10 +0x30);}else{mode = 1; //改变模式LCD_write_english_string(0,4,'CH' );LCD_write_char(station/10 +0x30);LCD_write_char(station%10 +0x30);LCD_write_english_string(24,4,' ' );eeprom_write_word(station*2,fre);}loop_until_bit_is_set(PIND, 3);LCD_write_inverse_string(48,5,' DOWN '); goto start;}}//LCD_write_english_string(0,4,'KEY1 press' ); LCD_write_inverse_string(48,5,' DOWN ');if ( mode ){station --;if ( station < 1 ) station = 10; eeprom_write_byte( 22,station);//*pst = station *2;fre = eeprom_read_word( station *2); calculate_pll();show_rx_power_blank();senddata[0] = pll/256;senddata[1] = pll%256;set5767();delay_nms(200);delay_nms(200);read5767();show_frequency2();show_rx_power();LCD_write_english_string(0,4,'CH' ); LCD_write_char(station/10 +0x30); LCD_write_char(station%10 +0x30); }else{fre -=5;if ( fre <= 8750 ) fre = 10800;calculate_pll();show_rx_power_blank();senddata[0] = pll/256;senddata[1] = pll%256;set5767();delay_nms(200);delay_nms(200);read5767();show_frequency2();show_rx_power();}}if ( (PIND&0x0c) == 0x08){delay_nms(50);if ( (PIND&0x0c) == 0x08){LCD_write_english_string(0,5,' UP ');delay_nms(200);if ( mode ){loop_until_bit_is_set(PIND, 2);LCD_write_inverse_string(0,5,' UP ');station ++;if ( station >= 11 ) station = 1;eeprom_write_byte( 22,station);//*pst = station *2;fre = eeprom_read_word( station *2); calculate_pll();show_rx_power_blank();senddata[0] = pll/256;senddata[1] = pll%256;set5767();delay_nms(200);delay_nms(200);read5767();show_frequency2();show_rx_power();LCD_write_english_string(0,4,'CH' ); LCD_write_char(station/10 +0x30); LCD_write_char(station%10 +0x30); }else{fre +=5;if ( fre >= 10800 ) fre = 8750;calculate_pll();show_rx_power_blank();senddata[0] = pll/256;senddata[1] = pll%256;set5767();delay_nms(200);delay_nms(200);read5767();show_frequency2();show_rx_power();//loop_until_bit_is_set(PIND, 2);LCD_write_inverse_string(0,5,' UP ');}}}}}。

摘要本设计是一个数字调频收音机（FM），就是接受频率调制的无线电信号，经过解调还原成原信号的电子设备，利用单片机控制有FM功能的专用芯片,设计一个基于TEA5767模块的数字FM收音机。

本设计采用模块化设计，整个系统由控制模块，FM音频模块和功放模块组成。

本设计核心采用的是TEA5767芯片，它是由PHILIPS公司推出的针对低电压应用的单芯片数字调谐FM立体声收音机芯片。

TEA5767芯片内集成了完整的IF频率选择和鉴频系统，就可实现FM收音机的全部功能。

采用的是Lcd1602液晶显示屏，实现单片机的频率值与模块内部的寄存器（PLL值）之间的相互转换，从而带动功放的工作。

功能：自动收台，手动收台，液晶显示。

采用主要模块有：（1）STC89C52单片机模块。

（2）Lcd1602显示模块。

（3）TEA5767收音机模块。

关键词：STC89C52 Lcd1602 TEA5767模块目录摘要 (2)1.绪论 (5)1.1 课题背景 (5)1.2 课题概述 (5)2.设计要求与思路 (5)2.1 收音机的设计要求 (5)2.2 系统设计整体思路 (5)3.主要电路模块的实现方案比较及选择 (6)3.1 控制模块方案选择 (7)3.2 液晶显示模块方案选择 (7)3.3 无线芯片方案选择 (7)4．系统电路图 (8)4.1 微控制器模块 (8)4.2 FM模块 (9)4.2.1 FM模块介绍 (9)4.3 工作原理 (10)4.3.1串行总线工作模式 (10)4.3.2 串行总线基本操作 (10)4.3.3数据传送 (12)4.3.4、三线总线工作模式 (12)5.系统软件设计 (13)5.1 主程序设计 (13)5.2 流程图 (14)6.硬件电路测试与检测 (14)6.1 硬件装配 (14)6.2 系统测试 (14)7.结束语 (15)8.参考文献 (15)9.致谢 (15)10.附录 (16)10.1 电路原理图 (16)10.2 电路PCB图 (16)10.3 电路实物图 (17)10.3 元器件清单 (18)11.操作框图 (19)程序框图 (20)12.程序 (21)12.1 主程序 (21)12.2 I2C总线 (26)12.3 Lcd1602程序 (29)基于TEA5767模块的数字FM收音机设计一．绪论1.1课题背景随着科学技术的不断发展,新颖的调频收音机的不断出现,技术不断的提高,设计出来的收音机外型精致和小巧。

题目：基于单片机和TDA5767HN的收音机系统设计An overview of microcontrollerDescriptionThe AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. Function characteristicThe AT89C52 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during programverification.Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulledhigh by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C52 as listed below:Port 3 also receives some control signals for Flash programming and verification.RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN Program Store Enable is the read strobe to external program memory.When the AT89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched onreset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes programexecution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a randomvalue, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line ofone-chip computer the chips have,such as8052, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same.8052 daily representatives- 51 serial one-chip computers .An one-chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc.. ( 4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. ( 6) Five cut off cutting off the control system of the source . ( 7) One all duplexing serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. ( 8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertas now at most. Every theabove-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarilies of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on8052 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in8052 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as8052 basic beats of working, namely the minimum unit of time.8052 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in8052 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure8052 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data8052- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 byteses that can be appointed as the job register, this and general microprocessor is different,8052 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will,namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton.8052 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users,8052 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of8052: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8052 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing Output grade , P3 of mouth , P1 of P1 , connect with inside have load resistance of drawing , every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of8052 one-chip computers as P3 mouth in a normal way . Because draw resistance on output grade of them have, can open away collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outerly . Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first . As to 80C51one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base , in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into 0000H initially , make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally,as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in8052 China RST pin. Restore to the throne signal high level effective , should sustain 24 shake cycle (namely 2 machine cycles ) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal:Restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST ) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal insidly. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running,should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with the oscillograph tentatively, push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restoreto the throne circuit group holding value carry on the experiment to change.With the costant growing consumption of fossil energy, global energy crisis and environmental problems have become more and more acute. Among various green renewable energy resources, solar energy has drawn the attention from the scientific circles of various countries due to its unique advantages such as bountless storage content, cleaness and safety, and easiness to obtain. In particular, the application of solar photovoltaic technology has become a universal focus. China has relatively scarce fossil energy resources while a huge energy consumption. Therefore, the research and application of solar photovoltaic technology has important strategic meaning for the future economic development of China. A basic solar photovoltaic system is generally composed of solar panels, storage batteries, DC (direct current) control system and inverters, among which, DC control system is the central part of the solar photovoltaic system.The major content of this subject includes the development and application of the solar photovoltaic system, the classification of the solar photovoltaic system, solar photovoltaic cells, the design of DC (direct current) control system, settings of maximum power point tracking, circuit design and determination of the capacity of the inverter, and the settings of three-phase transformer and the AC (alternating current) distribution system.solar photovoltaic power, photovoltaic cells, DC (direct current) control system, AC (alternating current) distribution system.The8052 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAμE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approachby Aeroflex-United Technologies Microelectronics Center (UTMC), the commercial vendor of a radiation– hardened8052, that built their8052 microcontroller using radiation hardened processes. This broad range of technology within one device structure makesthe8052an ideal vehicle for performing this technology evaluation.The objective of this work is the technology evaluation of the CULPRiT process [3] from IAμE. The proc ess has been baselined against two other processes, the standard8052 commercial device from Intel and a version using state-of-the-art processing from Dallas Semiconductor. By performing this side-by-side comparison, the cost benefit, performance, and reliability trade study can be done.In the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as complete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more complete understanding of how to test complex structures, such as microcontrollers, and how to more efficiently test these structures in the future.IV. TEST DEVICESThree devices were used in this test evaluation. The first is the NASA CULPRIT device, which is the primary device to be evaluated. The other two devices are two versions of a commercial8052, manufactured by Intel and Dallas Semiconductor, respectively.The Intel devices are the ROM less, CMOS version of the classic 8052 MCS-51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to70 °C and at a clock speeds of 3.5 MHz to 24 MHz. They are manufactured in Intel’sP629.0 CHMOS III-E process.The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcontrollers, but they are enhanced in various ways. They are rated for operation from 4.25 to 5.5 V olts over 0 to 70 °C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, resulting in an effective processing ability that is roughly 2.5 times greater (faster) than the standard 8052 device. None of these features, other than those inherent in the device operation, were utilized inorder to maximize the similarity between the Dallas and Intel test codes.The CULPRiT technology device is a version of the MSC-51 family compatible C8052 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8052 device is designed to operate at a supply voltage of 500 mV and includes an on-chip input/output signal level-shifting interface with conventional higher voltage parts. The CULPRiT C8052 device requires two separate supply voltages; the 500 mV and the desired interface voltage. The CULPRiT C8052 is ROMless and is intended to be instruction set compatible with the MSC-51 family.V. TEST HARDWAREThe8052 Device Under Test (DUT) was tested as a component of a functional computer. Aside from DUT itself, the other componentsof the DUT computer were removed from the immediate area of the irradiation beam. A small card (one per DUT package type) with a unique hard-wired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This "DUT Board" was connected to the "Main Board" by a short 60-conductor ribbon cable. The Main Board had all other components required to complete the DUT Computer, including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch).The DUT Computer and the Test Control Computer were connected via a serial cable and communications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for commanding of the DUT, downloading DUT Code to the DUT, and real-time error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latchup.VI. TEST SOFTWAREThe8052 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the8052 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT computer. In this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established communications between the controller PC and the DUT.All test programs implemented:• An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and communication to controller computer.• An external real-time clock for data error tag.• A watchdog routine designed to provide visual verification of8052 health and restart test code if necessary.• A "foul-up" routine to reset program counter if it wanders out of code space.• An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission.The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured.Interrupt – This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the accumulator which was periodically compared to a known value. Unexpected values were transmitted with register information.Logic – This test performed a series of logic and math computations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3)multiplication/division. All miscompares of computations and expected results weretransmitted with other relevant register information.Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern. Compares were performed continuously and miscompares were corrected while error information and register values were transmitted.Program Counter -The program counter was used to continuously fetch constants at various offsets in the code. Constants were compared with known values and miscompares were transmitted along with relevant register information.Registers – This test loaded each of four (0,1,2,3) banks of general-purpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls general-purpose register bank selection. General-purpose register banks were then compared with their expected values. All miscompares were corrected and error information was transmitted.Special Function Registers (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly compared the learned value with the current one. Miscompares were reloaded with learned value and error information was transmitted.Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information.VII. TEST METHODOLOGYThe DUT Computer booted by executing the instruction code located at address0x0000. Initially, the device at this location was an EPROM previously loaded with "Boot/Serial Loader" code. This code initialized the DUT Computer and interface through a serial connection to the controlling computer, the "Test Controller". The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time (~10 ms); and, remapped the Test Code residing in the Program Code RAM to locate it to address 0x0000 (the EPROM will。

摘要现在人们常使用的收音机为手动调频收台，使用较为麻烦，而且由于接收灵敏度不高，所接收的频段较窄。

TEA5767具有高性能的RF AGC电路，其接收灵敏度高、参考频率选择灵活、可实现自动搜台。

本课题采用STC89C52单片机和TEA5767为核心器件，用I2C通信方式联接单片机与TEA5767，实现数字FM 收音机系统。

通过编写软件利用单片机控制TEA5767实现手动活自动调频，收到的信号通过TAD2030功放器件放大后，再用扬声器输出信号。

在调频的过程中可以通过LCD1602液晶显示屏来随时查看信号的频率。

关键词：数字调频； STC89C52； TEA5767； TDA2030ABSTRACTNowadays people usually use the radio for manual FM accept , it is much trouble, and because the rx sensitivity is not high, the frequency band received is very narrow。

TEA5767 has high-performance RF AGC circuit, high sensitivity receiving, reference frequency selection flexible and it can be the realization of automatic search platform。

So in this designing I will use the STC89C52 single-chip microcomputer and TEA5767 as the core components of digital FM radio system and Use the I2C communication to connect between STC89C52 and TEA5767 chip。

基于单片机的数字FM收音机设计摘要：本文在具体分析了STC89C52单片机的技术特点与数字FM收音机的基础上，提出了采用单片机控制收音机实现数字调频的方法，并给出了具体的软硬件设计。

该系统利主要由STC89C52单片机、液晶显示器、按键、调频收音模块TEA5767、功放LM386组成[1]。

实际运行时，用TEA5767搜索频率，利用单片机STC89C52控制处理，经LM386芯片放大音频功率同时再通过液晶显示器显示频率，最终实现87.5MHz～108MHz调频广播的接收。

相关的功能验证实验表明，本系统达到了既定的设计目标。

关键词：单片机技术；收音机；频率搜索；液晶显示The Design of Digital FM Radio Which Based on Single ChipMicrocomputerAbstract:This paper mainly proposes the method of using single chip computer to control digital FM radio . It gives the specific hardware and software design which based on a detailed analysis on of the technical characteristics of STC89C52 SCM and digital FM radio. The system uses STC89C52 SCM as CPU for overall control, mainly composed of STC89C52 SCM, LCD display, keypad, FM radio module TEA5767 and LM386 amplifier. When it operates, firstly you should use the TEA5767 display to show the search frequency. Then, control and process it with STC89C52 SCM. By the way magnify the audio power through LM386 chip. The LCD display frequency. Ultimatel y, it’ll reach a broadcast reception range from 87.5MHz to 108MHz FM. Some related functional verification experiments show that the system achieves the established design goals.Keywords:SCM technology; Radio; Frequency search;Liquid-crystal display目录序言 (1)第1章课题分析与方案论证 (2)1.1 课题任务分析 (2)1.2 方案论证 (2)第2章硬件电路 (5)2.1主控电路 (5)2.2音频输出电路 (9)2.3FM收音电路 (12)2.4LCD1062液晶屏模块 (15)2.5按键电路 (16)2.6I2C总线简介 (16)2.7电路装配注意事项 (18)第3章软件设计 (19)3.1主程序设计 (19)3.2液晶屏显示控制子程序 (21)3.3收音机控制子程序 (23)第4章系统测试 (25)4.1硬件测试 (25)4.2软件测试 (25)4.3整机调试 (26)4.4调试结果 (26)结束语 (27)参考文献 (28)致谢 (29)附录 (30)附录1 程序清单 (30)附录2 硬件原理图 (42)附录3 硬件实物图 (43)附录4 外文资料原文 (44)外文资料译文 (50)序言当前时代，虽然电视、手机、互联网等媒体和各种便携式娱乐设备已经普及到千家万户，但传统的收音机在丰富的娱乐媒介中任然占有重要地位。

基于TEA5767的智能收音机的开题报告郑州大学西亚斯国际学院本科生毕业论文（设计）开题报告题目名称基于单片机和TEA5767模块智能收音机的设计学生姓名张晓宇专业自动化学号20101523341指导教师姓名周伟所学专业自动化职称讲师完成期限2014年2月27日至2014年5月20日一、选题的目的意义：随着社会科技的发展，各种数字电子产品进入我们的生活，虽然智能手机、智能电视已经变得越来越普遍、但是收音机在丰富的娱乐媒介和广大司机朋友，老人及各位观众听友们里还是占有很重要的地位。

现在大都电子产品都在向数字化、集成化发展而且成本越来越低，使得广大厂商在各种设备中嵌入收音机诸如MP3，智能手机，便携式video播放器等电子产品中嵌入FM部分。

这是因为飞利浦公司研发的TEA5768设计的数字FM收音机使这种低成本的实现可能，它可以实现手动、自动、搜台和存台、带有I2C 和3-Wire 两个总线接口, 最小供电电压为2.5V, 外围只需要少量元器件即可实现FM收音机功能, 具有体积小、功耗低、频率稳定性好、高灵敏度、高保真等特点。

EA5767HN芯片是PHILIPS公司推出的针对低电压应用的单芯片数字谐调FM立体声收音机芯片。

它采用创新的收音机架构取代了外部的无源器件与复杂的线路，芯片内集成了完整的IF频率选择和鉴频系统，只需很少的低成本外围元件，就可实现FM收音机的全部功能，硬件系统完全不需要调试。

EA5767HN 芯片前端具有高性能的RF AGC电路，其接收灵敏度高，并且兼容欧洲、美国和日本FM频段；参考频率选择灵活，可通过寄存器设臵选择32.768kHz和13MHz的晶体振荡器或者6.5MHz的外部时钟参考频率；可通过IIC系统总线进行各种功能控制并通过IIC总线输出7位IF计数值；立体声解调器完全免调，可用软件控制SNC、HCC、暂停和静音功能；具有两个可编程I/O口，可用于系统的其他相关功能；由于其软件设计简单，再加上小尺寸的封装，使得它非常适合应用于电路板空间相当有限的设计上；可集成到便携式数码消费产品的设计中，如移动电话、MP3播放器、便携式CD 机、玩具等众多产品，使它们具有FM收音功能。

基于TEA5767模块的数字FM收音机设计：指导老师：摘要本设计是一个数字调频收音机（FM），就是接受频率调制的无线电信号，经过解调还原成原信号的电子设备，利用单片机控制有FM功能的专用芯片，设计一个收音机系统。

本设计采用模块化设计，整个系统由控制模块，FM音频模块，电源模块和功放模块组成。

未处理系统采用单片机控制。

单片机自从20世纪70年代问世以来，以极其高的性能价格比受到人们的重视和关注，所以应用很广，发展很快。

STC89C52单片机的特点是体积小、集成度高、重量轻、抗干扰能力强，对环境要求不高，价格低廉，可靠性高，灵活性好，开发较为容易。

本设计另一核心采用的是TEA5767芯片，它是由PHILIPS公司推出的针对低电压应用的单芯片数字调谐FM立体声收音机芯片。

TEA5767芯片集成了完整的IF频率选择和鉴频系统，就可实现FM收音机的全部功能。

设计的液晶屏采用的是Nokia5110，该液晶屏的性价比高，接口简单，速度快，适合便携式供电设备。

本设计主要是体现单片机系统的自动控制能力，更重要的意义是单片机的应用改变了控制系统传统的设计思想和方法。

关键词：STC89C52 Nokia5110 TEA5767AbstractThe design is a digital FM radio (FM), It is to receive the frequency modulated radio signals, electronic equipment restored to the original signal after demodulation, the use of dedicated chip MCU control FM functions, design a radio system. The system consists of the control module, FM audio module, power module and power amplifier module. The The micro-processing system microcontroller. The singlechip has come out since the 1970s, compared to is valued people's and the attention by the extremely high performance price, therefore the application is very broad, the development is very quick.STC89C52 Monolithic integrated circuit's characteristic is the volume is small, theintegration rate is high, the weight is light, antijamming ability, is not high to the environment request, the low in price, the reliability is high, the flexibility is good, the development is easier. What this design uses is the TEA5767 chip, it is promotes by PHILIPS Corporation in view of the low voltage application single chip digit harmonious FM stereophonic receiver chip. In the TEA5767 chip integrated the complete IF frequency selection and the frequency discrimination system, only need the very few low cost periphery part, be possible to realize the FM radio's complete function.The design of the LCD screen is Nokia5110, The LCD screen have high cost , simple interface, fast, and suitable for portable power supply equipment. A more vital significance was monolithic integrated circuit's application changed the control system tradition design concept and the method.Keywords：STC89C52 , Nokia5110 , TEA5767目录摘要 (2)Abstract (3)目录 (5)绪论 ........................................................ 错误!未定义书签。

ELECTRONIC ENGINEERING & PRODUCT WORLD2022.4电子产品世界基于单片机的FM收音机设计Design of home internet detection system based on STM32许可嘉，杨晓军 （成都大学电子信息与电气工程学院，成都610106）摘 要：该设计是单片机控制电路与TEA5767模块电路及音频功率放大电路共同组成的FM收音机电路，用来实现频道接收、保存、播放等功能。

系统采用STC89C52为主控，TEA5767作为数字信号处理器，I2C总线协议为主控与数字信号处理器之间的通信协议，可以实现频道自动搜索、接收、保存、播放等功能。

通过LCD显示器实时显示当下操作及相应频道所在频率。

最终测试结果表明：该设计可以实现频率在87.5 MHz~108 MHz调频广播的接收，本设计能够达到了既定的设计目标。

关键词：单片机；FM收音机；TEA5767；I2C总线随着现代科学技术的不断发展，电子产品也不断更新换代，单片机的广泛应用使用使现在的电子产品设计越来越方便、功能越来越好，而单片机是所有微处理器中性价比最高的一种，它的功能不断完善，种类不断增加，因此它的应用领域也不断扩大，本文我们将单片机与FM收音机芯片综合运用起来，设计了一款可以实现调频、存台的FM收音机系统。

1 系统方案1.1 系统总体设计该系统设计采用模块化设计，主要由存储模块，主控制器，数字处理芯片和音频功率放大器组成。

系统工作原理框图如图1所示，由主控制器接收按键信号进行人机交互，通过I2C总线，主控制器作为主机，TEA5767为从机，双机通信，TEA5767芯片输出音频信号经LM386放大后通过耳机或扬声器播放，系统运行时，收听电台的频率可在LCD显示器上实时显示，通过按键手动控制频率搜台，或切换至自动搜台模式，音频输出设备音量可由电位器调节[8]。

2 系统硬件设计该系统的硬件设计部分分为TEA5767数字处理电路、主控制器电路和音频功放电路。