NXP CorporateOverview_12_2015_partner
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nxp的芯片NXP Semiconductors是一家总部位于荷兰的全球领先的半导体公司。
它专注于提供广泛的高性能芯片解决方案,用于汽车、物联网、新能源和工业等多个领域。
NXP的芯片具有卓越的性能、高度集成和可靠性。
首先,NXP的芯片在汽车电子领域具有很高的知名度和影响力。
它们被广泛应用于汽车的智能驾驶、车载娱乐、车身电子、车辆网络和安全系统等方面。
例如,NXP的车载电源管理芯片可以提供高效的能量转换,使车辆的能源供应更加可靠和节能。
此外,NXP的汽车雷达芯片能够实现更高精度的障碍物检测,提高自动驾驶系统的性能和安全性。
其次,NXP的芯片在物联网领域发挥着重要作用。
它们支持物联网设备之间的无线通信和数据传输,并在智能家居、智能城市和工业自动化等领域得到广泛应用。
例如,NXP的无线射频识别(RFID)芯片用于物流管理和供应链追踪,可以实现实时跟踪和管理物品的位置和状态。
此外,NXP的低功耗蓝牙芯片可实现智能家居设备的互联互通,提供更便捷和智能的生活体验。
此外,NXP的芯片在新能源领域也具有重要意义。
它们被广泛应用于电动汽车、光伏发电和智能电网等新能源系统中。
例如,NXP的电动汽车控制芯片可实现电动汽车的精确控制和高效能源管理,提高电动汽车的性能和里程。
此外,NXP的太阳能逆变器芯片可实现光伏发电系统的高效能量转换,提高太阳能发电的效率和可靠性。
最后,NXP的芯片在工业领域发挥着重要的作用。
它们用于工业控制系统、机器人和自动化设备中,提高生产效率和制造质量。
例如,NXP的工厂自动化控制芯片能够实现复杂的运动控制和精确的位置检测,提高机器人和自动化设备的精度和稳定性。
此外,NXP的无线传感器芯片可实现工厂设备的智能监控和预测性维护,提高设备的可靠性和生产效率。
综上所述,NXP的芯片在汽车、物联网、新能源和工业等领域具有很高的应用价值。
它们通过提供高性能、高集成度和可靠性的解决方案,推动了各个行业的技术创新和发展。
REVISION HISTORYDECLARATIONTABLE OF CONTENTS5.3. DC Electrical Characteristics2.6.Memory Subsystem&Touch G-SENSORSPI1_CLK UART3_RX42 DDR3_D743 VCC3_DRAM79 AGND80 VRPSDC0_CMD 111PF3PE9 CSI_D6LCD_D10 141PD10PC19 163 VCC4function 0);3)Type: signal directionPC7 Input PC8 InputPE4 Input PE5 InputSignal Name DescriptionOthersVRP Reference voltageV IH High-Level Input Voltage V IL Low-Level Input VoltageFigure 5-1. Power Up Sequence5.5.2.Power Up Reset Sequence RequirementsThe device has a system reset signal to reset the board. When asserted, the following steps give an example of power up reset sequence supported by the R8 device.•AVCC ,VDD_CPU and VCC_DRAM can be powered up simultaneously.•VDD_INT can be powered up after VDD_CPU is powered up, the time difference is T1ms.•VCC can be powered up after VDD_INT is powered up, the time difference is T2ms.Figure 5-2. Power Up Reset Sequence5.5.3.Resume Power Up Sequence from Super Standby ModeTo resume a power up sequence when the device is in Super Standby mode:•VCC_DRAM and AVCC remains powered up always.•VDD_CPU can be powered up firstly.•VDD_INT can be powered up after VDD_CPU is powered up, the time difference is T1ms.•VCC can be powered up after VDD_INT is powered up, the time difference is T2ms.Figure 5-3. Exit Super Standby and Resume Power Up Sequence5.5.4.Power Down Sequence RequirementsTo reduce power consumption,the R8 can be partially powered down.The section lists the power down requirements in each mode.In Super Standby mode,•VCC_DRAM and AVCC must be kept powered up.•VDD_CPU,VDD_INT and VCC are powered down simultaneously.•VCC voltage fall time is more longer than VDD_INT.VDD_CPUVDD_CPU6.PIN ASSIGNMENT6.2.PACKAGE DIMENSIONThe following diagram shows the package dimension of R8.。
nxp 芯片
NXP是一家全球领先的半导体解决方案供应商,提供广泛的
高性能、高可靠性的芯片产品和解决方案。
NXP的芯片广泛
应用于汽车、通信、家庭娱乐、工业控制等领域,为客户提供安全、智能、高效的解决方案。
NXP的芯片在汽车领域表现突出。
汽车是NXP的主要市场之一,NXP芯片在汽车电子控制单元(ECU)、车载娱乐系统、驾
驶员辅助系统等方面提供了高级解决方案。
例如,NXP的汽
车介电层嵌入式处理器(PoP)芯片是全球最先进的汽车电子芯
片之一,集成了高性能的处理器、内存、图形引擎和安全模块,支持车载娱乐、导航、车载通信等多种应用。
在通信领域,NXP的芯片被广泛应用于移动通信、无线通信
和卫星通信等领域。
例如,NXP的RFID芯片是全球领先的RFID技术之一,能够实现无线物联网应用。
此外,NXP还提
供高性能的射频功率放大器(PA)芯片,用于增强信号传输和接收性能。
在家庭娱乐领域,NXP的芯片提供了丰富的解决方案。
例如,NXP的音频处理芯片可以实现高保真音频输出和音频信号处理。
此外,NXP还提供了高性能的图形处理芯片,支持高清
视频播放和图形处理。
在工业控制领域,NXP的芯片应用于各种工业自动化设备和
控制系统中,支持实时控制、数据采集和通信。
例如,NXP
的工业控制芯片可以实现高性能的实时数据处理和精确控制。
总之,NXP的芯片在汽车、通信、家庭娱乐和工业控制等领域提供了广泛的解决方案。
通过不断创新和技术升级,NXP 始终致力于为客户提供安全、智能、高效的芯片产品和解决方案。
芯片nxp
NXP Semiconductors的一款芯片为NXP1000。
该芯片具有以下特性:
1. 低功耗:该芯片采用低功耗设计,能够节省电池能量,延长设备续航时间。
2. 高性能:NXP1000芯片具备强大的处理能力和高速数据处理能力,可以处理复杂的计算任务和大数据流。
3. 多功能性:该芯片支持多种通信接口,如蓝牙、Wi-Fi、NFC等,可以与其他设备进行无线通信和数据传输。
4. 安全性:NXP1000芯片采用先进的安全性能,包括数据加密、身份认证和漏洞防护等,保障设备和数据的安全。
5. 可靠性:该芯片具有高可靠性和稳定性,能够适应各种工作环境和应用场景。
总的来说,NXP1000芯片是一款具备低功耗、高性能、安全可靠的多功能芯片,适用于各种智能设备和物联网应用。
Preview of i.MX 8M Plus Applications Processor Reference ManualGet entire reference manual (7406 pages, PDF)Document Number: IMX8MPRMRev. 1, 06/2021ContentsSection number Title PageChapter 1Introduction1.1Product Overview (9)1.2Target Applications (9)1.3Acronyms and Abbreviations (9)1.4Architectural Overview (12)Chapter 2Memory Map2.1Memory system overview (23)2.2Cortex-A53 Memory Map (24)2.3Cortex-M7 Memory Map (26)2.4DMA memory maps (29)2.5AIPS Memory Maps (30)2.6DAP Memory Map (36)2.7Audio Processor Memory Map (38)2.8HDMI_TX Subsystem Memory Map (38)Chapter 3Security3.1System Security (41)3.2Resource Domain Controller (RDC) (44)Chapter 4Arm Platform and Debug4.1Arm Cortex A53 Platform (A53) (91)4.2Arm Cortex M7 Platform (CM7) (97)4.3Messaging Unit (MU) (99)4.4Semaphore (SEMA4) (143)4.5On-Chip RAM Memory Controller (OCRAM) (161)4.6Network Interconnect Bus System (NIC) (164)4.7AHB to IP Bridge (AIPSTZ) (165)4.8Shared Peripheral Bus Arbiter (SPBA) (188)4.9TrustZone Address Space Controller (TZASC) (201)4.10System Debug (203)4.11System Counter (SYS_CTR) (207)Chapter 5Clocks and Power Management5.1Clock Control Module (CCM) (227)5.2General Power Controller (GPC) (566)5.3Crystal Oscillator (XTALOSC) (718)5.4Thermal Monitoring Unit (TMU) (722)Chapter 6SNVS, Reset, Fuse, and Boot6.1System Boot (741)6.2Fusemap (808)6.3On-Chip OTP Controller (OCOTP_CTRL) (824)6.4Secure Non-Volatile Storage (SNVS) (868)6.5System Reset Controller (SRC) (897)6.6Watchdog Timer (WDOG) (968)Chapter 7Interrupts and DMA7.1Interrupts and DMA Events (987)7.2Smart Direct Memory Access Controller (SDMA) (1008)7.3Enhanced Direct Memory Access (eDMA) (1256)7.4Interrupt Request Steering (IRQ_STEER) (1318)Chapter 8Chip IO and Pinmux8.1External Signals and Pin Multiplexing (1329)8.2IOMUX Controller (IOMUXC) (1352)8.3General Purpose Input/Output (GPIO) (1982)Chapter 9External Memory9.1External Memory Overview (2001)9.2DDR Controller (DDRC) (2003)9.3DDR BLK_CTRL (2164)9.4DDR PHY (DDR_PHY) (2166)9.5AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) (2177)9.662BIT Correcting ECC Accelerator (BCH) (2217)9.7General Purpose Media Interface (GPMI) (2280)Chapter 10Mass Storage10.1Enhanced Configurable SPI (ECSPI) (2339)10.2FlexSPI Controller (FlexSPI) (2369)10.3Ultra Secured Digital Host Controller (uSDHC) (2500)Chapter 11Connectivity11.1HSIO BLK_CTRL (2659)11.2Universal Serial Bus Controller (USB) (2680)11.3Universal Serial Bus PHY (USB_PHY) (2993)11.4PCI Express (PCIe) (2997)11.5PCI Express PHY (PCIe_PHY) (3369)11.6Ethernet MAC (ENET) (3754)11.7Ethernet Quality Of Service (ENET_QOS) (3957)11.8FlexCAN (4980)Chapter 12Timers12.1General Purpose Timer (GPT) (5123)12.2Pulse Width Modulation (PWM) (5142)Chapter 13Display, Imaging, and Camera13.1Display, Imaging, and Camera Overview (5155)13.2MEDIA BLK_CTRL (5163)13.3LCD Interface (LCDIF) (5233)13.4Image Sensing Interface (ISI) (5265)13.5MIPI CSI Host Controller (MIPI_CSI) (5347)13.6MIPI DSI Host Controller (MIPI_DSI) (5396)13.7MIPI D-PHY (MIPI_DPHY) (5469)13.8LVDS Display Bridge (LDB) (5493)13.9HDMI TX Controller (5496)13.10HDMI TX PHY (5779)13.11HDMI TX BLK_CTRL (5828)13.12HDMI TX Parallel Audio Interface (HTX_PAI) (5859)13.13HDMI TX Parallel Video Interface (HTX_PVI) (5871)13.14Image Signal Processor (ISP) (5895)13.15DeWarp (5901)13.16Machine Learning Neural Processing Unit (NPU) (5907)Chapter 14Audio14.1Audio Overview (5943)14.2AUDIO BLK_CTRL (5947)14.3PDM Microphone Interface (MICFIL) (5977)14.4Synchronous Audio Interface (SAI) (6023)14.5Asynchronous Sample Rate Converter (ASRC) (6077)14.6Enhanced Audio Return Channel (eARC) (6162)14.7Audio DSP (HiFi 4 DSP) (6231)Chapter 15Graphics Processing Unit (GPU)15.1GPU Overview (6239)15.22D Graphics Processing Unit (GPU2D) (6240)15.33D Graphics Processing Unit (GPU3D) (6254)Chapter 16Video Processing Unit (VPU)16.1VPU G1 Decoder (6263)16.2VPU G2 Decoder (6429)16.3VPU VC8000E Encoder (6665)16.4VPU BLK_CTRL (7256)Chapter 17Low Speed Communication and Interconnects17.1I2C Controller (I2C) (7269)17.2Universal Asynchronous Receiver/Transmitter (UART) (7293)Chapter 1Introduction1.1Product OverviewThis chapter introduces the architecture of the i.MX 8M Plus Applications Processor. The i.MX 8M Plus family is a set of NXP products focused on machine learning applications, combining state-of-art multimedia features with high-performance processing optimized for low-power consumption.The i.MX 8M Plus Applications Processor relies on a powerful fully coherent core complex based on a quad Cortex-A53 cluster, a Cortex-M7 coprocessor, audio digital signal processor, machine learning and graphics accelerators.The i.MX 8M Plus provides additional computing resources and peripherals:•Advanced security modules for secure boot, cipher acceleration and DRM support •A wide range of audio interfaces•Large set of peripherals that are commonly used in consumer/industrial markets including USB , PCIe, Ethernet, and CAN1.2Target ApplicationsThe i.MX 8M Plus Media Applications Processor targets applications on:•Smart Homes, Buildings and Cities•Machine Learning and Industrial Automation•Consumer and Pro Audio/Voice Systems1.3Acronyms and AbbreviationsThe table below contains acronyms and abbreviations used in this document.Acronyms and AbbreviationsAcronyms and Abbreviated TermsTerm Meaning ADC Analog-to-Digital ConverterAHB Advanced High-performance BusAIPS Arm IP BusALU Arithmetic Logic UnitAMBA Advanced Microcontroller Bus ArchitectureAPB Advanced Peripheral BusASRC Asynchronous Sample Rate ConverterAXI Advanced eXtensible InterfaceCA/CM Arm Cortex-A/Cortex-MCAAM Cryptographic Acceleration and Assurance Module CA53Arm Cortex A53 CoreCAN Controller Area NetworkCM7Arm Cortex M7 CoreCPU Central Processing UnitCSI CMOS Sensor InterfaceCSU Central Security UnitCTI Cross Trigger InterfaceD-cache Data cacheDAP Debug Access PortDDR Double data rateDMA Direct memory accessDPLL Digital phase-locked loopDRAM Dynamic random access memoryECC Error correcting codesECSPI Enhanced Configurable SPILPSPI Low-power SPIEDMA Enhanced Direct Memory AccessEIM External Interface ModuleENET EthernetEPIT Enhanced Periodic Interrupt TimerEPROM Erasable Programmable Read-Only MemoryETF Embedded Trace FIFOETM Embedded Trace MacrocellFIFO First-In-First-OutGIC General Interrupt ControllerGPC General Power ControllerGPIO General-Purpose I/OGPR General-Purpose RegisterGPS Global Positioning SystemTable continues on the next page...Continue Reading This Reference ManualGet entire reference manual (7406 pages, PDF)Stay informed when design resources related to this product are updated.Go to i.MX 8M Plusi.MX 8M Plus Applications Processor Reference Manual, Rev. 1, 06/202111NXP Semiconductors。
绿色节能,恩智浦助你完成低功耗电源设计
电子发烧友网讯:近几年,随着技术的发展,各种电子产品如雨后春笋般冒出来,就拿智能手机来说,从2007年苹果发布第一代iPhone以来,安卓和苹果两个阵型在之后的几年里展开了硬件竞赛,这点在安卓各个手机厂商中越演越烈,屏幕从以前的2.4甚至1.8英寸,一跃跳到了现在的动不动是4.5,乃至7寸的手机,同时在CPU等方面的性能也翻了几番,随之而来就是在电源消耗方面也有了迅猛的增长,这样就给我们带来了庞大的之处。
同样的情况在电脑,平板电脑,白电等产品中也有出现。
如何做好电源低功耗设计,这就成为厂商亟待考虑的问题。
恩智浦半导体于2012年11月14日在深圳马可孛罗好日子酒店举办了一个GreenChip电源技术应用研讨会,和相关行业的工程师一起分享交流了他们在智能家电、charger和adapter等方面的设计方案。
让我们看看能否透过大厂家的方案获取到有用的信息,以方便我们设计借鉴。
大会的第一个议程就是恩智浦电源方案IC事业部的资深产品经理张锡亮给我们大概介绍了NXP的GreenChip电源管理方案。
NXP的张锡亮经理在演讲。
Using the CSE (Cryptographic Services Engine) Module in MCAL4.3by: NXP Semiconductors1 IntroductionToday, people are concerned about sharing/transmittinginformation in a secure and trusted manner betweenparties in the automotive area. The security functionsimplemented with Cryptographic Services Engine(CSE)module are described in the Secure HardwareExtension(SHE) functional specification.This application note provides an introduction to theCSE module on the MPC5777C and explains how toconfigure and use this module in MCAL4.3. Afterreading this application note, you should be able to:• Understand the CSE configuration process inMCAL4.3• Understand how CSE module working on theMPC5777CThe application note also provides examples for specificconfigurations. The examples are provided in thesoftware package accompanying this document and isalso explained in detail. To aid in understanding of thisdocument and software package, you need to downloadthe MPC5777C reference manual from the NXPwebsite. The following table shows the abbreviationsused throughout the document.NXP SemiconductorsDocument Number: AN 13061 Application Notes Rev. 0 , 12/2020 Contents 1 Introduction ............................................................................ 1 3 CSE module on MPC5777C device ....................................... 2 3.1 Chip-specific CSE information ............................... 2 3.2 Main features .......................................................... 2 3.3 Modes of operation ................................................. 3 3.4 Block diagram ......................................................... 3 4 AES-128 encryption and decryption overview ....................... 5 4.1 Electronic Codebook (ECB) ................................... 5 4.2 Chiper-block chaining (CBC) ................................. 5 4.3 CMAC (Cipherbased Message Authentication Code) 6 5 CRYPTO module in MCAL4.3 ......................................... 7 6 CRYPTO loading key and processing primitive .............. 11 7 References . (12)2 CSE module on MPC5777CTable 1. Abbreviations and acronyms2 CSE module on MPC5777CThe Cryptographic Services Engine (CSE) is a peripheral module that implements the security functions described in the Secure Hardware Extension (SHE) Functional Specification Version 1.1.The CSE design includes a host interface with a set of memory mapped registers and a system bus interface. The host interface are used by the CPU to issue commands. The system bus interface allows the CSE to access system memory directly. Two dedicated blocks of system flash memory are used by the CSE for secure key storage.2.1 Chip-specific CSE informationThis chip has one instance of the CSE module. The module:•Executes the chip's secure boot process. See the System Boot details in the MPC5777C Reference Manual.•Exclusive access to the flash memory blocks mapped to the C55FMC_LOCK1 register, PASS_LOCK1_PGn registers, and TDRn_LOCK1 DCF client. See C55FMC_LOCK1 register bit mapping. The system MPU is automatically configured to prevent other bus masters frominterfering with CSE's access to the flash memory.2.2 FeaturesThe CSE has the following features:•Secure storage for cryptographic keys•AES-128 encryption and decryption•AES-128 CMAC authentication•True random number generation•Secure boot mode•System bus master interface2.3 Modes of operationThe CSE supports operation in Normal and Debug modes of operation. The use of the cryptographic keys stored by the CSE is controlled based on the activation of the CPU debug port and the successful completion of the secure boot process.The CSE has a low-power mode that disables the clock to all logic except the host interface. Register accesses are supported in this mode, but commands are not processed.2.4 Block diagramThe CSE design includes a command processor, host interface, system bus interface, local memory, AES logic, and True Random Number Generator (TRNG) as shown below.A host interface (via the peripheral bridge) with a set of memory mapped registers that are used by the CPU to issue commands. Furthermore, a system bus interface (via the crossbar interface) allows the CSE to directly access system memory. Here the crypto module behaves like any other master on the Crossbar switch (XBAR). Through the host interface, you can configure and control the CSE module, like putting the module into low power mode, enabling interrupts for finished command processing, or suspending command processing. A status and error register gives further system information. For a complete list of CSE commands see MPC5777C reference manual.Two dedicated blocks of system flash memory are used by the CSE for secure key and firmware storage. These blocks are not accessible by other masters from the system. Therefore, they are called secure flash. The command processing is done by a 32-bit CSE core with attached ROM and RAM running at system frequency. After system boot, the core comes out of reset and executes boot code from the module ROM. This code will load the firmware from the secure flash into the module RAM and start executing from there. This reduces the flash accesses by the crypto core on the Crossbar. The AES block is a slave to the crypto internal bus. It processes the encryption (plaintext → ciphertext) and decryption (ciphertext → plaintext) and offers AES CMAC authentication. This application note deals only with the authentication capabilities of the CSE.2 CSE module on MPC5777CFigure 1. CSE block diagram on MPC5777C3 AES-128 encryption and decryption overviewBlock ciphers like the AES algorithm, working with a defined granularity, are often 64 bits or 128 bits. The simplest way to encode data is to split the message in the cipher specific granularity. In this case, the cipher output depends only on the key and input value. The drawback of this cipher mode, which is called Electronic Code Book (ECB), is that the same input values will be decoded into the same output values. This gives attackers the opportunity to use statistical analysis (for example, in a normal text some letter combinations occur much more often than others).To overcome this issue other cipher modes were developed like the Cipher-block chaining (CBC), Cipher feedback (CFB), Output feedback (OFB) and Counter (CTR) mode.The CSE module supports only the ECB and the CBC mode which are described in the following sections.3.1 Electronic Codebook (ECB)Each block has no relationship with another block of the same message or information. The following figure shows the block diagram of the ECB mode.Figure 2. ECB block diagramThe following figure shows the drawback of the ECB mode. Taking the Freescale logo as an example it is still visible in the encoded form using this mode. It is obvious that this is not very secure.Figure 3. Encoding using ECB mode3.2 Cipher-block chaining (CBC)The Cipher-block (CBC) mode, invented in 1976, is one of the most important cipher modes. In this mode the output of the last encoding step is xor’ed with the input block of the actual encoding step. Because of this, an additional value for the first encoding step is necessary which is called initialization vector (IV). Using this method each cipher block depends on the plaintext blocks processed up to that point.3 AES-128 encryption and decryption overviewThe following figure shows the block diagram of the CBC mode.Figure 4. CBC block diagramThe following figure shows the encoding result of the Freescale logo using the CBC cipher mode. The difference from the ECB mode is self-evident. In many applications ECB mode may not be appropriate.Figure 5. Encoding using CBC mode3.3 CMAC (Cipher-based Message Authentication Code)A CMAC provides a method for authenticating messages and data. The CMAC algorithm accepts as input a secret key and an arbitrary-length message to be authenticated, and outputs a CMAC. The CMAC value protects both a message's data integrity as well as its authenticity, by allowing verifiers (who also possess the secret key) to detect any change in the message contentFigure 6. CMAC SchemeIf you want more information about CSE functional description and CSE commands, see MPC5777C reference manual.CRYPTO module in MCAL4.34 CRYPTO module in MCAL4.3The following figure shows the location of Crypto Driver module in the micro controller abstraction layer. It is below the Crypto Interface module and Crypto Service Manager module. It implements a generic interface for synchronous and asynchronous cryptographic primitives. It also supports key storage, key configuration, and key management for cryptographic services.To provide cryptographic functionalities an ECU needs to integrate one unique Crypto Service Manager module and one Crypto Interface. However, the Crypto interface can access several Crypto Drivers, each of them is configured according to the underlying Crypto Driver Object.Figure 7. AUTOSAR layered view with crypto moduleA Crypto Driver Object represents an instance of independent crypto hardware “device” (e.g. AES accelerator). There could be a channel for fast AES and CMAC calculations on a HSM for jobs with high priority, which ends on a native AES calculation service in the Crypto Driver. But it is also possible that a Crypto Driver Object is a piece of software, e.g. for RSA calculations where jobs are able to encrypt, decrypt, sign or verify. The Crypto Driver Object is the endpoint of a crypto channel.NOTECrypto have layers including Crypto Cryif and CSM, since CSM is alwaysa stub and only in order to avoid compiler error. Thejob_configuration_structure is responsible by CSM, so the job structurecannot generated by NXP CSM itself, as CSM is a stub in MCALperspective. Developers need to manually update the structure and passingit to Crypto_Process_Job. So if need more CSM package support andshould contact the third party(i.e vector DaVinci).CRYPTO module in MCAL4.3Figure 8 shows the relationship between different configuration items in EB:Cryptoprimitives ->CryptoDriverObject->CryIfChannel->CsmQueue->CsmJobs CryptokeyElement->CryptokeyType->Cryptokey->CryIfKey->CsmKeysCrypto Driver Object: A Crypto Driver implements one or more Crypto Driver Objects. The Crypto Driver Object can offer different crypto primitives in hardware or software. The Crypto Driver Objects of one Crypto Driver are independent of each other. There is only one workspace for each Crypto Driver Object (i.e. only one crypto primitive can be performed at the same time)CryptoKeyElement: Key elements are used to store data. This data can be key material or the IV needed for AES encryption. It can also be used to configure the behavior of the key management functions.CryptoKeyType: A key type consists of references to key elements. The key types are typically pre-configured by the vendor of the Crypto Driver.CryptoKey: A Key can be referenced by a job in the CSM. In the Crypto Driver, the key references a specific key type.CryptoPrimitive: A crypto primitive is an instance of a configured cryptographic algorithm realized in a Crypto Driver Object.Figure 8. Crypto configuration in EBCRYPTO module in MCAL4.3 CryIf: The crypto drivers are called by CryIf, the Crypto drivers access the underlying hardware and software objects to calculate results with their cryptographic primitives. The results are forwarded to CryIf.CsmJob: A job is an instance of a job’s configured in cryptographic primitive. An operation of a crypto primitive declares what part of the crypto primitive will be performed. There are three different operation modes:•START is a operation mode indicates a new request of a crypto primitive and will be cancel all previous request of the same job and preemptive•UPDATE mode indicates that the crypto primitive expects input data•FINISH mode indicates that after this part all data are fed completely and the crypto primitive can finalize the calculationThe priority of a job defines the importance of it. The higher the priority means more immediately the job is executed. The priority of a cryptographic job is part of the configuration.Figure 9. Cryif and CsmJobs in EBNOTEThe crypro driver does not have callback function in CryIf.c file, so itshould add SampleAppCrypto(job, result) intoCryIf_CallbackNotification(const Crypto_JobType* job, Std_ReturnTyperesult) function in CryIf.c file.CRYPTO module in MCAL4.3As show in the following figure, this sample configure three primitives, ENCRYPT, RNG(random number generated) and DECRYPT.Figure 10. CryptoPrimitive configuration in EBAs show in the following figure, A CryptoKeyElement having the CryptoKeyElementId set to 1 represents a key material and cannot be set be using the field CryptoKeyElementInitValue. All the other CryptoKeyElementIds can be set either using CryptoKeyElementSet function or the Tresos field CryptoKeyElementInitValue.Figure 11. CryptoKeyEelment configuration in EBAs show in the following figure, key elements and keys have to be configured for all primitives supported in this release. Containers CryptoKeyElements, CryptoKeyTypes and CryptoKeys should be activated or deactivated in Tresos in the same time. For a key it is mandatory to have a key type and configured key elements. The index of the different key elements from the different Crypto services are defined as in imported types table SWS_Csm_01022(in AUOTOSAR document Specification of Crypto Service Manager)A key has a state which is either 'valid' or 'invalid'. By default, all the keys are 'invalid' and have to be set to valid by using the function Crypto_KeySetValid. If a key is in the invalid state then the Crypto services which make use of the key returns CRYPTO_E_KEY_NOT_VALID value.Figure 12. CryptoKey configuration in EBCRYPTO loading key and processing primitive Because crypto driver not include CSM layer, so the Crypto_JobType structure should be initialized manually in the code.Figure 13. Csm in EB5 CRYPTO loading key and processing primitiveTo process a primitive (random number generation, MAC generation or verification, AESencrypt/decrypt), the following sequence should be followed:1.If keys are needed, the containers CryptoKeyElements, CryptoKeyTypes, CryptoKeys should beenabled2.Crypto_KeyElementSet(65536, CryptoKeyElementId_0, aes_test01_key, 16) meaning a keymaterial corresponding to key 65536 and having the size 16 bytes is configured3.Call the API function Crypto_KeySetValid(65536) to enable key 655364.Call the API function Crypto_ProcessJob() to process job, it process three jobs(randomgenerated, encryption and decryption) in this sample codeFigure 14. Process job in sample code6 ReferencesCall API function StringCompare ((uint8_t*)ucPlainText, ucDecText, 16) to verify the encryption and decryption functionality.Figure 15. Compare the ucPlainText and ucDecText6 References•MPC5777C Reference Manual (Document ID: MPC5777CPRM)•Specification of Crypto Service Manager(Document link)•Specification of Crypto Driver(Document link)•AUTOSAR_MCAL_CRYPTO_IM•AUTOSAR_MCAL_CRYPTO_UMDocument Number: AN 13061 Rev. 0 12/2020 How to Reach Us: Home Page: Web Support: /supportInformation in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. 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1. LPCXpresso-CN-LPC1114处理器内核Cortex-M0/M0+内核,运行速度高达50MHz带有SWD 调试功能、支持JTAG 调试功能(仅LPC11U00 系列)支持边界扫描(仅LPC11U00 系列)支持非屏蔽(NMI)中断(仅LPC11U00 和LPC1100XL 系列)内置嵌套向量中断控制器(NVIC)系统节拍定时器片内存储器最高配合256KB 片内Flash 程序存储器支持256 字节页擦除(仅LPC1100XL/LPC11U3X/LPC11U6X 系列)最高配置36KB 片内SRAM;最高配置4KB 片内EEPROM(仅LPC11E00 系列)(仅LPC11E00 和LPC11U00 系列)可通过片内引导装载程序软件来实现在系统编程(ISP)和在应用编程(IAP)可选择通过CAN(仅LPC11C00 系列)、USB Device(仅LPC11U00 系列)或UART 接口进行Flash ISP 编程串行接口包括:USB 2.0 全速接口,集成片上PHY(仅LPC11U00 系列)CAN 控制器(LPC11C12/C14/C22/C24 支持),内部ROM 集成供CAN 和CANOpen 标准使用的初始化和通信的API 函数,用户可直接调用;兼容CAN2.0A/B,传输速率高达1Mbit/s;支持32 个消息对象,且每个消息对象有自己的掩码标识;提供可屏蔽中断、可编程FIFO 模式集成片上高速CAN 收发器(仅LPC11C22/C24 支持)UART,可产生小数波特率,具有调制解调器、内部FIFO,支持RS-485/EIA-485 标准,支持ISO7816-3 智能卡接口及IrDA(仅LPC11U00 系列)SSP 控制器,带FIFO 和多协议功能I2C 总线接口,完全支持I2C 总线规范和快速模式,数据速率为1Mbit/s,具有多个地址识别功能和监控模式数字外设:多达80 个通用I/O(GPIO)引脚,带可配置的上拉/下拉电阻,LPC11U00 系列还可配置为中继模式和开漏模式每个GPIO 口均可配作边沿或电平中断(LPC11U00 可选择所有GPIO 中的8 个,每个GPIO中断占用独立NVIC 通道)1 个引脚(P0.7)支持20mA 的高驱动电流I2C 总线引脚在FM+模式下可支持20mA 的灌电流4 个通用定时器/计数器,共有4 路捕获输入和13 路匹配输出2 个状态可配置定时器SCT(仅LPC11U6x 系列支持)可编程的看门狗定时器(WDT)(LPC11U00 为带窗看门狗WWDT)4×40 段LCD 驱动(仅LPC11D14 支持)模拟外设:8 通道10 位ADC1 个多达12 通道输入的12 位ADC,支持多个内部和外部触发输入,支持2 个独立转换序列,最大采样率为2MBit/s(仅LPC11U6x 系列支持)内置温度传感器(仅LPC11U6x/LPC11A00 系列支持)时钟产生单元:12MHz 内部RC 振荡器可调节到+1%精度,并可将其选择为系统时钟PLL 允许CPU 在最大CPU 速率下操作,而无需高频晶振,可从主振荡器、内部RC 振荡器运行第二个专用PLL 用于USB 接口(仅LPC11U00 系列)时钟输出功能可以反映主振荡器时钟、IRC 时钟、CPU 时钟和看门狗时钟片内32KHz 的振荡器(仅LPC11U6x 系列支持)电源与功率控制:具有三种低功耗模式:睡眠模式、深度睡眠模式和深度掉电模式(LPC11E00/LPC11U00 系列为四种,增加掉电模式)集成了PMU(电源管理单元),可在睡眠、深度睡眠、掉电(仅LPC11E00/LPC11U00 系列)和深度掉电模式中极大限度地减少功耗片内固化功耗管理文件,通过简单调用就能降低功耗(仅LPC1100L、LPC1100XL、LPC11E00 和LPC11U00 系列)13 个拥有专用中断的GPIO 可将CPU 从深度睡眠模式中唤醒(LPC11E00 系列可通过复位、WDT 中断、BOD 中断唤醒,LPC11U00 系列还可通过USB 活动唤醒)上电复位(POR)掉电检测,具有4 个独立的阀值,用于中断和强制复位3.3V 单电源供电(1.8V~3.6V)封装:采用SO20、TSSOP20、TSSOP28、DIP28、HQFN33 (5 mm x 5 mm)、HQFN33 (7 mm x 7 mm)、LQFP100、LQFP64、LQFP48、PLCC44、HVQFN24、HVQFN32、HVQFN33、TFBGA 或WL-CSP(晶片级)封装参阅/products/microcontrollers/cortex_m0_m0/series/LPC1100XL.html/zh-hans/content/device/lpc11xx2. LPCXpresso-CN-LPC1227处理器内核ARM Cortex-M0 内核,运行速度高达45MHz内置嵌套向量中断控制器(NVIC)SWD 调试接口系统节拍定时器片内存储器高达8kB SRAM高达128kB 片内Flash 存储器可通过片内引导装载程序软件实现在系统编程(ISP)和在应用编程(IAP)功能数字外设21 通道Micro DMA 控制器硬件CRC 计算及校验模块两个带有小数波特率发生器和内部FIFO 的UART。
© 2018 NXP B.V.MIMXRT1020 EVK Board Hardware User’sGuide1.IntroductionThis Hardware User’s Guide for the MIMXRT 1020Evaluation Kit (EVK) is based on the NXP Semiconductor i.MX RT1020 Processor. This board is fully supported by NXP Semiconductor. The guide includes system setup and debugging, and provides detailed information on overall design and usage of the EVK board from a hardware systems perspective.1.1. Board overviewThis EVK board is a platform designed to showcase the most commonly used features of the i.MX RT1020 Processor in a small, low cost package. The MIMXRT1020 EVK board is an entry level development board, which gives the developer the option of becoming familiar with the processor before investing a large amount or resources in more specific designs.NXP Semiconductors Document Number: MIMXRT1020EVKHUGUser's GuideRev. 0 , 05/2018Contents1.Introduction ........................................................................ 11.1.Board overview ....................................................... 11.2.MIMXRT1020 EVK contents ................................. 21.3.MIMXRT1020 EVK Board revision history ........... 32.Specifications ..................................................................... 32.1.i.MX RT1020 processor .......................................... 52.2.Boot Mode configurations ....................................... 52.3.Power tree ............................................................... 62.4.SDRAM memory .................................................... 92.5.SD Card slot ............................................................ 92.6.QSPI flash ............................................................... 92.7.Ethernet connector .................................................. B PHY connector ............................................. 102.9.Audio input / output connector .............................. 102.10.OpenSDA circuit (DAP-Link) ............................... 102.11.JTAG connector .................................................... 102.12.Arduino expansion port ......................................... er interface LED indicator ................................ 133.PCB information .............................................................. 134.EVK design files .............................................................. 135.Contents of the Evaluation Kit ......................................... 146.Revision history (14)IntroductionFeatures of the MIMXRT1020 EVK board are shown in Table 11.2. MIMXRT1020 EVK contentsThe MIMXRT1020 EVK contains the following items: •MIMXRT1020 EVK Board•USB Cable (Micro B)Specifications 1.3. MIMXRT1020 EVK Board revision history•Rev A: Prototype.2. SpecificationsThis chapter provides detailed information about the electrical design and practical considerations of the EVK Board, and is organized to discuss each block in the following block diagram of the EVK board.( Figure 1)Figure 1. Block diagramThe overview of the MIMXRT1020 EVK Board is shown in Figure 1 & Figure 2.SpecificationsFigure 2. Overview of the MIMXRT1020 EVK Board (Front side)Figure 3. Overview of the MIMXRT1020 EVK Board (Back side)Specifications 2.1. i.MX RT1020 processorThe i.MX RT1020 is a new processor family featuring NXP's advanced implementation of the Arm® Cortex®-M7 Core. It provides high CPU performance and best real-time response. The i.MX RT1020 provides various memory interfaces, including SDRAM, Raw NAND FLASH, NOR FLASH,SD/eMMC, Quad SPI, HyperBus and a wide range of other interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS. Same as other i.MX processors, i.MX RT1020 also has rich audio features, including SPDIF and I2S audio interface.The i.MX RT1020 applications processor can be used in areas such as industrial HMI, IoT, motor control and home appliances. The architecture's flexibility enables it to be used in a wide variety of other general embedded applications too. The i.MX processor provides all interfaces necessary to connectp eripherals such as WLAN, Bluetooth™, GPS.The more detail information about i.MX RT1020 can be found in the Datasheet and Reference Manual2.2. Boot Mode configurationsThe device has four boot modes (one is reserved for NXP’s use). The boot mode is selected based on the binary value stored in the internal BOOT_MODE register. Switch (SW8-3 & SW8-4) is used to select the boot mode on the MIMXRT1020 EVK Board.Typically, the internal boot is selected for normal boot, which is configured by external BOOT_CFG GPIOs. The following Table 3 shows the typical Boot Mode and Boot Device settings.NOTEFor more information about boot mode configuration, see the System Boot chapter of theMIMXRT1020 Reference Manual. (waiting for update)For more information about MIMXRT1020 EVK boot device selection and configuration, see the main board schematic. (waiting for update)Specifications2.3. Power treeA DC 5 V external power supply is used to supply the MIMXRT1020 EVK Board at J2, and a slide switch SW1 is used to turn the Power ON/OFF. J23 and J9 also can be used to supply the EVK Board. Different power supply need to configure different Jumper setting of J1. Table 4 shows the details:NOTEFor some computers’ USB, it cannot support 500ma before establishingcommunication. In this case, it is recommended to replace the computer oruse the power adapter(J2) to power the EVK Board.The power tree is shown in Figure 4SpecificationsFigure 4. Power TreeThe power control logic of the MIMXRT1020 EVK board is shown in the Figure 5: •It will power up SNVS, and then PMIC_REQ_ON will be switched on to enable external DC/DC to power up other power domains.•ON/OFF button is used to switch ON/OFF PMIC_REQ_ON to control power modes.•RESET button and WDOG output are used to reset the system power.SpecificationsFigure 5. Power Control Diagram The power rails on the board are shown in Table 5.Specifications2.4. SDRAM memoryOne 256 Mb, 166MHz SDRAM (MT48LC16M16A2P) is used on the EVK Board.2.5. SD Card slotThere is a SD card slot(J15) on the MIMXRT1020 EVK Board. J15 is the Micro SD slot for USDHC1 interface. If the developer wants to boot from the SD Card, the boot device switch (SW8) settings should be: OFF, ON, ON, OFF, as shown in Table 3.2.6. QSPI flashA 64 Mbit QSPI Flash is used on the MIMXRT1020 EVK Board. If the developer wants to boot from the QSPI Flash, the boot device switch(SW8) settings should be: OFF, OFF, ON, OFF, as shown in Table 3.2.7. Ethernet connectorThere is one Ethernet Mac controller in the MIMXRT1020 processor. The Ethernet subsystem of the MIMXRT1020 EVK Board is provided by the KSZ8081RNB 10/100M Ethernet Transceiver (U11) and a RJ45 (J14) with integrated Magnetic.Figure 6. Ethernet Connector RJ45Specifications2.8. USB PHY connectorThe MIMXRT1020 contains a integrated USB 2.0 PHYs capable of connecting to USB host/device systems at the USB low-speed (LS) rate of 1.5 Mbits/s, full-speed (FS) rate of 12 Mbits/s or at the USB 2.0 high-speed (HS) rate of 480 Mbits/s.2.9. Audio input / output connectorThe Audio CODEC used on the MIMXRT1020 EVK Board is Wolfson’s Low Power, high quality Stereo Codec, WM8960.The MIMXRT1020 EVK Board include one headphone interface (J11), one onboard MIC (P1), two speaker interfaces (J12, J13). J11 is a 3.5 mm audio stereo headphone jack, which supports jack detect.2.10. OpenSDA circuit (DAP-Link)The OpenSDA circuit (CMSIS–DAP) is an open-standard serial and debug adapter. It bridges serial and debug communications between a USB host and an embedded target processor.CMSIS-DAP features a mass storage device (MSD) bootloader, which provides a quick and easy mechanism for loading different CMSIS-DAP Applications such as flash programmers, run-control debug interfaces, serial-to-USB converters, and more. Two or more CMSIS-DAP applications can run simultaneously. For example, run-control debug application and serial-to-USB converter runs in parallel to provide a virtual COM communication interface while allowing code debugging via CMSIS-DAP with just single USB connection.For the MIMXRT1020 EVK Board, J23 is the connector between the USB host and the target processor. Jumper to serial downloader mode to use stable DAP-Link debugger function. If developer wants to make OpenSDA going to the bootloader mode, and press SW5 when power on. Meanwhile, the OpenSDA supports drag/drop feature for U-Disk. First, use the seral downloader mode and drag/drop the image file to U-Disk. Then select QSPI Flash as boot device and reset the Board, the image will run.2.11. JTAG connectorJ16 is a standard 20-pin/2.54 mm Box Header Connector for JTAG. The pin definitions are shown in Figure 7. Support SWD by default.SpecificationsFigure 7. JTAG pin definitions2.12. Arduino expansion portJ17 – J20 (unpopulated) is defined as Arduino Interface. The pin definitions of Arduino Interface are shown in Table 6.Specifications2.12.1. Power switchSW1 is a slide switch to control the power of the MIMXRT1020 EVK Board when the power supply is from J2. The function of this switch is listed below:•Sliding the switch to the ON position connects the 5 V power supply to the Evaluation board main power system.•Sliding the switch to OFF position immediately removes all power from the board.2.12.2. ON/OFF buttonSW2 is the ON/OFF button for MIMXRT1020 EVK Board. A short pressing in OFF mode causes the internal power management state machine to change state to ON. In ON mode, a short pressing generates an interrupt (intended to be a software-controllable(power-down). An approximate 5 seconds or more pressing causes a forced OFF. Both boot mode inputs can be disconnected.2.12.3. Reset buttonThere are two Reset Button on the EVK Board. SW5 is the Power Reset Button. Pressing the SW5 in the Power On state will force to reset the system power except SNVS domain. The Processor will be immediately turn off and reinitiate a boot cycle from the Processor Power Off state. SW3 is POR Reset Button.EVK design files 2.12.4. USER buttonSW4 is the USER Button(GPIO5-00) for developers using. Pressing can produce changes in high and low levels.2.13. User interface LED indicatorThere are four LED status indicators located on the EVK Board. The functions of these LEDs include: •Main Power Supply(D3)Green: DC 5V main supply is normal.Red: J2 input voltage is over 5.6V.Off: the board is not powered.•Reset RED LED(D15)•OpenSDA LED(D16)•USER LED(D5)3. PCB informationThe MIMXRT1020 EVK Board is made using standard 2-layer technology. The material used was FR-4. The PCB stack-up information is shown in Table 7.4. EVK design filesThe schematics, layout files, and gerber files (including Silkscreen) can be downloaded from/MIMXRT1020-EVK(waiting for update).Revision history5. Contents of the Evaluation KitNOTEPower adaptor, Micro SD Card are not standard parts of the Evaluation Kit.6. Revision historyTable 9 summarizes the changes made to this document since the initial release.Document Number: MIMXRT1020EVKHUGRev. 0 05/2018How to Reach Us: Home Page: Web Support: /supportInformation in this document is provided solely to enable system and softwareimplementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein.NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequenti al or incidental damages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals”, must be validated for each customer application by customer’s technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: /SalesTermsandConditions . While NXP has implemented advanced security features, all products may be subject to unidentified vulnerabilities. Customers are responsible for the design and operation of their applications and products to reduce the effect of these vulnerabilities oncustomer’s applications and products, and NXP accepts no liability for any vulne rability that is discovered. Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, , Freescale, the Freescale logo, and Kinetis, are trademarks of NXP B.V. All other product or service names are the property of their respective owners. Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. © 2018 NXP B.V.。
NXP半导体文档编号:AN12170应用笔记Rev.0,2018年4月i.MXRT1050产品使用寿命估算原文链接:https:///docs/en/application-note/AN12170.pdf1.引言本文档根据认证过程中使用的标准介绍了i.MXRT1050应用处理器产品的使用寿命估算方法。
这里描述的产品使用寿命是估算的,并不代表处理器产品的实际保证使用寿命。
i.MX RT系列有许多处理器产品,它们支持高性能的运算处理和多媒体能力,并提供不同的认证资质等级。
不同认证资质等级的i.MX RT1050产品有着不同的最大目标运行频率和最高支持结温。
本文为您提供了目标运行频率和支持结温如何影响不同认证资质等级的i.MX RT1050产品使用寿命的解释指导。
内容1.引言 (1)2.设备认证资质等级及可用开机时间 (3)2.1.商业等级资质 (3)2.2.工业等级资质 (4)3.结合用例 (6)©2018NXP B.V.引言i.MXRT1050产品使用寿命估计,应用说明,Rev.0,04/20182NXP半导体每个支持的认证资质级别(商业级和工业级)定义了处理器在给定的一组工作条件下若干可用的开机时间(PoH)。
工作条件如:•应用(商业级和工业级)的目标频率—目标频率由处理器内核架构的输入电压(VDD_SOC_IN)决定。
—使用片上DCDC供电或片上DCDC旁路模式。
–当使用DCDC旁路模式时,目标电压不应设置为数据手册中指定的最小值。
所有电源管理IC都有允许的公差,因此目标电压必须设置为高于最小指定电压,以考虑PMIC的公差。
本文计算中假定的公差为+25mV。
–片上DCDC供电模式使用片上DCDC模块为i.MX RT系列产品的内核逻辑提供电源。
该DCDC模块具有良好的特性,可以输出精确的最小指定电压。
使用片上DCDC供电模式,可以实现更长的开机时间。
•运行时间与待机时间的百分比—运行状态意味着处理器正处于有效运行模式。
恩智浦半导体文档编号:AN12217 应用笔记第0版,2018年8月S32K1xx ADC 指南、规格和配置作者:恩智浦半导体1. 简介NXP S32K1xx 汽车微控制器具有 12 位逐次逼近模数转换器(SAR ADC),可用于模拟输入信号的采集和数字化。
本应用笔记提供了有关以下基本主题的信息,便于从ADC模块的使用中获得最大收益:-理解 ADC 常用术语、误差来源和规格。
-提高测量精度的最佳做法。
-S32K1xx 系列的常见触发配置示例。
目录作者:恩智浦半导体 (1)1. 简介 (1)2. ADC 概念、误差源和规格 (2)2.1. ADC 基本概念 (2)2.2. ADC测量中的误差来源 (3)2.3. S32K1xx ADC 规格 (5)3. 提高准确性的最佳措施 (8)4. ADC 触发模式示例 (10)4.1. 软件触发 (11)4.2. PDB 触发器 (11)4.3. 背靠背模式下的 PDB 触发器 (13)4.4. TRGMUX 触发器 (14)5. 参考资料 (16)附录A. 示例代码:ADC 软件触发 (17)附录B. 示例代码:带有 PDB 触发器的 ADC (19)附录 C. 示例代码:带有 PDB 和背靠背触发器的 ADC .. 21S32K1xx ADC 指南、规格和配置,第0版,2018年8月2恩智浦半导体2. ADC 概念、误差源和规格本节解释了用于表征 ADC 的概念和术语以及潜在的误差源,并提供了S32K1xx 系列数据表中的规范参数。
2.1. ADC 基本概念分辨率:ADC 数字输出中代表模拟输入信号的位数。
对于 S32K1xx 系列,分辨率可配置为 8、10 或 12 位。
参考电压:ADC 需要一个参考电压,用于与模拟输入进行逐次近似比较,以产生数字输出。
数字输出是模拟输入相对于该参考电压的比率。
VREF = VREFH – VREFL 其中:VREFH = 高参考电压 VREFL = 低参考电压ADC 输出公式:ADC 的转换公式用于计算特定模拟输入电压对应的数字输出。
搜集了些半导体厂商的LOGO,让大家认识下。
从事电子元器件这行应该知道业内一些牛逼的企业。
就像广告人知道哪些是 4A广告公司,会计师知道4大一样!本文就介绍半导体行业最牛逼的 25家企业。
很多小日本的企业。
不得不承认人家在技术上很牛逼!1.英特尔,营收额313.59亿美元英特尔公司(美国是全球最大的半导体芯片制造商,它成立于1968年,具有44 年产品创新和市场领导的历史。
1971年,英特尔推出了全球第一个微处理器。
微处理器所带来的计算机和互联网革命,改变了整个世界。
2.三星营收额192.07亿美元三星电子-主要业务为消费型电子、DRAM与NAND Flash,微控制器和微处理器、无线通信芯片与晶圆代工,美国《财富》杂志2011年世界500强行列中排名第22位集团旗下的旗舰公司。
2009年营业额约为99兆7000亿韩元。
3.德州仪器,营收额128.32亿美元德州仪器(英语:Texas Instruments简称:Tl ,是世界上最大的模拟技术部件制造商,全球领先的半导体跨国公司,以开发、制造、销售半导体和计算机技术闻名于世主要从事创新型数字信号处理与模拟电路方面的研究、制造和销售。
除半导体业务外,还提供包括传感与控制、教育产品和数字光源处理解决方案。
德州仪器(TI 总部位于美国德克萨斯州的达拉斯,并在25多个国家设有制造、设计或销售机构。
4.东芝,营收额101.66亿美元东芝公司(Toshiba Corporation是日本最大的半导体制造商,亦是第二大综合电机制造商,隶属于三井集团旗下。
公司创立于1875年7月,原名东京芝浦电气株式会社,1939年由东京电气株式会社和芝浦制作所合并而成,业务领域包括数码产品、电子元器件、社会基础设备、家电等。
20世纪80年代以来,东芝从一个以家用电器、重型电机为主体的企业,转变为包括通讯、电子在内的综合电子电器企业。
进入90年代,东芝在数字技术、移动通 信技术和网络技术等领域取得了飞速发 展,成功从家电行业的巨人转变为IT 行业的先锋。
UM11515Component library – getting started user manualRev. 1 — 2 November 2020User manualComponent library – getting started user manualComponent library – getting started user manual 1OverviewThe component library is a platform agnostic development model designed to work withany general and custom SDKs and hardware. The component library operates as aservice utility to application development environments by providing the essence of themodule specialties. The utilities are platform agnostic with respect to I/O and MCUs andspecialized in modular approach. The library includes various service utilities such filters,generic sensor drivers for specific sensors, tilt/angle calculation, eCompass, MachineLearning (ML), sensor fusion and pedometers. The distribution model is through sourcecode or library.2Downloading component libraryDownload the component library release package from component-lib download page on. To understand the component library release package structure and supportedcomponents, follow these steps:1.Open the component library download page.2.Unzip the component library release zip package.3.The unzipped package directory structure is shown in Figure 2.•docs: Folder containing component documentation•example: Folder containing example project•src: Folder containing component source filesComponent library – getting started user manualFigure 2. Package directory structure3Running component library example projectsThis section provides prerequisite steps for running example projects provided as part ofthe component library release package.3.1Running example projects for MCUXpresso SDK1.Open the NXP MCUXpresso IDE toolchain download page and download latestversion.2.Install the MCUXpresso IDE tool chain on your windows PC. MCUXpresso IDE isrequired to be able to build and run the example projects for chosen MCU.3.Connect the NXP sensor demonstration kit (including sensor shield board with thechosen MCU) to the PC via the USB cable between the OpenSDA USB port on theboard and the USB connector on the PC.4.Open the NXP MCUXpresso SDK builder page: https:///en/welcome and generate/download the SDK package for chosen board, for exampleFRDM-K64F, FRDM-K22F, FRDM-KL25Z.5.Install the downloaded MCUXpresso SDK package into MCUXpresso IDE. Simplydrag and drop the zipped SDK package to the “Installed SDKs” view. The IDE installsthe SDK package.6.Import the component library example projects for MCUXpresso SDK available in therelease package under “example” folder to open the project into MCUXpresso IDE.7.Build the imported example project using MCUXpresso IDE and load the firmware tothe connected sensor demonstration kit.8.Install any serial terminal application for windows, for example RealTerm or TeraTerm or Putty. The output of example project can be viewed on a serial terminal.9.Open a serial terminal with the following settings:•115200 baud rate•8 data bits•No parity•One stop bit•No flow control10.Run the program on the sensor demonstration board by clicking “Run” option on theMCUXpresso IDE.11.When the example runs successfully, you can see the output printed to the terminal.Component library – getting started user manual 4Legal information4.1 DefinitionsDraft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may resultin modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information.4.2 DisclaimersLimited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does notgive any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liabilityfor the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makesno representation or warranty that such applications will be suitablefor the specified use without further testing or modification. Customersare responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated withtheir applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is basedon any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.Security — While NXP Semiconductors has implemented advanced security features, all products may be subject to unidentified vulnerabilities. Customers are responsible for the design and operation of their applications and products to reduce the effect of these vulnerabilities on customer’s applications and products, and NXP Semiconductors accepts no liability for any vulnerability that is discovered. Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and products.4.3 TrademarksNotice: All referenced brands, product names, service names and trademarks are the property of their respective owners.NXP — wordmark and logo are trademarks of NXP B.V.Component library – getting started user manualFiguresFig. ponent library components ........................3Fig. 2.Package directory structure (4)Component library – getting started user manualPlease be aware that important notices concerning this document and the product(s)described herein, have been included in section 'Legal information'.Contents1Overview ..............................................................32Downloading component library .......................33Running component library exampleprojects ................................................................43.1Running example projects for MCUXpressoSDK (44)Legal information (5)。
NXP SEMICONDUCTORS CORPORATE OVERVIEWDECEMBER 2015ACCELERATING TECHNOLOGY TRENDSDRIVE OPPORTUNITIES FOR NXPSecure Connections for a Smarter WorldEverythingConnected1B+ additionalconsumers online, 30B+ connected devicesEverythingSmart40B+ devices with intelligence shippedin 2020,EverythingSecurePotential savings toeconomy up tohalf trillion dollarsProcessingConnectivity Security#1Communications Processors #1RF Power Transistors#1Automotive Radar#1Automotive Safety2#2MCUs#1SECUREIDENTIFICATION#1AUTOMOTIVE#1RF POWERTRANSISTORS#1COMMUNICATIONSPROCESSORS#1SMALL SIGNALDISCRETES#1BROAD-BASEDMCUs1#1Secure Identification#1Car Entertainment#1In-Vehicle Networking#1Secure Car Access#1Smart Card MCUs#1Small Signal DiscretesEXPANDED SOLUTIONS FOR CUSTOMERSA NEW POSITION OF STRENGTH✓50+ year history ✓17,300 employees ✓$4.59b in revenue ✓$839m in R&D✓50+ year history✓28,000 employees✓$6.03b in revenue✓$723m in R&D>$10BIN ANNUALREVENUE11,000+ENGINEERS~45,000EMPLOYEES9,000+PATENTFAMILIES35+COUNTRIES4th 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SOLUTIONSMCUMPUANALOGSENSORSRFNFCSTANDARDPRODUCTSMCUMPUSENSORSANALOGSTANDARDPRODUCTSMCUMPUANALOGSENSORSNFCSTANDARDPRODUCTSMCUMPUANALOGSENSORSRFNFCSTANDARDPRODUCTSSMARTINFRASTRUCTUREMPUAnalogRFSTANDARDPRODUCTSNXP UNIQUELY POSITIONED TO DELIVER SECURE SMART CONNECTED SOLUTIONSSecurity Technology Smart Connected ApplicationIdentificationDevice IdentificationCertification ComplianceCryptographyAccelerationNetwork SecurityNFC RFIDSecure Boot Secure KeysSecure Memory Secure UpdateTrusted Execution Environments Unique Chip IdentitySMARTHOMEWEARABLESSMARTINDUSTRYSMARTINFRASTRUCTURESMARTHEALTHCARESecurity Expertise E-Passport Mobile Transactions BankingIOT NEEDS A SECURE AND DYNAMIC NETWORK Trust Architecture Trust Architecture Trust ArchitectureSecureConnectionsSecureConnectionsApplication/ActionBig DataMPUsAnalogMPUsNFCSensorsConnectivityMCUsRFIDAnalogEdge Nodes Gateway CloudMPUsNFCSensorsConnectivityMCUsAnalogRFTHE ONLY SUPPLIER TO PROVIDE COMPLETE IOT SOLUTIONSDSPs, MCUs & CPUsSuite of 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