AD5282BRU50中文资料

DISCRETE SEMICONDUCTORS DATA SHEETBLT50UHF power transistorProduct specification April 1991UHF power transistor BLT50FEATURES•SMD encapsulation•Gold metallization ensures excellent reliability. DESCRIPTIONNPN silicon planar epitaxial transistor encapsulated in a SOT223 surface mounted envelope and designed primarily for use in hand-held radio equipment in the 470 MHz communications band.PINNING - SOT223PIN DESCRIPTION1emitter2base3emitter4collectorQUICK REFERENCE DATARF performance at T s≤ 60°C in a common emitter class-B test circuit (note 1).Note1.T s = temperature at soldering point of collector tab.PIN CONFIGURATIONMODE OF OPERATION f (MHz)V CE (V)P L (W)G p (dB)ηc (%) c.w. narrow band4707.5 1.2>10>55handbook, halfpageecbMBB012Fig.1 Simplified outline and symbol.age4123MSB002 - 1Top viewUHF power transistorBLT50LIMITING VALUESIn accordance with the Absolute Maximum System (IEC 134).Note1.T s = temperature at soldering point of collector tab.THERMAL RESISTANCESYMBOL PARAMETERCONDITIONS MIN.MAX.UNIT V CBO collector-base voltage open emitter −20V V CEO collector-emitter voltage open base −10V V EBO emitter-base voltage open collector −3V I C , I C(AV)collector current DC or average value −500mA I CM collector current peak value f >1 MHz − 1.5A P tottotal power dissipationf >1 MHz;T s =103°C (note 1)−2WT stg storage temperature range −65150°C T j operating junction temperature−175°CSYMBOLPARAMETERCONDITIONSMAX.UNIT R th j-s(DC)from junction to soldering pointP tot = 2 W; T s =103°C36K/WFig.2 DC SOAR.T s =103°C.handbook, halfpage102MEA21710V CE (V)I C (A)10.110.50.2UHF power transistorBLT50CHARACTERISTICS T j = 25°C.SYMBOL PARAMETERCONDITIONS MIN.TYP .MAX.UNIT V (BR)CBO collector-base breakdown voltage open emitter;I C = 5 mA 20−−V V (BR)CEO collector-emitter breakdown voltage open base;I C = 10 mA 10−−V V (BR)EBO emitter-base breakdown voltage open collector;I E = 1 mA 3−−V I CES collector-emitter leakage current V BE = 0;V CE = 10 V −−250µAh FE DC current gainV CE = 5 V;I C = 300 mA 25−−E SBRsecond breakdown energyL = 25 mH;R BE = 10Ω;f = 50 Hz 0.55−−mJC ccollector capacitance V CB = 7.5 V;I E = I e = 0;f = 1 MHz − 4.76pFC refeedback capacitance V CE = 7.5 V;I C = 0;f = 1 MHz− 2.9 4.5pFFig.3Collector capacitance as a function of collector-base voltage, typical values.I E =i e =0; f =1 MHz.handbook, halfpage 08101002MEA218246V CB (V)C c (pF)468UHF power transistorBLT50APPLICATION INFORMATIONRF performance at T s ≤ 60°C in a common emitter class-B test circuit.MODE OF OPERATIONf (MHz)V CE (V)P L (W)G p (dB)ηc (%)c.w. narrow band4707.5 1.2>10typ. 11.2>55typ. 65Fig.4Gain and efficiency as functions of load power, typical values.V CE = 7.5 V;f = 470 MHz.handbook, halfpage1612408MEA2190.61.01.42.21.8G p (dB)G pP L (W)806040100ηη(%)Fig.5Load power as a function of drive power,typical values.V CE = 7.5 V;f = 470 MHz.handbook, halfpage100P D (mW)P L (W)200201MEA220Ruggedness in class-B operationThe BLT50 is capable of withstanding a load mismatch corresponding to VSWR = 50:1 through all phases at rated output power, up to a supply voltage of 9 V,f = 470 MHz and T s ≤ 60°C, where T s is the temperature at the soldering point of the collector tab.UHF power transistor BLT50List of components (see test circuit)Notes1.American Technical Ceramics (ATC) capacitor, type 100B or other capacitor of the same quality.2.The striplines are mounted on a double copper-clad printed circuit board, with PTFE fibre-glass dielectric (εr = 2.2);thickness 1⁄16inch.COMPONENT DESCRIPTIONVALUE DIMENSIONSCATALOGUE NO.C1film dielectric trimmer 1.4 to 5.5 pF 222280909004C2film dielectric trimmer 1.4 to 5.5 pF 222280909001C3film dielectric trimmer 2 to 9 pF 222280909002C4film dielectric trimmer2 to 9 pF 222280909005C5multilayer ceramic chip capacitor (note 1)100 pF C6multilayer ceramic chip capacitor (note 1)1 nF C763 V electrolytic capacitor 2.2µF L1stripline (note 2)50Ω54 mm ×4.7 mm L2 5 turns enamelled 0.4 mm copper wireint. dia. 3 mmL3, L7grade 3B1 Ferroxcube wideband RF choke431202036640L4stripline (note 2)50Ω36 mm ×4.7 mm L5 1 turn enamelled 1.4 mm copper wire 5 nHint. dia. 4 mm L6 3 turns enamelled 0.4 mm copper wireint. dia. 3 mmR1, R20.25 W metal film resistor10Ω,5%Fig.6 Class-B test circuit at f = 470 MHz.handbook, full pagewidthMBA57650 Ω50 ΩC7C6C5R2L7L6C3C4L5L4TUTL2L3R1C2C1L1+V CCUHF power transistor BLT50Fig.7 Component layout for 470 MHz class-B test circuit.The circuit and components are situated on one side of a copper-clad PTFE fibre-glass board; the other side is unetched and serves as a ground plane. Earth connections from the component side to the ground plane are made by means of fixing screws, hollow rivets and copper foil straps, as shown.handbook, full pagewidthMBA575L7C7C6R2L6L5C3C4L4L2C5R1L3L1C1C2V CChandbook, full pagewidthMBA574strapstrapstrapstraprivets (14x)mounting screws (8x)140 mm80 mmUHF power transistor BLT50Fig.8Input impedance (series components) as a function of frequency, typical values.Class-B operation;V CE = 7.5 V;P L = 1.2 W.handbook, halfpage350450Z i (Ω)x ir i55065043102MEA221f (MHz)Fig.9Load impedance (series components) as a function of frequency, typical values.Class-B operation;V CE = 7.5 V;P L = 1.2 W.handbook, halfpage350450550X LR LZ L (Ω)65020155010MEA222f (MHz)Fig.10 Definition of transistor impedance.handbook, halfpageMBA451Z iZ LFig.11Power gain as a function of frequency,typical values.Class-B operation;V CE = 7.5 V;P L = 1.2 W.handbook, halfpage350450550G p (dB)6501612408MEA223f (MHz)UHF power transistorBLT50PACKAGE OUTLINEUNIT A 1b p c D E e 1H E L p Q y w v REFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IECJEDECEIAJmm0.100.011.81.50.800.60b 13.12.90.320.226.76.33.73.32.3e 4.67.36.71.10.70.950.850.10.10.2DIMENSIONS (mm are the original dimensions) SOT22396-11-1197-02-28w M b pD b 1e 1eAA 1L pQdetail XH EE v M AA B Bcy02 4 mmscaleA X1324Plastic surface mounted package; collector pad for good heat transfer; 4 leadsSOT223UHF power transistor BLT50DEFINITIONSData Sheet StatusObjective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.Limiting valuesLimiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.Application informationWhere application information is given, it is advisory and does not form part of the specification.LIFE SUPPORT APPLICATIONSThese products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.。

PRELIMINARY TECHNICAL DATA Information furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700World Wide Web Site: Fax: 617/326-8703© Analog Devices, Inc., 2002aZero-Drift, Single-Supply,Rail-to-Rail Input/Output Low Noise Operational AmplifierPreliminary Technical Data AD8628FEATURESLowest auto-zero amplifier noiseLow Offset Voltage: 5 µVInput Offset Drift: 0.03 µV/°CRail-to-Rail Input and Output Swing5 V Single-Supply OperationHigh Gain, CMRR, and PSRR: 120 dBVery Low Input Bias Current: 100 pALow Supply Current: 1.3 mAOverload Recovery Time: 0.2 msNo External Components RequiredAPPLICATIONSAutomotive SensorsPressure and Position SensorsStrain Gage AmplifiersMedical InstrumentationThermocouple AmplifiersGENERAL DESCRIPTIONThis new family of amplifiers has ultra-low offset, drift and bias current. The AD8628 is a wide bandwidth auto-zero amplifier featuring rail-to-rail input and output swings and low noise. Operation is fully specified from 2.7 to 5 volts single supply (±1.35V to ±2.5V dual supply).The AD8628 family provides the benefits previously found only in expensive auto-zeroing or chopper-stabilized amplifiers. Using Analog Devices’ new topology these zero-drift amplifiers combine low cost, with high accuracy and low noise. (No external capacitors are required.) In addition, the AD8628 greatly reduces the digital switching noise found in most chopper stabilized amplifiers.With an offset voltage of only 1µV, drift less than 0.005 µV/°C and noise of only 0.5uV P-P (0Hz to 10 Hz) the AD8628 is perfectly suited for applications where error sources cannot be tolerated. Position and pressure sensors, medical equipment, and strain gage amplifiers benefit greatly from nearly zero drift over their operating temperature range. Many systems may take advantage of the rail-to-rail input and output swings provided by the AD8628 family to reduce input biasing complexity and maximize SNR.The AD8628 family is specified for the extended industrial (-40° to +125°C) temperature range. The AD8628 amplifier is available in the tiny SOT23 and the popular 8-pin narrow SOIC plastic packages.5-Lead SOT(RT-5)8-Lead SO(R-8)AD8628AD8628SpecificationsPRELIMINARY TECHNICAL DATAAD8628– 2 – REV. PrA 1/29/02PRELIMINARY TECHNICAL DATAAD8628– 3 –SpecificationsPRELIMINARY TECHNICAL DATAAD8628– 4 – REV. PrA 1/29/02ABSOLUTE MAXIMUM RATINGSSupply Voltage..........................................................................+6V Input Voltage......................................................GND to Vs + 0.3V Differential Input Voltage 1.....................................................±5.0V Output Short-Circuit Duration to Gnd...............................Indefinite Storage Temperature RangeRT, R Package...............................................-65°C to +150°C Operating Temperature RangeAD8628.........................................................-40°C to +125°C Junction Temperature RangeRT, R Package...............................................-65°C to +150°C Lead Temperature Range (Soldering, 10 sec).......................+300°CNOTES1 Differential input voltage is limited to ±5.0 volts or the supply voltage, whichever is less.2 θJA is specified for the worst case conditions, i.e., θJAis specified for device in socket for P-DIP packages; θJA is specified for device soldered in circuit board for SOIC and TSSOP packages.ORDERING GUIDE。

Rev. DDocument Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However , noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Speci cations subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved. Technical Support 引脚接线图NIC 1–IN 2+IN 3V–4NIC 8V+7OUT 6NIC5NOTES1. NIC = NO INTERNAL CONNECTION.ADA4528-1TOP VIEW (Not to Scale)09437-001图1. ADA4528-1引脚配置(8引脚MSOP)09437-102ADA4528-1TOP VIEW (Not to Scale)3+IN –V 41NIC 2–IN 6OUT 5NIC8NIC7V+NOTES1. NIC = NO INTERNAL CONNECTION.2. CONNECT THE EXPOSED PAD TO V– OR LEAVE IT UNCONNECTED.图2. ADA4528-1引脚配置(8引脚LFCSP)1101001101001k 10k 100k 1M 10MV O L T A G E N O I S E D E N S I T Y (n V /√H z )FREQUENCY (Hz)09437-063V SY = 5V V CM = V SY /2A V = 1图3. 电压噪声密度与频率的关系表1. ADI 公司零漂移运算放大器产品组合 1类型 超低噪声微功耗(<20 μA)低功耗(<1 mA) 16 V工作电压30 V 工作电压单通道 ADA4528-1 ADA4051-1 AD8628 AD8638 ADA4638-1AD8538双通道 ADA4528-2 ADA4051-2 AD8629 AD8639AD8539 四通道AD86301欲选择最新的零漂移运算放大器，请访问 。

ADS528x 评估板用户手册2008年1月ZHCU007内容2ZHCU007–2008年1月内容1概述 42电路描述 73TI 公司模数转换器串行外围接口控制接口 94模数转换器评价 125 勘误表146物理描述15重要的注释271.1 目的41.2 评估板基本功能51.3 ADS528x 评估板快速启动程序62.1 原理图 72.2 电路功能模块73.1 安装模数转换器串行外围接口控制软件 93.2 利用TI 公司模数转换器串行外围接口软件94.1 选择硬件124.2 选择相关的输入频率135.1 印刷电路勘误表 146.1 印刷电路板布局 156.2 材料清单 196.3 印刷电路板图22图表1 ADS5281评估板52 TI公司模数转换器串行外围接口控制接93 顶层印刷层154 地线层165 电源层176 底层的印刷层187 评估板原理图1 228 评估板原理图2 239 评估板原理图3 2410 评估板原理图42511 评估板原理图526表列表1 三个跳线表62 评估板的供电电源选择73 ADS528X 经常使用的寄存器114 材料清单19 ZHCU007–2008年1月图表3ADS528x 评估板用户手册4ZHCU007–2008年1月应用报告ZHCU007–2008年1月概述本用户指南主要描述了ADS5281/82/87 (ADS528X) QFN 芯片评估板的整体情况，并且给出了评估板的一般特征和主要功能。

图1是评估板的图片。

11.1目的评估板提供了一个测试平台，主要是测试8通道的ADS528X 模数转换器在各种信号、参考电压和供电条件下性能，本指导书还包含了评估板的原理图。

ADS5281和DS5282 芯片是12位模数转换器，而ADS5287芯片是10位模数转换器。

ADS528x 评估板用户手册5ZHCU007–2008年1月 1.2EVM Basic FunctionsOverviewFigure 1.ADS5281EVMEight analog inputs to the ADC are provided via external SMA connectors.The EVM provides an external SMA connector for input of the ADC clock.The ADC can be clocked using either a single-ended or differential clock.Provisions are made on the EVM to allow users to evaluate the ADC using a single-ended PECL clock and a differential transformer-coupled clock.Digital output from the EVM is via a high-speed,high-density Samtec output header.The digital output connector mates directly to the TSW1200Rev B or through an adapter to the TI ADSDeSer-50EVM,both of which deserialize the serial data stream into parallel CMOS data.Power connections to the EVM are via banana jack sockets.Separate sockets are provided for the ADC analog and ADC digital supplies and for the auxiliary circuits.6SLAU205–January 2008Submit Documentation Feedback图1. ADS5281 评估板1.2评估板基本功能通过外部SMA 连接器，给模数转换器提供8个模拟输入。

DescriptionThe Avago Technologies ADNS-5020 is an entry-level, small form factor optical mouse sensor. It comes with many built-in features and optimized for LED-based corded products.The ADNS-5020 is capable of high-speed motion detection – up to 14 ips and 2G. In addition, it has an on-chip oscillator and built-in LED driver to minimize external components. Frame rate is also adjusted internally.The ADNS-5020 along with the ADNS-5100/ADNS-5100-00 lens, ADNS-5200 clip and HLMP-ED80 LED form a complete and compact mouse tracking system. There are no moving parts, which means high reliability and less maintenance for the end user. In addition, precision optical alignment is not required, facilitating high volume assembly.The sensor is programmed via registers through a three-wire SPI interface. It is housed in an 8-pin staggered dual in-line package (DIP).Theory of OperationThe ADNS-5020 is based on Optical Navigation Technology, which measures changes in position by optically acquiring sequential surface images (frames) and mathematically determining the direction and magnitude of movement.The ADNS-5020 contains an Image Acquisition System (IAS), a Digital Signal Processor (DSP), and a three wire serial port.The IAS acquires microscopic surface images via the lens and illumination system. These images are processed by the DSP to determine the direction and distance of motion. The DSP calculates the D x and D y relative displacement values.An external microcontroller reads the D x and D y information from the sensor serial port. The microcontroller then translates the data into PS2 or USB signals before sending them to the host PC.Features•Small form factor•Built-in LED driver for simpler circuitry•High speed motion detection up to 14 ips and 2G •Self-adjusting frame rate for optimum performance •Internal oscillator – no clock input needed •Selectable 500 and 1000 cpi resolution •Operating voltage: 5 V nominal• Three-wire serial interface• Minimal number of passive components Applications•Optical mice•Optical trackballs•Integrated input devicesADNS-5020 Optical Mouse SensorData SheetPin Name Description1SDIO Serial Port Data Input and Output 2XY_LED LED Control3NRESET Reset Pin (active low input)4NCS Chip Select (active low input)5VDD5Supply Voltage 6GND Ground7REGO Regulator Output 8SCLKSerial Clock InputFigure 1. Package outline drawing (top view).Figure 2. Package outline drawing.CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.NOTES:1. DIMENSIONS IN MILLIMETERS (INCHES).2. DIMENSIONAL TOLERANCE: ± 0.1 mm.3. COPLANARITY OF LEADS: 0.1 mm.4. CUMULATIVE PITCH TOLERANCE: ± 0.15 mm.5. LEAD PITCH TOLERANCE: ± 0.15 mm.6. MAXIMUM FLASH: + 0.2 mm.7. LEAD WIDTH: ± 0.5 mm.8. ANGULAR TOLERANCE: ± 3.0°.0.50LEAD PITCH∅ 5.00(0.197)0.80(0.031)PATHAvago Technologies provides an IGES file drawing describing the base plate molding features for lens and PCB alignment.The ADNS-5020 sensor is designed for mounting on a through-hole PCB, looking down. There is an aperture stop and features on the package that align to the lens.The ADNS-5100/5100-001 lens provides optics for the imaging of the surface as well as illumination of the surface at the optimum angle. Features on the lens align it to the sensor, base plate, and clip with the LED.Figure 3. Recommended PCB mechanical cutouts and spacing.The ADNS-5200 clip holds the LED in relation to the lens. The LED must be inserted into the clip and the LED’s leads formed prior to loading on the PCB. The HLMP-ED80 LED is recommended for illumination.ALL DIMENSIONS IN MILLIMETERS (INCHES).2.40(0.094)Figure 4. 2D Assembly drawing of ADNS-5020 (top and side views).Figure 5. Exploded view drawing.PCB Assembly Considerations1.Insert the sensor and all other electrical components into PCB.2.Insert the LED into the assembly clip and bend the leads 90 degrees.3.Insert the LED clip assembly into PCB.4.Wave solder the entire assembly in a no-wash solder process utilizing solder fixture. The solder fixture is needed to protect the sensor during the solder process. It also sets the correct sensor-to-PCB distance as the lead shoulders do not normally rest on the PCB surface. The fixture should be designed to expose the sensor leads to solder while shielding the optical aperture from direct solder contact.5.Place the lens onto the base plate.6.Remove the protective kapton tape from optical aperture of the sensor. Care must be taken to keep contaminants from entering the aperture. Recommend not to place the PCB facing up during the entire mouse assembly process. Recommend to hold the PCB first vertically for the kapton removal process.7.Insert PCB assembly over the lens onto the base plate aligning post to retain PCB assembly. The sensor aperture ring should self-align to the lens.Figure 6. Block diagram of ADNS-5020 optical mouse sensor.8.The optical position reference for the PCB is set by the base plate and lens. Note that the PCB motion due to button presses must be minimized to maintain optical alignment.9.Install mouse top case. There MUST be a feature in the top case to press down onto the PCB assembly to ensure all components are interlocked to the correct vertical height.P O W E R A N D C O N T R O LS E R I A L P O R T A N DR E G I S T E R SIMAGE ARRAYDSP OSCILLATOR LED DRIVEREGOGND VDD5NCS ADNS-5020SCLK SDIO NRESETXY_LEDADNS-5100 (LENS)CUSTOMER SUPPLIED PCBHLMP-ED80 (LED)ADNS-5200 (LED CLIP)SENSORDesign Considerations for Improved ESD Performance For improved electrostatic discharge performance, typical creepage and clearance distance are shown in the table below. Assumption: base plate construction as per the Avago Technologies supplied IGES file and ADNS-5100/5100-001 lens.Typical Distance MillimetersCreepage16.0Clearance 2.1Note that the lens material is polycarbonate and therefore, cyanoacrylateFigure 7. Sectional view of PCB assembly highlighting optical mouse components.DFigure 8. Schematic diagram for interface between ADNS-5020 and microcontroller.Regulatory Requirements•Passes FCC B and worldwide analogous emission limits when assembledinto a mouse with shielded cable and following Avago Technologiesrecommendations.•Passes IEC-1000-4-3 radiated susceptibility level when assembled intoa mouse with shielded cable and following Avago Technologiesrecommendations.•Passes EN61000-4-4/IEC801-4 EFT tests when assembled into amouse with shielded cable and following Avago Technologiesrecommendations.•UL flammability level UL94 V-0.•Provides sufficient ESD creepage/clearance distance to avoid discharge upto 15 kV when assembled into a mouse using ADNS-5100 round lensaccording to usage instructions above.Absolute Maximum RatingsParameter Symbol Minimum Maximum Units NotesStorage Temperature T S-4085°CLead Solder Temp260°CSupply Voltage V DD-0.5 5.5VESD2kV All pins, human body model MIL 883 Method 3015 Input Voltage V IN-0.5V DD+0.5V All I/O pinsOutput Current Iout7mA SDIO pinRecommended Operating ConditionsParameter Symbol Minimum Typical Maximum Units NotesOperating Temperature T A040°CPower Supply V DD 4.0 5.0 5.25VPower Supply Rise Time V RT0.005100ms0 to V DDSupply Noise (Sinusoidal)V NA100mV p-p10 kHz-50 MHzSerial Port Clock Frequency f SCLK1MHz50% duty cycle.Distance from Lens Reference Z 2.3 2.4 2.5mmPlane to Tracking Surface (Z)Speed S14ipsAcceleration a2GLoad Capacitance C out100pF SDIOAC Electrical SpecificationsElectrical Characteristics over recommended operating conditions. Typical values at 25 °C, V DD = 5.0 V.Parameter Symbol Minimum Typical Maximum Units NotesReset Pulse Widtht RESET 250ns Active low.Motion Delay after Reset t MOT-RST 50ms From NRESET pull high to valid motion,assuming V DD and motion is present.SDIO Rise Time t r-SDIO 150300ns C L = 100pF SDIO Fall Timet f-SDIO 150300ns C L = 100pFSDIO delay after SCLKt DLY-SDIO 120ns From SCLK falling edge to SDIO data valid, no load conditions.SDIO Hold Time t hold-SDIO 0.51/f SCLKus Data held until next falling SCLK edge.SDIO Setup Timet setup-SDIO 120ns From data valid to SCLK rising edge.SPI Time between Write Commandst SWW30µsFrom rising SCLK for last bit of the first data byte, to rising SCLK for last bit of the second data byte.SPI Time between Write t SWR 20µsFrom rising SCLK for last bit of the first and Read Commands data byte, to rising SCLK for last bit of the second address byte.SPI Time between Read t SRW 500nsFrom rising SCLK for last bit of the first and Subsequent Commands t SRR data byte, to falling SCLK for the first bit of the next address.SPI Read Address-Data Delayt SRAD4µsFrom rising SCLK for last bit of the address byte, to falling SCLK for first bit of data being read.NCS Inactive after Motion Burst t BEXIT 250ns Minimum NCS inactive time after motion burst before next SPI usage.NCS to SCLK Active t NCS-SCLK 120ns From NCS falling edge to first SCLK rising edge.SCLK to NCS Inactive t SCLK-NCS 120ns From last SCLK rising edge to NCS (for read operation)rising edge, for valid SDIO data transfer.SCLK to NCS Inactive t SCLK-NCS 20us From last SCLK rising edge to NCS (for write operation)rising edge, for valid SDIO data transfer.NCS to SDIO High-Z t NCS-SDIO 500ns From NCS rising edge to SDIO high-Z state.Transient Supply CurrentI DDT60mAMax supply current during a V DD ramp from 0 to V DD .Figure 9. Distance from lens reference plane to tracking surface (Z).(0.094)Z =DC Electrical SpecificationsElectrical Characteristics over recommended operating conditions. Typical values at 25 °C, V DD = 5.0 V.Parameter Symbol Minimum Typical Maximum Units NotesDC Supply Current I DD_AVG 3.66mA Average sensor current, at max frame rate.No load on SDIO.Idle Supply Current 2mA Input Low Voltage V IL 0.5V SCLK, SDIO, NCS, NRESET Input High Voltage V IH V DD – 0.5V SCLK, SDIO, NCS, NRESET Input Hysteresis V I_HYS 200mV SCLK, SDIO, NCS, NRESETInput Leakage Current I leak ±1±10µA Vin = VDD-0.6 V, SCLK, SDIO, NCS, NRESET XY_LED Current I XY_LED 29mA XY_LED pin voltage range should be greater than 0.8 V.Output Low Voltage V OL 0.7V I out = 1 mA, SDIO Output High Voltage V OH VDD-0.7V I out = -1 mA, SDIOInput CapacitanceC in50pFNCS, SCLK, SDIO, NRESETTypical Performance CharacteristicsFigure 10. Mean resolution vs. distance from lens reference plane to surface.Figure 11. Average error vs. distance (mm).Figure 12. Relative wavelength responsivity.101520253035404550No r m a l i z e d R e s p o n s eWavelength (nm)LED ModeFor power savings, the LED will not be continuously on. ADNS-5020 will pulse the LED only when needed.Synchronous Serial PortThe synchronous serial port is used to set and read parameters in the ADNS-5020, and to read out the motion information.The port is a three wire serial port. The host micro-controller always initiates communication; the ADNS-5020 never initiates data transfers. SCLK, SDIO,and NCS may be driven directly by a micro-controller. The port pins may be shared with other SPI slave devices. When the NCS pin is high, the inputs are ignored and the output is tri-stated.The lines that comprise the SPI port:SCLK:Clock input. It is always generated by the master(the micro-controller).SDIO:Input and Output data.NCS:Chip select input (active low). NCS needs to be low to activatethe serial port; otherwise, SDIO will be high Z,and SDIO & SCLK will be ignored. NCS can also be used to reset the serial port in case of an error.Write OperationSDIO Setup and Hold TimeChip Select OperationThe serial port is activated after NCS goes low. If NCS is raised during a transaction, the entire transaction is aborted and the serial port will be reset.This is true for all transactions. After a transaction is aborted, the normal address-to-data or transaction-to-transaction delay is still required before beginning the next transaction. To improve communication reliability, all serial transactions should be framed by NCS. In other words, the port should not remain enabled during periods of non-use because ESD and EFT/B events could be interpreted as serial communication and put the chip into an unknown state. In addition, NCS must be raised after each burst-mode transaction i s c omplete t o t erminate b urst-mode. T he p ort i s n ot a vailable f or further use until burst-mode is terminated.Write OperationWrite operation, defined as data going from the micro-controller to the ADNS-5020, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address (seven bits) and has a “1” as its MSB to indicate data direction. The second byte contains the data. The ADNS-5020 reads SDIO on rising edges of SCLK.11234567891011121314151621D 0D 5D 6D 7A 0A 1A 2A 3A 4A 5A 61A 6D 4D 3D 2D 1SCLK NCSSDIOSDIO DRIVEN BY MICRO-CONTROLLERsetupSCLKSDIORead OperationA read operation, defined as data going from the ADNS-5020 to the micro-controller, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address, is sent by the micro-controller over SDIO, and has a “0” as its MSB to indicate data direction. The second byte contains the data and is driven by the ADNS-5020 over SDIO. The sensor outputs SDIO bits on falling edges of SCLK and samples SDIO bits on every rising edge of SCLK.Read OperationMicrocontroller to ADNS-5020 HandoffADNS-5020 to Microcontroller HandoffNOTE: The 0.5/f SCLK minimum high state of SCLK is also the minimum SDIO data hold time of the ADNS-5020. Since the falling edge of SCLK is actually the start of the next read or write command, the ADNS-5020 will hold the state of data on SDIO until the falling edge of SCLK.12345678910111213141516SCLK CYCLE #SCLK SDIOSDIO DRIVEN BY MICRO-CONTROLLERSDIO DRIVEN BY ADNS-5020DETAIL "A"MICROCONTROLLER TO ADNS-5020SDIO HANDOFFSDIOSCLKSCLKSDIODETAIL "B"ADNS-5020 TOMICROCONTROLLER SDIO HANDOFFRequired Timing between Read and Write CommandsThere are minimum timing requirements between read and write commands on the serial port.If the rising edge of the SCLK for the last data bit of the second write command occurs before the required delay (t SWW ), then the first write command may not complete correctly.Timing between Two Write CommandsIf the rising edge of SCLK for the last address bit of the read command occurs before the required delay (t SWR ), the write command may not complete correctly.Timing between Write and Read CommandsDuring a read operation SCLK should be delayed at least t SRAD after the last address data bit to ensure that the ADNS-5020 has time to prepare the requested data. The falling edge of SCLK for the first address bit of either the read or write command must be at least t SRR or t SRW after the last SCLK rising edge of the last data bit of the previous read operation.Timing between Read and Either Write or Subsequent Read CommandsWRITE OPERATIONWRITE OPERATIONWRITE OPERATION NEXT READ OPERATION• • •READ OPERATIONNEXT READor WRITE OPERATION• • •Notes on Power-up and ResetThe ADNS-5020 does not perform an internal power up self-reset; the NRESET pin must be asserted low every time power is applied. There are two ways to reset the chip, either assert low NRSET pin or by writing 0x5a to register 0x3a. A full reset will thus be executed. Any register settings must then be reloaded.During power-up there will be a period of time after the power supply is high but before any clocks are available. The table below shows the state of the various pins during power-up and reset.State of Signal Pins After VDD is Valid Pin During Reset After ResetNCS Ignored Functional SDIO Ignored Depends on NCS SCLK Ignored Depends on NCS XY_LED Hi-Z FunctionalBurst Mode OperationBurst mode is a special serial port operation mode that may be used to reduce the serial transaction time for a motion read. The speed improvement is achieved by continuous data clocking to or from multiple registers without the need to specify the register address, and by not requiring the normal delay period between data bytes.Burst mode is activated by reading the Motion_Burst register. The ADNS-5020 will respond with the contents of the Delta_X, Delta_Y, SQUAL,Shutter_Upper, Shutter_Lower, Maximum_Pixel and Pixel_Sum registers in that order. The burst transaction can be terminated anywhere in the sequence after the Delta_X value by bringing the NCS pin high. After sending the register address, the micro-controller must wait t SRAD and then begin reading data. All data bits can be read with no delay between bytes by driving SCLK at the normal rate. The data are latched into the output buffer after the last address bit is received. After the burst transmission is complete,the micro-controller must raise the NCS line for at least t BEXIT to terminate burst mode. The serial port is not available for use until it is reset with NCS,even for a second burst transmission.Avago Technologies highly recommends the usage of burst mode operation in optical mouse sensor design applications.Motion Burst TimingMOTION_BURST REGISTER ADDRESSREAD FIRST BYTEFIRST READ OPERATION READ SECOND BYTE READ THIRD BYTESCLK• • •RegistersThe ADNS-5020 registers are accessible via the serial port. The registers areused to read motion data and status as well as to set the device configuration.Address Register Read/Write Default Value 0x00Product_ID R0x120x01Revision_ID R0x000x02Motion R0x000x03Delta_X R Any0x04Delta_Y R Any0x05SQUAL R Any0x06Shutter_Upper R Any0x07Shutter_Lower R Any0x08Maximum_Pixel R Any0x09Pixel_Sum R Any0x0a Minimum_Pixel R Any0x0b Pixel_Grab R/W Any0x0c Reserved0x0d Mouse Control R/W0x000x0e – 0x39Reserved0x3a Chip_Reset W N/A0x3b – 0x3e Reserved0x3f Inv_Rev_ID R0xff0x40 – 0x62Reserved0x63Motion_Burst R0x00Access: Read Reset Value: 0x12Bit76543210Field PID7PID6PID5PID4PID3PID2PID1PID0 Data Type: 8-Bit unsigned integerUSAGE:This register contains a unique identification assigned to the ADNS-5020. The value in this register does not change; it can be used to verify that the serial communications link is functional.Revision_ID Address: 0x01Access: Read Reset Value: 0x00Bit76543210Field RID7RID6RID5RID4RID3RID2RID1RID0 Data Type: 8-Bit unsigned integerUSAGE:This register contains the IC revision. It is subject to change when new IC versions are released.Motion Address: 0x02Access: Read/Write Reset Value: 0x00Bit76543210Field MOT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Data Type: Bit field.USAGE:Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If the MOT bit is set, then the user should read registers 0x03 and 0x04 to get the accumulated motion. Read this register before reading the Delta_X and Delta_Y registers.Writing anything to this register clears the MOT bit, Delta_X and Delta_Y registers. The written data byte is not saved.Field Name DescriptionMOT Motion since last report0 = No motion1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registersReserved ReservedAccess: ReadReset Value: 0x00Bit 76543210FieldX 7X 6X 5X 4X 3X 2X 1X 0Data Type: Eight bit 2’s complement number.USAGE:X movement is counts since last report. Absolute value is determined by resolution. Reading clears the register.NOTE: Avago Technologies RECOMMENDS that registers 0x03 and 0x04 be read sequentially.8081FE FF 0001027E 7F-128-127-2-1+1+2+126+127MOTIONDELTA_X Delta_Y Address: 0x04Access: ReadReset Value: 0x00Bit 76543210FieldY 7Y 6Y 5Y 4Y 3Y 2Y 1Y 0Data Type: Eight bit 2’s complement number.USAGE:Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the register.NOTE: Avago Technologies RECOMMENDS that registers 0x03 and 0x04 be read sequentially.-128-127-2-1+1+2+126+127MOTIONDELTA_YData Type: Upper 8 bits of a 9-bit unsigned integer.USAGE:SQUAL (Surface Quality) is a measure of the number of valid features visible by the sensor in the current frame.The maximum SQUAL register value is 144. Since small changes in the current frame can result in changes in SQUAL, variations in SQUAL when looking at a surface are expected. The graph below shows 250 sequentially acquired SQUAL values, while a sensor was moved slowly over white paper. SQUAL is nearly equal to zero, if there is no surface below the sensor. SQUAL is typically maximized when the navigation surface is at the optimum distance from the imaging lens (the nominal Z-height).Figure 13. Squal values (white paper).Figure 14. Mean squal vs. Z (white paper).Access: ReadReset Value: 0x00Bit 76543210FieldSQ 7SQ 6SQ 5SQ 4SQ 3SQ 2SQ 1SQAccess: Read Reset Value: 0x00Bit76543210Field S15S14S13S12S11S10S9S8Shutter_Lower Address: 0x07Access: Read Reset Value: 0x00Bit76543210Field S7S6S5S4S3S2S1S0 Data Type: Sixteen bit unsigned integer.USAGE:Units are clock cycles. Read Shutter_Upper first, then Shutter_Lower. They should be read consecutively. The shutter is adjusted to keep the average and maximum pixel values within normal operating ranges. The shutter value is automatically adjusted.Figure 15. Shutter (white paper).300250200150100Figure 16. Mean shutter vs. Z (white paper).Maximum_Pixel Address: 0x08Access: Read Reset Value: 0x00Bit76543210Field MP0MP6MP5MP4MP3MP2MP1MP0Data Type: Eight-bit number.USAGE:Maximum Pixel value in current frame. Minimum value = 0, maximum value = 127. The maximum pixel value can vary with every frame.Pixel_Sum Address: 0x09Access: Read Reset Value: 0x00Bit76543210Field AP7AP6AP5AP4AP3AP2AP1AP0 Data Type: High 8 bits of an unsigned 15-bit integer.USAGE:This register is the accumulated pixel value from the last image taken. The maximum accumulator value is 28,575, but only bits [14:7] are reported.It may be described as the full sum divided by 1.76.The maximum register value is 223. The minimum is 0. The pixel sum value can change on every frame.Minimum_Pixel Address: 0x0aAccess: Read Reset Value: 0x00Bit76543210Field MP0MP6MP5MP4MP3MP2MP1MP0 Data Type: Eight-bit number.USAGE:Minimum Pixel value in current frame. Minimum value = 0, maximum value = 127. The minimum pixel value can vary with every frame.Pixel_Grab Address: 0x0bAccess: Read/Write Reset Value: 0x00Bit76543210Field Valid PD6PD5PD4PD3PD2PD1PD0Data Type: Eight-bit word.USAGE:The pixel grabber captures 1 pixel per frame. If there is a valid pixel in the grabber when this register is read, the MSB will be set, an internal counter will incremented to capture the next pixel and the grabber will be armed to capture the next pixel. It will take 225 reads to upload the complete image. Any write to this register will reset and arm the grabber to grab pixel 0 on the next image.Physical Pixel Address Map – readout order of the array(looking through the sensor aperture at the bottom of the package)TOP X-RAY VIEW OF MOUSEBOTTOM VIEW OF MOUSEReserved Address: 0x0cMouse_control Address: 0x0dAccess: Read/Write Reset Value: 0x00Bit76543210Field Reserved Reserved Reserved Reserved Reserved Reserved Reserved RES Data Type: Eight bit numberUSAGE:Resolution and chip reset information can be accessed or to be edited by this register.Field Name DescriptionRES Set resolution0 = 500 cpi1 = 1000 cpiReserved ReservedReserved Address: 0x0e-0x39Chip_Reset Address: 0x3aAccess: Write Reset Value: 0x00Bit76543210Field CR7CR 6CR 5CR 4CR 3CR 2CR 1CR 0 Data Type: 8-Bit unsigned integerUSAGE:Write 0x5a to initiate chip RESET.Reserved Address: 0x3b – 0x3eInv_Rev_ID Address: 0x3fAccess: Read Reset Value: 0xffBit76543210Field RRID7RRID6RRID5RRID4RRID3RRID2RRID1RRID0 Data Type: 8-Bit unsigned integerUSAGE:This register contains the inverse of the revision ID which is located at register 0x01.Reserved Address: 0x40-0x62Motion_Burst Address: 0x63Access: Read Reset Value: 0x00Bit76543210Field MB7MB6MB5MB4MB3MB2MB1MB0 Data Type: Various.USAGE:Read from this register to activate burst mode. The sensor will return the data in the Delta_X, Delta_Y, Squal, Shutter_Upper, Shutter_Lower, Maximum_Pixel and Pixel_Sum. If the burst is not terminated at this point, the internal address counter stops incrementing and Pixel Sum register’s value will be continuously returned. Bursts are terminated when NCS is raised.For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0095ENAV02-0114EN January 25, 2007。

AD5206: 6通道、256位数字电位计产品概述：AD5204/AD5206分别是4/6通道、256位、数字控制可变电阻(VR)器件，可实现与电位计或可变电阻相同的电子调整功能。

各通道均内置一个带游标触点的固定电阻，该游标触点在载入SPI兼容串行输入寄存器的数字码所确定的点位分接该固定电阻值。

游标与固定电阻任一端点之间的电阻值，随传输至VR锁存器中的数字码呈线性变化。

在A端子与游标或B端子与游标之间，可变电阻提供一个完全可编程电阻值。

A至B固定端接电阻（10 kΩ、50 kΩ或100 kΩ）的标称温度系数为700 ppm/°C 。

每个VR均有各自的VR锁存器，用来保存其编程电阻值。

这些VR锁存器由一个内部串行至并行移位寄存器更新，该移位寄存器从一个标准三线式串行输入数字接口加载数据。

由11个数据位构成的数据字读入串行输入寄存器。

前3位经过解码，可确定当 CS 选通脉冲变回逻辑高电平时，哪一个VR锁存器需要载入该数据字的后8位。

利用串行寄存器相对端的串行数据输出引脚（仅限AD5204），就可以简单地以菊花链形式连接多个VR，而无需额外的外部解码逻辑。

可选复位(PR)引脚可将0x80载入VR锁存器，从而强制AD5204的所有游标处于中量程位置。

AD5204/AD5206提供24引脚表贴SOIC、TSSOP和PDIP三种封装。

AD5204还提供32引脚、5 mm × 5 mm LFCSP封装。

所有器件的保证工作温度范围均为−40°C至+85°C 工业温度范围。

欲了解更多单通道、双通道和四通道器件，请参考AD8400/AD8402/AD8403数据手册。

应用•机械电位计的替代产品•仪器仪表：增益、失调电压调整•可编程电压至电流转换•可编程滤波器、延迟、时间常数•线路阻抗匹配AD5206 功能框图AD5206管脚图：AD5206管脚功能介绍：。

AD7682: 16位、4通道/8通道、250 KSPS® ADCAD7682/AD7689是4/8通道、16位、电荷再分配逐次逼近寄存器(SAR)型模数转换器（ADC），采用单电源VDD供电。

AD7682/AD7689拥有多通道、低功耗数据采集系统所需的所有组成部分，包括：无失码的真16位SAR ADC；用于将输入配置为单端输入（使用或不使用参考地）、差分输入或双极性输入的4通道(AD7682)或8通道(AD7689)低串扰多路复用器；内部低漂移基准源（可以选择2.5 V或4.096 V）和缓冲器；温度传感器；可选择的单极点滤波器；以及当多通道依次连续采样时非常有用的序列器。

AD7682/AD7689使用简单的SPI接口实现配置寄存器的写入和转换结果的接收。

SPI接口使用单独的电源(VIO)，它被设定为主机逻辑电平。

功耗与吞吐速率成正比。

AD7682/AD7689采用小型20引脚LFCSP封装，工作温度范围为−40°C至+85°C。

应用- 多通道系统监控- 电池供电设备- 医疗仪器：ECG/EKG- 移动通信：GPS- 电源线路监控- 数据采集- 地震数据采集系统- 仪器仪表- 过程控制特点和优势•提供中文数据手册•16位分辨率、无失码•4通道(AD7682)/8通道(AD7689)多路复用器输入可选择：单极性单端输入差分输入（使用参考地伪双极性输入•吞吐速率：250 kSPS•INL：典型值±0.4 LSB，最大值±1.5 LSB（±23 ppm或FSR）•动态范围：93.8 dB•SINAD：92.5 dB (20 kHz)•THD：-100 dB（20 kHz时）•模拟输入范围：0 V至VREF，VREF可达VDD•欲了解更多特性，请参考数据手册。