EDA课程设计-电子钟一、设计要求1、基本功能要求：设计一个电子时钟，要求可以显示时、分、秒，用户可以设置时间。
扩展功能要求：2、跑表功能，闹钟功能，调整数码管的亮度。
二、系统结构控制键—jian5、jian4、jian7、jian8：数码管显示段选信号输出sg：——选择6位数码管中的某一个显示数据；发光二极管控制信号输出—led（7~0）闹钟声音输出—speaker通过一个10M信号分出各种所需频率功能介绍运行后，选择模式7，8位数码管分显示时间的时、分、秒，当前为模式0：时间显示模式，按键7为模式选择键，按下按键7，系统进入模式1，第二次按下为模式2，设置时间模式，第三次按下为跑表模式，第四次为闹钟设置模式，第五次为亮度调节模式：设置时间模式，按键4控制更改数码管的位，按键5控制选中数码管的数值，时间设置完成后，按键按键8，设置时间会保存住，并在模式0中显示；系统进入模式2：秒表模式，按键4为开始/结束键，按键5为清零键；系统进入模式3：闹钟设置模式，相关设置与模式1相同，当当前时间与闹钟设置时间相同时，喇叭就会响；系统进入模式4:亮度调节模式，通过按键4设置亮度，共三种亮度；再按下按键7，系统又会进入模式0。
4、RTL图三、VHDL源程序1、library ieee; --通过10M分出所需频率use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin isport (clk_10M : in std_logic;clk_10000 : out std_logic;clk_100 : out std_logic;clk_1 : out std_logic);end entity;architecture sub1 of fenpin issignal Q_1 : std_logic_vector(8 downto 0);signal Q_2 : std_logic_vector(6 downto 0);signal Q_3 : std_logic_vector(6 downto 0);signal clk10000 : std_logic;signal clk100 : std_logic;signal clk1 : std_logic;beginprocess(clk_10M)beginif clk_10M'event and clk_10M='1' thenif Q_1=500 thenQ_1 <= "000000000";clk10000 <= not clk10000;if Q_2=100 thenQ_2 <= "0000000";clk100<= not clk100;if Q_3=100 thenQ_3 <= "0000000";clk1<=not clk1;else Q_3<=Q_3+1;end if;else Q_2<=Q_2+1;end if;else Q_1<=Q_1+1;end if;end if;end process;clk_10000 <= clk10000;clk_100 <= clk100;clk_1 <= clk1;end sub1;2、library ieee; --扫描数码管use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xianshi isport(clk_10000:in std_logic;jian4:in std_logic;moshi:in integer range 0 to 4;a0,a1,a3,a4,a6,a7:in integer range 0 to 9;sg11:out std_logic_vector(6 downto 0);bt11:out std_logic_vector(7 downto 0));end;architecture one of xianshi issignal cnt8 :std_logic_vector(2 downto 0);signal a :integer range 0 to 15;signal light: std_logic;signal flash:integer range 0 to 2;signal count1,count2:integer range 0 to 10;beginp1: process(cnt8,light,a0,a1,a3,a4,a6,a7)begincase cnt8 iswhen "000" => bt11<= "0000000"&(light);a<=a0;when "001" => bt11<= "000000"&(light)&'0';a<=a1; when "010" => bt11<= "00000"&(light)&"00";a<=15; when "011" => bt11<= "0000"&(light)&"000";a<=a3; when "100" => bt11<= "000"&(light)&"0000";a<=a4; when "101" => bt11<= "00"&(light)&"00000";a<=15; when "110" => bt11<= '0'&(light)&"000000";a<=a6; when "111" => bt11<= (light)&"0000000";a<=a7;when others => null;end case;end process p1;p2:process(clk_10000)beginif clk_10000'event and clk_10000 ='1' then cnt8 <= cnt8+1; end if;end process p2;p3:process(a)begincase a iswhen 0 => sg11<= "0111111";when 1 => sg11<= "0000110";when 2 => sg11<= "1011011";when 3 => sg11<= "1001111";when 4 => sg11<= "1100110";when 5 => sg11<= "1101101";when 6 => sg11<= "1111101";when 7 => sg11<= "0000111";when 8 => sg11<= "1111111";when 9 => sg11<= "1101111";when 10 => sg11<= "1110111";when 11 => sg11<= "1111100";when 12 => sg11<= "0111001";when 13 => sg11<= "1011110";when 14 => sg11<= "1111001";when 15 => sg11<= "1000000";when others => null;end case;end process p3;process(jian4,moshi)beginif moshi=4 thenif jian4'event and jian4='1' thenif flash =2 thenflash<=0;else flash<=flash+1;end if;end if;end if;end process;process(clk_10000,flash)beginif clk_10000'event and clk_10000 ='1' thencase flash iswhen 0 => light<='1';when 1 => if count1=2 thencount1<=0; light<='1';else count1<=count1+1;light<='0';end if;when 2 => if count2=4 thencount2<=0; light<='1';else count2<=count2+1;light<='0';end if;end case;end if;end process;end;3、library ieee; --跑表开始暂停use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity paobiao isport(clk_1:in std_logic;jian8:in std_logic;shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9; shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:out integer range 0 to 9); end entity;architecture bhv of paobiao issignal shi:integer range 0 to 100;signal fen:integer range 0 to 100;signal miao:integer range 0 to 100;beginprocess(clk_1,jian8,shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1)beginif jian8='1' thenshi<=shishi1*10+shige1;fen<=fenshi1*10+fenge1;miao<=miaoshi1*10+miaoge1;elsif clk_1'event and clk_1='1' thenif miao=59 thenmiao<=0;fen<=fen+1;elsif fen>59 thenfen<=0;shi<=shi+1;elsif shi>23 thenshi<=0;else miao<=miao+1;end if;end if;end process;miaoge2<=miao rem 10;miaoshi2<=miao/10;fenge2<=fen rem 10;fenshi2<=fen/10;shige2<=shi rem 10;shishi2<=shi/10;end;4、library ieee; --设置当前时间use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity settime isport(moshi:in integer range 0 to 4;jian4,jian5:in std_logic;shishi,shige,fenshi,fenge,miaoshi,miaoge:out integer range 0 to 9);end entity;architecture bav of settime issignal a:integer range 0 to 5;signal shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1: integer range 0 to 9; beginprocess(moshi,jian4)beginif moshi=1 thenif jian4'event and jian4='1' thenif a < 5 thena<=a+1;else a<=0;end if;end if;end if;end process;process(moshi,a,jian5)beginif moshi=1 thenif a=0 thenif jian5'event and jian5='1' thenif miaoge1 =9 thenmiaoge1<=0;else miaoge1<=miaoge1+1;end if;end if;end if;if a=1 thenif jian5'event and jian5='1' thenif miaoshi1 =5 thenmiaoshi1<=0;else miaoshi1<=miaoshi1+1;end if;end if;end if;if a=2 thenif jian5'event and jian5='1' thenif fenge1 =9 thenfenge1<=0;else fenge1<=fenge1+1;end if;end if;end if;if a=3 thenif jian5'event and jian5='1' thenif fenshi1 =5 thenfenshi1<=0;else fenshi1<=fenshi1+1;end if;end if;end if;if a=4 thenif jian5'event and jian5='1' thenif shige1 =9 thenshige1<=0;else shige1<=shige1+1;end if;end if;end if;if a=5 thenif jian5'event and jian5='1' thenif shishi1 =2 thenshishi1<=0;else shishi1<=shishi1+1;end if;end if;end if;end if;end process;miaoge<=miaoge1;miaoshi<=miaoshi1;fenge<=fenge1;fenshi<=fenshi1;shige<=shige1;shishi<=shishi1;end;5、library ieee; --秒表功能use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity miaobiao isport(clk_100:in std_logic;moshi:in integer range 0 to 4;jian5,jian4:in std_logic;fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:out integer range 0 to 9); end entity;architecture bhv of miaobiao issignal fen,miao,xmiao:integer range 0 to 99;signal start:std_logic:='0';signal reset:std_logic:='0';beginprocess(clk_100,jian5,jian4,moshi,reset,start)beginif moshi=2 thenif reset='1' thenfen<=0;miao<=0;xmiao<=0;elsif start='1' thenelsif clk_100'event and clk_100='1' thenif xmiao=99 thenxmiao<=0;miao<=miao+1;elsif miao>59 thenmiao<=0;fen<=fen+1;elsif fen>23 thenfen<=0;else xmiao<=xmiao+1;end if;end if;end if;end process;process(jian4,start)beginif jian4'event and jian4='1' thenstart<=not start;else start<=start;end if;end process;process(jian5,reset)beginif jian5'event and jian5='1' thenreset<=not reset;else reset<= reset;end if;end process;xmiaoge<=xmiao rem 10;xmiaoshi<=xmiao/10;miaoge<=miao rem 10;miaoshi<=miao/10;fenge<=fen rem 10;fenshi<=fen/10;end;6、library ieee; --设置闹钟时间use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity naozhongset isport(moshi:in integer range 0 to 4;jian4,jian5:in std_logic;shishi,shige,fenshi,fenge,miaoshi,miaoge:out integer range 0 to 9); end entity;architecture bav of naozhongset issignal a:integer range 0 to 5;signal fenshi1,fenge1,miaoge1: integer range 0 to 9;signal shishi1: integer range 0 to 9:=1;signal shige1: integer range 0 to 9:=2;signal miaoshi1: integer range 0 to 9:=0;beginprocess(moshi,jian4)beginif moshi=3 thenif jian4'event and jian4='1' thenif a < 5 thena<=a+1;else a<=0;end if;end if;end if;end process;process(moshi,a,jian5)beginif moshi=3 thenif a=0 thenif jian5'event and jian5='1' thenif miaoge1 =9 thenmiaoge1<=0;else miaoge1<=miaoge1+1;end if;end if;end if;if a=1 thenif jian5'event and jian5='1' thenif miaoshi1 =5 thenmiaoshi1<=0;else miaoshi1<=miaoshi1+1;end if;end if;end if;if a=2 thenif jian5'event and jian5='1' thenif fenge1 =9 thenfenge1<=0;else fenge1<=fenge1+1;end if;end if;end if;if a=3 thenif jian5'event and jian5='1' thenif fenshi1 =5 thenfenshi1<=0;else fenshi1<=fenshi1+1;end if;end if;end if;if a=4 thenif jian5'event and jian5='1' thenif shige1 =9 thenshige1<=0;else shige1<=shige1+1;end if;end if;end if;if a=5 thenif jian5'event and jian5='1' thenif shishi1 =2 thenshishi1<=0;else shishi1<=shishi1+1;end if;end if;end if;end if;end process;miaoge<=miaoge1;miaoshi<=miaoshi1;fenge<=fenge1;fenshi<=fenshi1;shige<=shige1;shishi<=shishi1;end;7、library ieee; --闹钟喇叭输出use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity naozhongspeaker isport(clk_100:in std_logic;shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9; shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:in integer range 0 to 9; speaker:out std_logic);end entity;architecture bav of naozhongspeaker isbeginprocess(clk_100,shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1,shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2)beginif shishi2=shishi1 and shige2=shige1 and fenshi2=fenshi1 andfenge2=fenge1 and miaoshi2=miaoshi1 thenspeaker<=clk_100;else speaker<='1';end if;end process;end;8、library ieee; --转换模式use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity moshi isport(jian7:in std_logic;moshi:out integer range 0 to 4);end;architecture one of moshi issignal moshis:integer range 0 to 4;beginprocess(jian7)beginif jian7'event and jian7='1' thenif moshis=4 thenmoshis<=0;else moshis<=moshis+1;end if;end if;end process;moshi<=moshis;end;9、library ieee; --五选一选择器use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mux5_1 isport(moshi:in integer range 0 to 4 ;shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9;shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:in integer range 0 to 9;shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3:in integer range 0 to 9; fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:in integer range 0 to 9;a0,a1,a3,a4,a6,a7:out integer range 0 to 9);end entity mux5_1;architecture bhv of mux5_1 isbeginprocess(shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1,shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2,shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3,fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge,moshi)begincase moshi iswhen 0 =>a0<=shishi1;a1<=shige1;a3<=fenshi1;a4<=fenge1;a6<=miaoshi1;a7<=miaoge1;when 1 =>a0<=shishi2;a1<=shige2;a3<=fenshi2;a4<=fenge2;a6<=miaoshi2;a7<=miaoge2;when 2 =>a0<=fenshi;a1<=fenge;a3<=miaoshi;a4<=miaoge;a6<=xmiaoshi;a7<=xmiaoge;when 3 =>a0<=shishi3;a1<=shige3;a3<=fenshi3;a4<=fenge3;a6<=miaoshi3;a7<=miaoge3;when 4 => a0<=8;a1<=8;a3<=8;a4<=8;a6<=8;a7<=8;end case;end process;end;10、library ieee; --主程序置顶use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity clock isport(clk_10M:in std_logic;jian5,jian4,jian7,jian8:in std_logic;sg:out std_logic_vector(6 downto 0);bt:out std_logic_vector(7 downto 0);speaker:out std_logic);end entity;调用声明语句architecture bav of clock iscomponent fenpin --分频port (clk_10M : in std_logic;clk_10000 : out std_logic;clk_100 : out std_logic;clk_1 : out std_logic);end component;component paobiao --跑表port(clk_1:in std_logic;jian8:in std_logic;shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9; shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:out integer range 0 to 9);end component;component xianshi --扫描显示port(clk_10000:in std_logic;jian4:in std_logic;moshi:in integer range 0 to 4;a0,a1,a3,a4,a6,a7:in integer range 0 to 9;sg11:out std_logic_vector(6 downto 0);bt11:out std_logic_vector(7 downto 0));end component;component moshi --模式转换port(jian7:in std_logic;moshi:out integer range 0 to 4);end component;component mux5_1 --五选一选择器port(moshi:in integer range 0 to 4 ;shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9;shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:in integer range 0 to 9;shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3:in integer range 0 to 9;fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:in integer range 0 to 9;a0,a1,a3,a4,a6,a7:out integer range 0 to 9);end component;component settime --设置当前时间port(moshi:in integer range 0 to 4;jian4,jian5:in std_logic;shishi,shige,fenshi,fenge,miaoshi,miaoge:out integer range 0 to 9);end component;component miaobiao is --秒表port(clk_100:in std_logic;moshi:in integer range 0 to 4;jian5,jian4:in std_logic;fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:out integer range 0 to 9);end component;component naozhongset is --闹钟时间设置port(moshi:in integer range 0 to 4;jian4,jian5:in std_logic;shishi,shige,fenshi,fenge,miaoshi,miaoge:out integer range 0 to 9);end component;component naozhongspeaker is --闹钟喇叭输出port(clk_100:in std_logic;shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9;shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:in integer range 0 to 9;speaker:out std_logic);end component;signal moshis:integer range 0 to 4; --信号声明signal shishi1s,shige1s,fenshi1s,fenge1s,miaoshi1s,miaoge1s:integer range 0 to 9;signal shishi2s,shige2s,fenshi2s,fenge2s,miaoshi2s,miaoge2s:integer range 0 to 9;signal shishi3s,shige3s,fenshi3s,fenge3s,miaoshi3s,miaoge3s:integer range 0 to 9;signal fenshis,fenges,miaoshis,miaoges,xmiaoshis,xmiaoges: integer range 0 to 9;signal a0s,a1s,a3s,a4s,a6s,a7s: integer range 0 to 9;signal clk_10000s,clk_100s, clk_1s: std_logic;begin --元件例化u1:paobiao port map(clk_1=>clk_1s,jian8=>jian8,shishi1=>shishi2s,shige1=>shige2s,fenshi1=>fenshi2s,fenge1=>fenge2s,miaoshi 1=>miaoshi2s,miaoge1=>miaoge2s,shishi2=>shishi1s,shige2=>shige1s,fenshi2=>fenshi1s,fenge2=>fenge1s,miaoshi2=>m iaoshi1s,miaoge2=>miaoge1s);u2:xianshi port map(clk_10000=>clk_10000s,jian4=>jian4,moshi=>moshis,a0=>a0s,a1=>a1s,a3=>a3s,a4=>a4s,a6=>a6s,a7=>a7s,sg11=>sg,bt11=>bt);u3:settime port map(moshi=>moshis,jian5=>jian5,jian4=>jian4,shishi=>shishi2s,shige=>shige2s,fenshi=>fenshi2s,fenge=>fenge2s,miaoshi=>miaosh i2s,miaoge=>miaoge2s);u4:moshi port map(jian7=>jian7,moshi=>moshis);u5:mux5_1 port map(moshi=>moshis,shishi1=>shishi1s,shige1=>shige1s,fenshi1=>fenshi1s,fenge1=>fenge1s,miaoshi1=>m iaoshi1s,miaoge1=>miaoge1s,shishi2=>shishi2s,shige2=>shige2s,fenshi2=>fenshi2s,fenge2=>fenge2s,miaoshi2=>m iaoshi2s,miaoge2=>miaoge2s,shishi3=>shishi3s,shige3=>shige3s,fenshi3=>fenshi3s,fenge3=>fenge3s,miaoshi3=>m iaoshi3s,miaoge3=>miaoge3s,fenshi=>fenshis,fenge=>fenges,miaoshi=>miaoshis,miaoge=>miaoges,xmiaoshi=>x miaoshis,xmiaoge=>xmiaoges,a0=>a0s,a1=>a1s,a3=>a3s,a4=>a4s,a6=>a6s,a7=>a7s);u6:miaobiao port map(clk_100=>clk_100s,moshi=>moshis,jian5=>jian5,jian4=>jian4,fenshi=>fenshis,fenge=>fenges,miaoshi=>miaoshis,miaoge=>miaoges,xmiaoshi=>xmiao shis,xmiaoge=>xmiaoges);u7:fenpin port map(clk_10M=>clk_10m,clk_10000=>clk_10000s,clk_100=>clk_100s,clk_1 =>clk_1s);u8:naozhongset port map(moshi=>moshis,jian5=>jian5,jian4=>jian4,shishi=>shishi3s,shige=>shige3s,fenshi=>fenshi3s,fenge=>fenge3s,miaoshi=>mi aoshi3s,miaoge=>miaoge3s);u9:naozhongspeaker port map(clk_100=>clk_100s,speaker=>speaker,shishi1=>shishi3s,shige1=>shige3s,fenshi1=>fenshi3s,fenge1=>fenge3s,miaoshi1=>m iaoshi3s,miaoge1=>miaoge3s,shishi2=>shishi1s,shige2=>shige1s,fenshi2=>fenshi1s,fenge2=>fenge1s,miaoshi2=>m iaoshi1s,miaoge2=>miaoge1s);end;。
