用EDA设计智力抢答器设计一、用EDA设计智力抢答器设计，设计要求：1设计制作一个可容纳四组参赛者的数字智力抢答器，每组设置一个抢答按钮。
2电路具有第一抢答信号鉴别和锁存功能。
3设置记分电路。
二、原理分析：将电路分为三个主要模块：抢答鉴别模块QDJB；计时模块JSQ；记分模块JFQ；译码器显示模块YMQ；元件例化QDQ三、代码：方法1用静态显示，使用4个数码管，两个显示计时，一个显示组别，一个显示分数1抢答鉴别模块QDJBLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY QDJB ISPORT(CLR: IN STD_LOGIC;A, B, C, D: IN STD_LOGIC; --4个组A1,B1,C1,D1: OUT STD_LOGIC;STATES: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END ENTITY QDJB;ARCHITECTURE ART OF QDJB ISsignal a_1,b_1,c_1,d_1:std_logic;BEGINPROCESS(CLR,A,B,C,D) ISBEGINIF CLR='1' THEN STATES<="0000";a_1<='0';b_1<='0';c_1<='0';d_1<='0';--清零elsif a_1='1' or b_1='1' or c_1='1' or d_1='1' then null;--锁存，当有一组选中时其他组再抢答没作用elsif a='1' then a_1<='1';states<="0001";elsif b='1' then b_1<='1';states<="0010";elsif c='1' then c_1<='1';states<="0011";elsif d='1' then d_1<='1';states<="0100";end if;a1<=a_1;b1<=b_1;c1<=c_1;d1<=d_1;END PROCESS;END ARCHITECTURE ART;2计时模块JSQLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY JSQ ISPORT(CLR,LDN,EN,CLK: IN STD_LOGIC;TA,TB:IN STD_LOGIC_vector(3 downto 0);QA:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --ge weiQB:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --shi weiEND ENTITY JSQ;ARCHITECTURE ART OF JSQ ISBEGINPROCESS(CLK) ISVARIABLE TMPA:STD_LOGIC_VECTOR(3 DOWNTO 0);VARIABLE TMPB:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINIF CLR='1' THEN TMPA:="0000"; TMPB:="0110"; --清零，倒计时60秒ELSIF CLK'EVENT AND CLK='1' THENIF LDN='1' THEN TMPA:=tA; TMPB:=tB; --置数控制，如果不想要60可以从TA,TB输入倒计时秒数ELSIF EN='1' THEN--计时开始IF TMPA="0000" THEN--遇到9则自动变为0，否则减一TMPA:="1001";IF TMPB="0000" THEN TMPB:="0110";ELSE TMPB:=TMPB-1;END IF;ELSE TMPA:=TMPA-1;END IF;END IF;END IF;QA<=TMPA; QB<=TMPB;END PROCESS;END ARCHITECTURE ART;3记分模块JFQLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY JFQ ISPORT(RST: IN STD_LOGIC;ADD: IN STD_LOGIC;CHOS: IN STD_LOGIC_VECTOR(3 DOWNTO 0);out1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END ENTITY JFQ ;ARCHITECTURE ART OF JFQ ISBEGINPROCESS(RST,ADD,CHOS) ISVARIABLE POINTS_A0: STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE POINTS_B0: STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE POINTS_C0: STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE POINTS_D0: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINIF (ADD'EVENT AND ADD='1') THENIF RST='1' THENPOINTS_A0:="0000";POINTS_B0:="0000";POINTS_C0:="0000";POINTS_D0:="0000";ELSIF CHOS="0001" THENIF POINTS_A0="1001" THENPOINTS_A0:="0000";ELSEPOINTS_A0:=POINTS_A0+1;END IF;ELSIF CHOS="0010" THENIF POINTS_B0="1001" THENPOINTS_B0:="0000";ELSEPOINTS_B0:=POINTS_B0+1;END IF;ELSIF CHOS="0011" THENIF POINTS_C0="1001" THENPOINTS_C0:="0000";ELSEPOINTS_C0:=POINTS_C0+1;END IF;ELSIF CHOS="0100" THENIF POINTS_D0="1001" THENPOINTS_D0:="0000";ELSEPOINTS_D0:=POINTS_D0+1;END IF;END IF;END IF;if chos="0001" then out1<=POINTS_a0;elsif chos="0010" then out1<=POINTS_b0;elsif chos="0011" then out1<=POINTS_c0;elsif chos="0100" then out1<=POINTS_D0;elsif chos="0000" then out1<="0000";end if;END PROCESS;END ARCHITECTURE ART;4译码器显示模块YMQLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY YMQ ISPORT(AIN4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT7: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END YMQ;ARCHITECTURE ART OF YMQ ISBEGINPROCESS(AIN4)BEGINCASE AIN4 ISWHEN "0000"=>DOUT7<="1111110"; --0WHEN "0001"=>DOUT7<="0110000"; --1WHEN "0010"=>DOUT7<="1101101"; --2WHEN "0011"=>DOUT7<="1111001"; --3WHEN "0100"=>DOUT7<="0110011"; --4WHEN "0101"=>DOUT7<="1011011"; --5WHEN "0110"=>DOUT7<="1011111"; --6WHEN "0111"=>DOUT7<="1110000"; --7WHEN "1000"=>DOUT7<="1111111"; --8WHEN "1001"=>DOUT7<="1111011"; --9WHEN OTHERS=>DOUT7<="0000000";END CASE;END PROCESS;END ARCHITECTURE ART;5元件例化library ieee;use ieee.std_logic_1164.all;USE IEEE.STD_LOGIC_UNSIGNED.ALL;entity qdq isport(qd :in std_logic_vector(3 downto 0);clk,en,ldn,add,rst,clrqd,clrsj :in std_logic;ta,tb : in std_logic_vector(3 downto 0);qdo :out std_logic_vector(3 downto 0);out1 :out std_logic_vector(3 downto 0);out2 :out std_logic_vector(3 downto 0);out4 :out std_logic_vector(3 downto 0);out3 :out std_logic_vector(3 downto 0));end;architecture aa of qdq iscomponent qdjb isPORT(CLR:IN STD_LOGIC;A, B, C, D: IN STD_LOGIC;A1,B1,C1,D1: OUT STD_LOGIC;STATES: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END component QDJB;component jsq isPORT(CLR,LDN,EN,CLK: IN STD_LOGIC;TA,TB:IN STD_LOGIC_vector(3 downto 0);QA:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);QB:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END component JSQ;component ymq isPORT(AIN4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);DOUT7: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));END component YMQ;component jfq isPORT(RST: IN STD_LOGIC;ADD: IN STD_LOGIC;CHOS: IN STD_LOGIC_VECTOR(3 DOWNTO 0);out1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END component JFQ ;signal tmp1,tmp2,tmp3,tmp4 : std_logic_vector(3 downto 0);beginu1: qdjb port map(clr=>clrqd,a=>qd(0),b=>qd(1),c=>qd(2),d=>qd(3),a1=>qdo(0),b1=>qdo(1),c1=>qdo(2),d1=>qdo(3),STATES=>tmp1);u2: jfq port map (rst=>rst,add=>add,chos=>tmp1,out1=>out2);u3: jsq port map(clr=>clrsj,ldn=>ldn,en=>en,clk=>clk,ta=>ta,tb=>tb,qa=>out3,qb=>out4);out1<=tmp1;end;方法2用动态显示library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jfq isport(rst:in std_logic;add:in std_logic;chos:in std_logic_vector(3 downto 0);PP2,PP1,PP0:OUT std_logic_vector(3 downto 0));end entity jfq;architecture art of jfq isSIGNAL aa2,aa1,aa0,bb2,bb1,bb0: std_logic_vector(3 downto 0);SIGNAL cc2,cc1,cc0,dd2,dd1,dd0: std_logic_vector(3 downto 0);beginprocess(rst,add,chos) isvariable points_a2,points_a1:std_logic_vector(3 downto 0);variable points_b2,points_b1:std_logic_vector(3 downto 0);variable points_c2,points_c1:std_logic_vector(3 downto 0);variable points_d2,points_d1:std_logic_vector(3 downto 0);beginIF(ADD'EVENT AND ADD='1') THENIF RST='1'THENPOINTS_A2:="0001";POINTS_A1:="0000"; POINTS_B2:="0001";POINTS_B1:="0000"; POINTS_C2:="0001";POINTS_C1:="0000"; POINTS_D2:="0001";POINTS_D1:="0000"; ELSIF CHOS="0001"THENIF POINTS_A1="1001"THENPOINTS_A1:="0000";IF POINTS_A2="1001"THENPOINTS_A2:="0000";ELSEPOINTS_A2:=POINTS_A2+'1';END IF;ELSEPOINTS_A1:=POINTS_A1+'1';AA2<=points_A2;AA1<= points_A1;AA0<="0000"; PP2<=AA2;PP1<=AA1;PP0<=AA0;END IF;ELSIF CHOS="0010"THENIF POINTS_B1="1001"THENPOINTS_B1:="0000";IF POINTS_B2="1001"THENPOINTS_B2:="0000";ELSEPOINTS_B2:=POINTS_B2+'1';END IF;ELSEPOINTS_B1:=POINTS_B1+'1';BB2<= points_B2;BB1<= points_B1;BB0<="0000"; PP2<=BB2;PP1<=BB1;PP0<=BB0;END IF;ELSIF CHOS="0100"THENIF POINTS_C1="1001"THENPOINTS_C1:="0000";IF POINTS_C2="1001"THENPOINTS_C2:="0000";ELSEPOINTS_C2:=POINTS_C2+'1';CC2<= points_C2;CC1<= points_C1;CC0<="0000"; PP2<=CC2;PP1<=CC1;PP0<=CC0;END IF;ELSEPOINTS_C1:=POINTS_C1+'1';END IF;Elsif chos="1000" thenIf points_D1="1001" thenPoints_D1:="0000";If points_D2="1001" thenPoints_D2:="0000";ElsePoints_D2:=points_D2+'1';End if;ElsePoints_D1:=points_D1+'1';DD2<= points_D2;DD1<= points_D1;DD0<="0000"; PP2<=DD2;PP1<=DD1;PP0<=DD0;End if;End if;End if;End process;End architecture art;Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity jsq isPort(clr,ldn,en,clk:in std_logic;TA,Tb:in std_logic;Qa:out std_logic_vector(3 downto 0);Qb:out std_logic_vector(3 downto 0));End entity jsq;Architecture art of jsq isSignal da: std_logic_vector(3 downto 0);Signal db: std_logic_vector(3 downto 0); BeginProcess(ta,tb,clr) isBeginIf clr='1' thenDa<="0000";db<="0000";elseif ta='1' thenda<=da+'1';end if;if tb='1' thendb<=db+'1';end if;end if;end process;process(clk) isvariable tmpa:std_logic_vector(3 downto 0); variable tmpb:std_logic_vector(3 downto 0); beginif clr='1' then tmpa:="0000";tmpa:="0110"; elsif clk'event and clk='1' thenif ldn='1' then tmpa:=da;tmpb:=db;elsif en='1' thenif tmpa="0000" thentmpa:="1001";if tmpb="0000" then tmpb:="0110"; else tmpb:=tmpb-1;end if;else tmpa:=tmpa-1;end if;end if;end if;qa<=tmpa;qb<=tmpb;end process;end architecture art;library ieee;use ieee.std_logic_1164.all;entity qdjb isport(clr:in std_logic;A,B,C,D:in std_logic;A1,B1,C1,D1:out std_logic;states:out std_logic_vector(3 downto 0)); end entity qdjb;architecture art of qdjb isconstant w1:std_logic_vector:="0001";constant w2:std_logic_vector:="0010";constant w3:std_logic_vector:="0100";constant w4:std_logic_vector:="1000";beginprocess(clr,A,B,C,D) isbeginif clr='1' then states<="0000";elsif (A='1' and B='0' and C='0' and D='0') then A1<='1';B1<='0';C1<='0';D1<='0';states<=w1; elsif (A='0' and B='1' and C='0' and D='0') then A1<='0';B1<='1';C1<='0';D1<='0';states<=w2; elsif (A='0' and B='0' and C='1' and D='0') then A1<='0';B1<='0';C1<='1';D1<='0';states<=w3; elsif (A='0' and B='0' and C='0' and D='1') then A1<='0';B1<='0';C1<='0';D1<='1';states<=w4; end if;end process;end architecture art;library ieee;use ieee.std_logic_1164.all;USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity qdq isport(qd :in std_logic_vector(3 downto 0);ck,clk,en,ldn,add,rst,clr:in std_logic;TA,TB:in std_logic;qdo :out std_logic_vector(3 downto 0);sel:out std_logic_vector(5 downto 0);sm:out std_logic_vector(6 downto 0));end;architecture aa of qdq iscomponent qdjb isPORT(CLR: IN STD_LOGIC;A, B, C, D: IN STD_LOGIC;A1,B1,C1,D1: OUT STD_LOGIC;STATES: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END component QDJB;component jsq isPORT(CLR,LDN,EN,CLK: IN STD_LOGIC;TA,TB:IN STD_LOGIC;QA:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);QB :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END component JSQ;component jfq isPORT(RST: IN STD_LOGIC;ADD: IN STD_LOGIC;CHOS: IN STD_LOGIC_VECTOR(3 DOWNTO 0);pp2,pp1,pp0:inOUT STD_LOGIC_VECTOR(3 DOWNTO 0));END component JFQ ;signal tmp1,tmp2,tmp3: std_logic_vector(3 downto 0); signal pp22,pp11,pp00: std_logic_vector(3 downto 0); signal tmp: integer range 0 to 5;signal q_s:std_logic_vector(3 downto 0);beginu1:qdjb port map(clr,qd(0),qd(1),qd(2),qd(3),qdo(0),qdo(1),qdo(2),qdo(3),tmp1);u2: jfq port map (rst,add,tmp1,pp22,pp11,pp00);u3: jsq port map(clr,ldn,en,clk,ta,tb,tmp2,tmp3); process(ck) isbeginif (ck'event and ck='1') thentmp<=tmp+1;end if;end process;process(tmp) isbeginif tmp=0 then q_s<=tmp1;sel<="000001";elsif tmp=1 then q_s<=tmp2;sel<="000010";elsif tmp=2 then q_s<=tmp3;sel<="000100";elsif tmp=3 then q_s<=pp00;sel<="001000";elsif tmp=4 then q_s<=pp11;sel<="010000";else q_s<=pp22;sel<="100000";end if;end process;process(q_s) isbegincase q_s iswhen"0000"=>sm<="0111111";when"0001"=>sm<="0000110";when"0010"=>sm<="1011011";when"0011"=>sm<="1001111";when"0100"=>sm<="1100110";when"0101"=>sm<="1101101";when"0110"=>sm<="1111101";when"0111"=>sm<= "0000111"; when"1000"=>sm<="1111111"; when"1001"=>sm<="1101111";when others=>sm<="0000000";end case;end process;end;。
