1/2-inch CMOS Digital Image Sensor BG0605D Datasheet
General Descriptions
BG0605D is a high performance ? inch CMOS digital image sensor with an active-pixel array 768H x 582V. This chip features breakthrough high sensitivity and high dynamic range 8.6um x 8.3um pixels. It is programmable through a simple two-wire serial interface.
Features
●High sensitivity and high dynamic range
pixel.
●Programmable controls: gain, frame rate,
frame size, exposure.
●Superior low light performance.
●Enhanced NIR performance.
●Auto black level calibration.
●Maximum 50 frame per sec.
Applications
●High-end surveillance
●Industrial vision Key Parameter
Table 1 Key Specification Parameter Typical Value Optical format 1/2 inch
Active pixel array 768H x 582V Pixel size
8.60um(H) x
8.30um(V) Active pixel array Area
6604.8 um x
4830.6 um Frame rate 50fps@full frame Color filter array Bayer RGB Shutter Type Electronic Rolling Responsivity@550nm 13.6V/lux-sec SNR 48db
Dynamic range 69db
Output 10-bit
Power
supply
Digital Internal 1.8V
IO 3.0V ~3.45V
Analog 3.15V ~3.45V Power Consumption 270mW@50fps Package Option 48 pin CLCC
In the absence of confirmation by device specification sheets, BRIGA TES takes no responsibility for any defects that may occur in equipment using any BRIGAGES device shown in catalogs, data book, etc. Contact BRIGA TES in order to obtain the latest device specification before using any BRIGA TES device.
Table of Content
General Descriptions (1)
Features (1)
Applications (1)
Key Parameter (1)
Top-level Description (5)
Block-level Description (8)
Image Sensor Array (8)
I2C Master Interface (8)
I2C Slave Interface (9)
Digital Image Processing (10)
Initial Loader (10)
Pin Outs (11)
Output Timing (13)
Chip Control (14)
Gain (14)
Frame Time (14)
Exposure (14)
Window Control (15)
Vertical Blanking Control (15)
Mirror (15)
Restart (15)
PLL (15)
Register Description (16)
Chip Characteristics (19)
Spectral Responsivity (19)
I/O Timing (19)
Electrical Specifications (20)
Maximum Ratings (21)
Power-up Sequence (21)
Mechanical Drawing (22)
Revision History (23)
List of Figures
Figure 1 Block Diagram (6)
Figure 2 Typical Connection Diagram (7)
Figure 3 Pixel Array Read Out (8)
Figure 4 Color Filter Arrangements (8)
Figure 5 I2C Slave Write Operation (9)
Figure 6 I2C Slave Read Operation (9)
Figure 7 48-Pin PLCC Pinout Diagram (11)
Figure 8 Output Timing Diagram (13)
Figure 9 Analog Processing and AD Conversion (14)
Figure 10 Readout of 8 rows in Normal and Row Mirror Readout Mode (15)
Figure 12 Spectral Responsivity (19)
Figure 13 I/O Timing Diagram (19)
Figure 14 Power-up Sequence (21)
Figure 15 Package and Mechanical Drawing (22)
List of Tables
Table 1 Key Specification (1)
Table 2 IO Description (11)
Table 3 Register Definition Table (16)
Table 4 IO Timing (20)
Table 5 Electrical Specification (20)
Table 6 Maximum Ratings (21)
Top-level Description
BG0605D is a progressive-scan image sensor with 768x582 active pixels array which
generates a stream of pixel data at a maximum frame rate of 50 fps. Frame size,
exposure, gain and other parameters are programmable through I2C interface. Figure
1 shows the function diagram of BG0605D.
The timing and control circuitry sequences through the rows of array, resetting and
then reading each row in turn. Once the pixel data of a row is put onto bit-line, analog
processing (providing CDS and gain) and A/D conversion is performed in column
parallel way. The output from the ADC is a 10-bit value for each pixel and then is
passed to digital data path.
Digital image processing unit provides row wise noise canceling and black level
correction. Besides, digital gain is performed in this part. After these, image will output
in parallel way along with FRMAE_VALID, LINE_VALID and synchronized pixel clock.
I2C interfaces are utilized in this chip. I2C master should be connected to the off-chip
EEPROM to load the initial setting. And I2C slave interface is used to get access to the
internal register file. The register file controls the array, analog signal and digital signal
chain .Typical connection diagram is shown in Figure 2.
Active Pixel Array
Analog Processing and A/D Conversion
G R B
G
Datapath
Array&Analog path Parallel Output
EESDA EESCL
Digital Image Processing
Timing and Control
SDA_S SCL_S
INIT Loader
Register File I2C Master I2C Slave
Figure 1 Block Diagram
BG0605
EESDA EESCL
EEPROM
LINE_VALID
nRst
VDDPIX
VDDA VDDO VDD VDDPLL VDDA3V3VDD3V3VDD1P8PLL3V3
VTH VCM_AMP
GND
GND
VSSPIX
DGND
GNDPLL
GND GND GND GND
D[0-9]
FRAME_VALID
PIXCLK SDA_S SCL_S
Host
GND
Figure 2 Typical Connection Diagram
Block-level Description
Image Sensor Array
The image sensor array contains 768 x 582 active pixels. Besides, 6 dark rows and 36 dark columns can be read out for special purpose as Figure 3. BG0605D employs primary color filter of RGB (red, green and blue), the color filter arrangement (top right corner of pixel array) is show in Figure 4.
768x582Active Pixel
6 dark rows
36 dark columns
Acitve (0,0) point
Figure 3 Pixel Array Read Out
R G B G R G B G R G B G G R B G R G B
G
G R B G R G B
G
G R B G R G B
G
BLACK PIXELS
B L A
C K P I X E L S
(0,0) point
Figure 4 Color Filter Arrangements
I2C Master Interface
BG0605D utilizes I2C master interface to load initial settings from off-chip EEPROM. It will read the off-chip EEPROM at the power up phrase. Maximum support EEPROM is 16K size.
I2C Slave Interface
BG0605D is programmable through I2C interface with reading slave device address
0x65 and writing slave device address 0x64. The related IO pin is MCCDSCL and
MCCDSDA. MCCDSCL works as the serial clock and MCCD as the data line.
Figure 5 shows example of the write operation (Writing 0x2C register with 0x56 data).
The sequence is defined as following:
●The master sends a start bit to the slave.
●The master sends the slave device address with write mode.
●The slave sends an acknowledge bit to the master to indicate receive its slave
device address.
●The master sends 8-bit register address to the slave.
●The slave sends an acknowledge bit after it receives the 8-bit data.
●The master sends 8-bit register data to the salve.
●The slave sends an acknowledge bit after it receives the 8-bit data
●The master sends a stop bit to the slave.
SCL
SDA
START 0x64 ADDR
ACK
0x2C REG
ACK
0x56 DATA
ACK STOP Figure 5 I2C Slave Write Operation
Figure 6 shows example of the read operation (Writing 0x56 data from 0x2C register).
The sequence is defined as following:
●The master sends a start bit to the slave.
●The master sends the slave device address with write mode.
●The slave sends an acknowledge bit to the master.
●The master sends 8-bit register address to the slave.
●The slave sends an acknowledge bit to the master.
●The master sends a start bit to the slave.
●The master sends the slave device address with read mode.
●The slave sends an acknowledge bit to the master.
●The slave sends 8-bit data to the master
●The master sends a no-acknowledge bit to the slave.
●The master sends a stop bit to the slave to stopping read.
SCL
SDA
START 0x64 ADDR
ACK
0x2C REG
ACK
0x65 DATA
ACK
0x56 DATA
ACK STOP
Figure 6 I2C Slave Read Operation
Digital Image Processing
Digital Image processing unit provides row wise noise canceling and BLCC.
●Row wise noise correction:
Row wise noise is handled automatically by the image sensor. Row wise noise
correction unit measures a set of optical black pixels at the start of each line and
then apply the average to the tied active pixels of the line.
●BLC:
Black level correction is handled automatically by the image sensor. By measures
the average value of pixels from a set of optical black lines in the image sensor, it
reduce the circuit offset to an acceptable level.
Initial Loader
BG0605D use an initial loader to load the necessary setting at the power up phrase.
The necessary setting is stored in the off chip EEPROM connected to the I2C master.
Pin Outs
30
2928272625242322212019
18
1716151413121110987313233343536373839404142
434445464748123456VCM_AMP
GND
GND
VDDA
DGND
D7
D6
D5
VDD
D4
D3
D2
GNDPLL
DGND CLKIN VDD D0D1PIXCLK
FRAMEVALID
LINEVALID Reserved VDDO VTH VDDAPLL
Reserved
Reserved
Reserved
Reserved
Reserved
DGND
Reserved
Reserved
Reserved
Reserved
VDDO
VDDO VDDA GND VSSPIX VDDPIX nRST SDA_S SCL_S EESDA EESCL D9D8
Figure 7 48-Pin PLCC Pinout Diagram
Table 2 IO Description
PIN NO.
NAME I/O TYPE DESCRIPTION
1 DGND - P Digital Ground
2 Reserved I D Connect to ground
3 Reserved I D Connect to ground
4 Reserved I D Connect to ground 5
Reserved
I
D
Connect to ground
6 VDDO - P I/O Power
7 D8 O D Pixel Data Out Bit8
8 D9 O D Pixel Data Out Bit9
9 EESCL I/O D Master Serial Bus Clock.
10 EESDA I/O D Master Serial Bus Data.
11 SCL_S I/O D Slave Serial Bus Clock
12 SDA_S I/O D Slave Serial Bus Data
13 nRST - A Power On Reset
14 VDDPIX - P Pixel Array Power
15 VSSPIX - P Pixel Array Ground
16 VSSA - P Analog Ground
17 VDDA - P Analog Power
18 VDDO - P I/O Power
19 D2 O D Pixel Data Out Bit2
20 D3 O D Pixel Data Out Bit3
21 D4 O D Pixel Data Out Bit4
22 VDD - P Digital Core Power
23 D5 O Out Pixel Data Out Bit5
24 D6 O Out Pixel Data Out Bit6
25 D7 O Out Pixel Data Out Bit7
26 DGND - P Digital Ground
27 VDDA - P Analog Power
28 VSSA - P Analog Ground
29 VSSA - P Analog Ground
30 VCM_AMP - A Analog Bias
31 VTH - A Charge Pump Out
32 VDDO - P I/O Power
33 Reserved O D NC
34 LINEVALID I/O D Line valid
35 FRAMEVALID I/O D Frame valid
36 PIXCLK O D Pixel clock
37 D1 O D Pixel Data Out Bit1
38 D0 O D Pixel Data Out Bit0
39 VDD - P Digital Core Power
40 CLKIN I D Clock Input.
41 DGND - P Digital Core Ground
42 VSSPLL - P PLL Ground
43 VDDPLL - P PLL Power
44 Reserved I D Connect to ground
45 Reserved I D Connect to ground
46 Reserved I D Connect to 3.3V
47 Reserved I D Connect to ground
48 Reserved I D Connect to ground
Output Timing
The BG0605D images are read out in progressive scan mode, which are divided into
frames and further divided into lines. By default, the sensor produces 752H*582V
pixels. The FRAME_VALID and LINE_VALID signal indicates the boundaries between
and lines. PIXCLK can be used as a clock to latch the data.
PIXCLK
FRAME_VALID
LINE_VALID
D0D1D2D3D4D5D6DN
DOUT[0:9]
Figure 8 Output Timing Diagram
Chip Control
Gain
BG0605D has three stages of gain, including PGA gain, AD Ramp gain and Digital
gain.
(Separate R,G,B channel gain are not available)
PGA AD Digital gain
Bitline
Figure 9 Analog Processing and AD Conversion
●PGA Gain:
BG0605D has a column parallel architecture and it has an analog gain stage per
column. PGA gain can be controlled by register C s and C f (0xb4, 0xb5 on page 00).
The PGA Gain is determined by:
Gain pga = C s / C f
The maximum PGA gain is 16x.
●Ramp Gain:
Ramp Gain controls the slope of AD ramp. It's control by register 0xb6 on Page
00.
●Digital Gain:
Digital gain can be controlled by register 0xb7 and 0xb8 on page 00. The format
for digital gain setting is xxxx_xxxx.yyyy_yyyy where 16'h0100 represents a 1x
gain.
Frame Time
In case of integration time is less than vertical size plus vertical blanking value, frame
time is decided by the sum of vertical size and vertical blanking. Otherwise, frame time
is decided by the integration time.
Exposure
Integration time is controlled by TEXP register, which use T row as time unit. Typically,
the value of the TEXP register is limited to the number of line per frame
(VBLANK+VSIZE), such that the frame rate is not affected by the integration time.
After write TEXP register, use RESTART register to make an update.
Window Control
HSTART, HSIZE, VSTART, VSIZE control the starting coordinates and size of the image window.
Vertical Blanking Control
Vertical blank time is controlled by the VBLANK registers, which is calculated in terms of ROW_TIME.
Mirror
BG0605D supports row mirror process. By setting READC = 1, the readout order of the rows is reversed as shown in Figure 10.
Normal readout Dout[9:0]Row0[9:0]
Row1[9:0]
Row2[9:0]
Row3[9:0]
Reversed readout
Dout[9:0]
Row5[9:0]Row4[9:0]Row3[9:0]Row2[9:0]Row5[9:0]
Row0[9:0]
Row4[9:0]
Row1[9:0]FV
Figure 10 Readout of 8 rows in Normal and Row Mirror Readout Mode
Restart
To restart BG0605D at any time during the operation of the sensor, write a "1" to the RESTART register. The sensor will stop the current frame immediately and a new frame starts.
PLL
The BG0605D has an internal PLL, which can generate PLL clock (f out ) 100MHz~250MHz.
The PLL is controlled through its PLM, PLN and PLK parameters. The PLL output frequency (f out ) has the following relationship to the input frequency (f xclk ): f out = f xclk *(PLM+2)/( (PLN[5:0]+2)*PLLK)
Note:
1) PLM=0~127; 2) PLN=0~63;
3) PLK[1:0]=2’b00: PL LK=2 PLK[1:0]=2’b01: PLLK=4 PLK[1:0]=2’b10: PLLK=8 PLK[1:0]=2’b11: PLLK=16
The input clock should be 14.1M and the Default frequency is 91M with PLM=63
PLN=3 and PLLK=2.
The PLL takes time to power up. During this time, the behavior of its output clock is not
guaranteed.
The PLL can be bypassed manually. When the PLL has been bypassed, the input
clock will be set as the main clock.
Register Description
BG0605D has three banks of control registers, which is controlled by register 0xf0.
Each 8-bit address accesses an 8-bit storage space. Some register may take more
than one consecutive addresses, which means these contents of consecutive
addresses form the value of the register together.
BG0605D is programmable through I2C interface with reading slave device address
0x65 and writing slave device address 0x64.
Table 3 Register Definition Table
Bank 0
Name Width Address
(hex)
Description Default
ID [15:0] 8'h00 Chip ID 16'h0601 HSTART [9:0] 8'h02 The first column to be read out 10'h026
VSTART [9:0] 8'h04 The first row to be read out, affected by READC:
1). When READC = 0, the read out circuit read
from VSTART to VSTART+VSIZE-1;
2).When READC = 1, the read out circuit read
from VSTRT+VSIZE-1 to VSTART.
10'h00e
HSIZE [9:0] 8'h06 The window width size. 10'h2f0 VSIZE [9:0] 8'h08 The window height size. 10'h246 TEXP [15:0] 8'h0c The exposure time in rowtime unit 16'h0032 ROWTIME [15:0] 8'h0e Half of CCD ROWTIME in clkin period uint: 16'h01c6
RESTART [1:0] 8'h1d Start a new session or update all registers
Bit1: assert this bit will updates all registers.
Bit0: assert this bit will start a new session.(CIS
mode only)
2’b0
VBLANK [15:0] 8'h21 Vertical blank, in terms of row time(CIS MODE
only)
16'h0020
PLLCTRL [5:0] 8'h50 Pll control:
Bit[5]: pllock(read only)
Bit[4]: pdmck
Bit[3]: plnpyp
Bit[2]: pllock_sel:
1 for plllock, 0 for pllcntr associated with
PLLOCKTIME.
Bit[1]: pllpd
Bit[0]: pllbyp
5’b00100
PLLOCKTI
ME [7:0] 8'h51 When PLLCTRL[2]=0, pllcnter 's threshold = {plltime,14'h000} 8’h02
PLLCOMC [6:0] 8'h52 PLL common control;
Bit[6:5] plcc:
Bit[4:2] pllr:
Bit[1:0] plk:
7’b01_000_
00
PLM [6:0] 8'h53 plm 8’h3f PLN [5:0] 8'h54 pln 6’h3
PCLK_CTR
L [5:0] 8’h88Bit[5:3] clk_dly
Bit[2:0] pclk_dly
6’b100_010
DV_DOUT [2:0] 8’h8c Drive of dout 3’b011 OEN_CTRL [3:0] 8'h8d Oen control of hsync, vsync and pclk, write 0x08 to
enable output.
4'b1101
OEN_DOU
T [1:0] 8'h8e Bit1: oen dout[4:0]
Bit2: oen dout[9:5] 2'b11
RAMP_VOL
_A
[17:0] 8’hae ramp gain=RAMP_VOL_A/(code + RAMP_VOL_B) 17’h01400 RAMP_VOL
_B
[17:0] 8’hb1ramp gain=RAMP_VOL_A/(code + RAMP_VOL_B) 17’h04000 CS_SEL_M
AN [3:0] 8’hb4fixed cs value when gain mapping mode is MANUAL 4’h7
CF_SEL_M
AN
[3:0] 8’hb5fixed cf value when gain mapping mode is MANUAL 4’h7
RAMP_SEL
_MAN [6:0] 8’hb6fixed ramp code when gain mapping mode is MANUAL 7’h7f
DIG_GAIN
_SEL_MAN [15:0] 8’hb7fixed digital gain when gain mapping mode is
MANUAL 16’h0100
GAIN_MAP
PING_MAN _MODE [0:0] 8’hb9
gain mapping mode selection. 1—MANUAL,
0—AUTO 1’b0
REG_PAGE [0:0] 8’hf0register page 1’b0
Bank 01
FD [4:0] 8’hc8Bit[4]:ss1 selection.
Bit[3]:enable indoor mode’s configuration by user.
Bit[2]:auto flag,1 for auto fd selection,0 for
manual fd selsection.
Bit[1:0]:manual fd value,10 for high conversion
gain,11 for middle conversion gain,01 for low conversion gain.
5’h05
FDOUT [1:0] 8’hc9Fd out value, read only
L_AVE [10:0] 8’hca Averge light value in log, read only
FD_TH0 [13:0] 8’hcf Bit[13:12]:fd selectin when
l_ave<=FD_TH0[10:0].
Bit[11]:reserved.
Bit[10:0]:fd threshold, 6bits integer, 5bits fractional.
14’h2320
FD_TH1 [13:0] 8’hd1Bit[13:12]:fd selectin when FD_TH1[10:0] =<
l_ave <= FD_TH2[10:0].
Bit[11]:reserved.
Bit[10:0]:fd threshold, 6bits integer, 5bits fractional.
14’h3360
FD_TH2 [10:0] 8’hd3Fd threshold, 6bits integer, 5bits fractional. 11’h4c0
FD_TH3 [13:0] 8’hd5Bit[13:12]:fd selectin when
l_ave>=FD_TH3[10:0].
Bit[11]:reserved.
Bit[10:0]:fd threshold, 6bits integer, 5bits fractional.
14’h1500
FRM_STAT
IC_NUM
[15:0] 8’hd7Every N frame to get an average light 16’h0708
POST_PRO
C_CTRL [2:0] 8'hf1 Post process control.
Bit2: post process enable
Bit1: lpf enable
Bit0: dpc enable
3'h7
DPC_HIGH_
MARGIN
[7:0] 8'hf2 dpc low margin 8'ha DPC_LOW_M
ARGIN
[7:0] 8'hf3 dpc high margin 8'ha DENOISE_TH
R_H [2:0] 8'hf4 denoise th high 8'h0 DENOISE_TH
R_L
[7:0] 8'hf5 denoise th low 8'h0
Chip Characteristics
Spectral Responsivity
Figure 11 Spectral Responsivity
I/O Timing
T CLKIN
t DH
t DS
t PFH t PLH
t PFL t PLL
t R
t F
t RP
t FP
CLKIN
PIXCLK
DATA[9:0]
FRAME_VALID LINE_VALID
DATA_1DATA_2
DATA_3
DATA_4
DATA_5
DATA_6
Figure 12 I/O Timing Diagram
400
450500
550600650700
00.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Wave Length (nm)
R e l a t i v e R e s p o n s e
B G2R G1
Table 4 IO Timing
Symbol Definition Min Typ Max Unit
f CLKIN Input clock frequency 70 ns
t R Input clock rise time 3 ns
t F Input clock fall time 3 ns
t RP PIXCLK rise time 2 ns
t FP PIXCLK fall time 2 ns
f PIXCLK Frequency of PIXCLK 22 ns
T DS DATA SETUP time 8 ns
T DH DATA HOLD time 8 ns
t PFH PIXCLK to FV HIGH 0 ns
t PFL PIXCLK to FV LOW 0 ns
t PLH PIXCLK to LV HIGH 0 ns
t PLL PIXCLK TO LV LOW 0 ns
C LOA
D Output load capacitance - <1.5 - pF
C IN Input pin capacitance - - pF Electrical Specifications
Table 5 Electrical Specification
Symbol Definition Condition Min Typ Max Unit Note V DD-A VDDA voltage 3.15 3.3 3.45 V
V DD-D VDD voltage 1.7 1.8 1.9 V
V DD-IO VDDO voltage 3.0 3.3 3.6 V
V IH Input Voltage High
0.7
*V DD-IO
V
V IL Input Voltage Low
0.3
*V DD-I
O
V
I IN Input Leakage
Current
No pull-up
resistor ,VIN=V DD
-IO
or DGND
-1 1 μA
V OH Output High Voltage
0.9
*V DD-IO
V
V OL Output Low Voltage
0.1*V
DD-IO
V I OH Output Current High V OH=0.9*V DD-IO -7 mA I OL Output Current Low V OH=0.1*V DD-IO -7 mA
I DD-A Analog Operating
Current
f PCLK=14.1 MHz
Default setting
70mA
I DD-D Digital Operating
Current
f PCLK=14.1 MHz
Default setting
31 mA
I DD-IO IO Operating Current f PCLK=14.1 MHz
Default setting
1.5 mA