DESCRIPTION
The M5M51016BTP, RT are a 1048576-bit CMOS static RAM
organized as 65536 word by 16-bit which are fabricated using high-performance triple polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery result in a high density and low power static RAM.
They are low stand-by current and low operation current and ideal for the battery back-up application.
The M5M51016BTP,RT are packaged in a 44-pin thin small outline package which is a high reliability and high density surface mount device (SMD). Two types of devices are available.M5M51016BTP(normal lead bend type package), M5M51016BRT (reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board.
FEATURES
1 & BC
2 M5M51016BTP,RT APPLICATION
Small capacity memory units
44pin 400mil TSOP(II)
..............................
CS BC 1BC 2W OE Mode
Non selection DQ 1~8DQ 9~16Stand-by High-Z I CC L X X X X High-Z Non selection Stand-by
High-Z X H H X X High-Z Upper-Byte Write Active High-Z
H H L L X Din Upper-Byte Read Active High-Z H H L H L Dout Active High-Z H H L H H High-Z Active Din H L H L X High-Z Active
Dout H L H H L High-Z Lower-Byte Write Lower-Byte Read Active High-Z H
L H H High-Z H Active
H L L X L Din Din Word Write Active
H L H L L Dout Dout Word Read Active High-Z H
L H H High-Z L The operation mode of the M5M51016B series are determined by a combination of the device control inputs BC 1, BC 2, CS, W and OE. Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with the low level BC 1 and/or BC 2 and the high level CS. The address must be set up before the write cycle and must be stable during the entire cycle.
12or CS, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input level, the output stage is in a high-impedance state, and the databus contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a low level while BC 1 and/or BC 2 and CS are in an active state.12=L,CS=H)
When setting BC 1 at a high level and the other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enabled, and lower-Byte are in a non-selectable mode.And when setting BC 2 at a high level and the other pins are in an active state, lower-Byte are in a selectable mode and upper -Byte are in a non-selectable mode.
When setting BC 1 and BC 2 at a high level or CS at a low level,the chips are in a non-selectable mode in which both reading and writing are disabled.
In this mode, the output stage is in a high-impedance state,allowing OR-tie with other chips and memory expansion by BC 1,BC 2 and CS. The power supply current is reduced as low as the stand-by current which is specified as I CC3 or I CC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during powerfailure or power-down operation in the non-selected mode.
FUNCTION
(High-Z=High-impedance)
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE Symbol Parameter
Test conditions
pF pF
Unit Max 68
Typ
Min
Limits V I =GND, V I =25mVrms, f=1MHz V O =GND,V O =25mVrms, f=1MHz
Input capacitance ( except BC 1,BC 2) Output capacitance
C I C O
Parameter
Supply voltage Input voltage Output voltage Power dissipation
Operating temperature Storage temperature
Unit V V V
W Conditions
With respect to GND Ta=2510 ~ 70– 65 ~ 150
Ratings Symbol Vcc V I V O P d T opr T stg
DC ELECTRICAL CHARACTERISTICS (Ta=0 ~70
, Vcc=2.7V ~ 3.6V, unless otherwise noted)– 0.3 ~ 4.6
(Ta=0 ~ 70 , Vcc=2.7V ~ 3.6V, unless otherwise noted)
0 ~ Vcc * –3.0V in case of AC ( Pulse width 50ns )
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc = 3.3V, Ta = 25pF 9V I =GND, V I =25mVrms, f=1MHz Input capacitance ( BC 1,BC 2 )C IBC
V IH
V IL V OH1Symbol Parameter
V V V Max
Vcc+0.3V
0.6
Typ
Limits Min 2.0– 0.3*
2.4
Test conditions
Unit High-level input voltage Low-level input voltage High-level output voltage 1CC3V OL I I I CC1W I V μA μA 0.4Low-level output voltage Input current
Output current in off-state I O 0.33
Stand-by current
mA
* –3.0V in case of AC ( Pulse width 30ns )
mA 55Stand-by current 60-VL -VLL
12I OH = – 1mA I OH = – 0.1mA I OL = 2mA V I =0 ~ Vcc
BC 1 and BC 2 = V IH or CS = V IL or OE = V IH , V I/O = 0 ~ Vcc
1BC 1 and BC 2 = V IL , CS = V IH other inputs = V IH or V IL Output-open(duty 100%)Min cycle 1MHz mA 12V OH2High-level output voltage 2CC4
I Vcc–0.5V
V I CC1B mA Min cycle 1MHz
mA Active supply current (AC,TTL level)Word operation (16bit)Active supply current (AC,TTL level)
Byte operation (8bit)(BC 1 = V IH and BC 2 = V IL )
or (BC 1 = V IL and BC 2 = V IH ),CS = V IH
other inputs = V IH or V IL Output-open(duty 100%)
1035I CC2W I CC2B
<– 0.3* ~ Vcc + 0.3
C
o C
o
C o
C o
+_ 1+_2) BC 1,BC 2 Vcc - 0.2V,other inputs = 0~Vcc
BC 1 and BC 2 = V IH or CS = V IL ,other inputs = 0~Vcc
1) CS 0.2V, other inputs = 0~Vcc
CS Vcc - 0.2V <>>μA μA C o
C
o
<
(2) READ CYCLE
(3) WRITE CYCLE
Symbol Parameter
t CR Read cycle time
Address access time
Unit ns ns ns ns ns ns ns ns ns ns ns ns t CW t w(W)t su(A)t en(OE)
t su(BC1)t su(BC2 )t su(CS)t su(D)t h(D)t rec(W)t dis(W)t dis(OE)t en(W)Symbol Parameter Write cycle time Write pulse width Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Max Typ Min Max Typ Min Limits
t a(BC1)t a(BC2)t a(CS)t a(OE)t dis(BC1)t dis(BC2)t dis(CS)t dis(OE)t en(BC1)t en(BC2)t a(A)Limits t en(CS)t en(OE)ns ns t su(A-WH)ns
t v(A)
120
Address set up time
0Address set up time with respect to W 10085Data set up time 45Data hold time
0Byte control 1 setup time 100Chip select set up time 1005Byte control 2 setup time 100Write recovery time
Output enable time from W high 5
Output enable time from OE low
Output disable time from W low Output disable time from OE high Output enable access time
Output disable time after CS low 120
Byte control 1 access time Chip select access time Output enable time after CS high Data valid time after address
Byte control 2 access time Output disable time after BC 1 high Output disable time after BC 2 high Output disable time after OE high Output enable time after BC 1 low Output enable time after BC 2 low Output enable time after OE low 6040120
1201201010
120404040
1010540
40AC ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70 , V
CC = 2.7V ~ 3.6V, unless otherwise noted )(1) MEASUREMENT CONDITIONS
Input pulse level Input rise and fall time Reference level Transition is measured 500mV from steady
state voltage. ( for t en , t dis )
Output loads Fig.1 Output load
C L ( Including scope
and JIG )
DQ
V IH = 2.2V, V IL = 0.4V 5ns
V OH = 1.5V, V OL = 1.5V Fig.1,C L = 30pF
C L = 5pF ( for t en , t dis )
........................................................................................ns
M5M51016B -12VL,-12VLL M5M51016B -12VL,-12VLL
C o
+_
Read cycle
Write cycle (W control mode)
(4) TIMING DIAGRAMS DQ 1~16
BC 1 and/or BC 2
CS
OE
W
A 0~15
DQ 1~16
BC 1 and/or BC 2
CS
OE
A 0~15
Write cycle ( BC control mode)
Note 3: Hatching indicates the state is "don't care".
4: Writing is executed while CS high overlaps BC 1 and/or BC 2 low and W low.
6: Don't apply inverted phase signal externally when DQ pin is output mode.
Write cycle (CS control mode)
5: When the falling edge of W is simultaneously or prior to the falling edge of BC 1 and/or BC 2 or rising edge of CS, the outputs are maintained in the high impedance state.
DQ 1~16
12
CS
W
A 0~15
DQ 1~16
BC 1 and/or BC 2
CS
W
A 0~15
(Ta = 0 ~ 70 , unless otherwise noted)
Symbol Parameter
V V
Max
Typ
Limits Min Test conditions
Unit μA
V
(3) POWER DOWN CHARACTERISTICS BC control mode
CS control mode
POWER DOWN CHARACTERISTICS
2(1) ELECTRICAL CHARACTERISTICS 50
2.0
0.60.2-VLL
-VL (Note 7)
0.3
10
Power down set up time Power down recovery time
(2) TIMING REQUIREMENTS (Ta = 0 ~ 70 , unless otherwise noted )V CC (PD)V I (BC)V I (CS)
I CC (PD)Power down supply voltage Byte control input BC 1 & BC 2Chip select input CS
Power down supply current
2.7V V
CC(PD)V CC(PD) 2.7V V CC = 3V
t su (PD)t rec (PD)
Symbol Parameter
ns Max
Typ
Limits Min Test conditions
Unit 05
ms
V CC
BC 1 & BC 2
V CC
CS C
o
<<
1) CS 0.2V
CS V
CC 0.2V,other inputs=0~3V 2) BC 1 & BC 2 Vcc 0.2V,other inputs = 0 ~ 3V
>> o C o CS 0.2V <
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