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IDT70T3519S-200DRI中文资料

APRIL 2004

–Data input, address, byte enable and control registers –Self-timed write allows fast cycle time

◆

Separate byte controls for multiplexed bus and bus matching compatibility

◆Dual Cycle Deselect (DCD) for Pipelined Output Mode ◆ 2.5V (±100mV) power supply for core

◆

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on each port

◆

Industrial temperature range (-40°C to +85°C) is available at 166MHz and 133MHz

◆

Available in a 256-pin Ball Grid Array (BGA), a 208-pin Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball Grid Array (fpBGA)

◆Supports JTAG features compliant with IEEE 1149.1

◆

Due to limited pin count JTAG is not supported on the 208-pin PQFP package

HIGH-SPEED 2.5V 256/128/64K x 36

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

IDT70T3519/99/89S 5666drw 01

ZZ R

(2)

Features:

◆True Dual-Port memory cells which allow simultaneous access of the same memory location ◆

High-speed data access

–Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

–Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)◆Selectable Pipelined or Flow-Through output mode ◆Counter enable and repeat features

◆

Dual chip enables allow for depth expansion without additional logic

◆Interrupt and Collision Detection Flags ◆

Full synchronous operation on both ports

–5ns cycle time, 200MHz operation (14Gbps bandwidth)–Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200MHz

1.Address A 17 is a NC for the IDT70T3599. Also, Addresses A 17 and A 16 are NC's for the IDT70T3589.

2.The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FT x and OPTx NOTES:

Description:

The IDT70T3519/99/89 is a high-speed 256/128/64K x 36 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory c ells t o a llow s imultaneous a ccess o f a ny a ddress f rom b oth p orts. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70T3519/99/89 has been optimized for applications having unidirec-tional o r b idirectional d ata f low i n b ursts. A n a utomatic p ower d own f eature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.

The 70T3519/99/89 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (V DD) is at 2.5V.

Pin Configuration (3,4,5,6,9)

NOTES:

1.Pin is a NC for IDT70T3599 and IDT70T3589.

2.Pin is a NC for IDT70T3589.

3.All V DD pins must be connected to 2.5V power supply.

4.All V DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DD (2.5V), and 2.5V if OPT pin for that port is

set to V SS (0V).

5.All V SS pins must be connected to ground supply.

6.Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

7.This package code is used to reference the package diagram.

8.This text does not indicate orientation of the actual part-marking.

9.Pins A15 and T15 will be V REFL and V REFR respectively for future HSTL device.

70T3519/99/89BC

BC-256(7)

256-Pin BGA Top View (8)

E16

I/O 14R

D16

I/O 16R

C16

I/O 16L

B16

A16

A15

B15

I/O 17L

C15

I/O 17R D15

I/O 15L E15

I/O 14L E14

I/O 13L D14

I/O 15R D13

V DD C12

A 6L

C14

OPT L B14

V DD

A14

A 0L

A12

A 5L

B12

A 4L

C11

ADS L

D12

V DDQR D11

V DDQR C10

CLK L B11

REPEAT L

A11

CNTEN L

V DDQR C8

BE 1L

CE 1L

V DDQL C9

BE 0L B9

CE 0L D10

V DDQL C7

A 7L

BE 3L

BE 2L

B13

A 1L

A13

A 2L

A10

OE L D7

V DDQR B7

A 9L

A 8L

A 12L

A 10L

V DDQL A5

A 14L

A 15L

A 13L

V DDQL A4

PIPE/FT L A3

TDO

V SS D3

I/O 20L D2

I/O 19R C2

I/O 19L

TDI

I/O 18L

I/O 18R D1

I/O 20R E1

I/O 21R E2

I/O 21L E3

I/O 22L E4

V DDQL

I/O 23L F2

I/O 22R F3

I/O 23R F4

V DDQL

I/O 24R G2

I/O 24L G3

I/O 25L G4

V DDQR

I/O 26L H2

I/O 25R H3

I/O 26R H4

V DDQR

I/O 27L J2

I/O 28R J3

I/O 27R J4

V DDQL

I/O 29R K2

I/O 29L K3

I/O 28L K4

V DDQL

I/O 30L L2

I/O 31R

I/O 30R L4

V DDQR M1

I/O 32R M2

I/O 32L M3

I/O 31L M4

V DDQR

I/O 33L N2

I/O 34R N3

I/O 33R N4

PIPE/FT R P1

I/O 35R P2

I/O 34L

TMS P4

I/O 35L

TRST

NC T2

TCK T3

NC T4

A 13R

A 15R

P12

A 6R

BE 1R P9

BE 0R R8

BE 3R T8

BE 2R P10

CLK R T11

CNTEN R P11

ADS R

R12

A 4R

T12

A 5R P13

A 3R

A 7R

R13

A 1R

T13

A 2R R6

A 12R

A 14R T14

A 0R R14

OPT R

P14

I/O 0L P15

I/O 0R

R15

T15

NC T16

R16

P16

I/O 1L

N16

I/O 2R

N15

I/O 1R N14

I/O 2L

M16

I/O 4L

M15

I/O 3L

M14

I/O 3R

L16

I/O 5R

L15

I/O 4R L14

I/O 5L

K16

I/O 7L

K15

I/O 6L

K14

I/O 6R

J16

I/O 8L

J15

I/O 7R

J14

I/O 8R H16

I/O 10R

H15

IO 9L H14

I/O 9R

G16

I/O 11R

G15

I/O 11L G14

I/O 10L F16

I/O 12L

F14

I/O 12R F15

I/O 13R R9

CE 0R R11

REPEAT R

A 11R T9

CE 1R A6

A 11L

B10

R/W L C13

A 3L

A 10R

R10

R/W R R7

A 9R

T10

OE R T7

A 8R E5

V DD

INT L

V SS

E10

V SS

E11

V DD

E12

V DD E13

V DDQR F5

V DD

V SS

F10

V SS

F12

V DD F13

V DDQR G5

V SS

G10

V SS

G11

V SS

G12

V SS

G13

V DDQL H5

V SS

H10

V SS

H11

V SS

H12

V SS

H13

V DDQL J5

ZZ R

V SS

J10

V SS

J11

V SS

J12

ZZ L

J13

V DDQR K5

V SS

V DD

COL R

V SS

V DD

INT R

V SS

V DDQR N6

V DDQR N7

V DDQL N8

V DDQL K9

V SS

K10

V SS

K11

V SS

K12

V SS

L10

V SS

L11

V SS

L12

V DD

V SS

M10

V SS

M11

V DD

M12

V DD

V DDQR N10

V DDQR N11

V DDQL N12

V DDQL

K13

V DDQR L13

V DDQL M13

V DDQL N13

V DD

COL L

F11

V SS

5666drw 02d

06/19/02A 17R (1)

A 17L (1)

A 16L (2)

A 16R (2)

I/O 19L I/O 19R I/O 20L I/O 20R V DDQL V SS I/O 21L I/O 21R I/O 22L I/O 22R V DDQR

V SS I/O 23L I/O 23R I/O 24L I/O 24R V DDQL V SS I/O 25L I/O 25R I/O 26L I/O 26R V DDQR ZZ R V DD V DD V SS V SS V DDQL V SS I/O 27R I/O 27L I/O 28R I/O 28L V DDQR

V SS I/O 29R I/O 29L I/O 30R I/O 30L V DDQL V SS I/O 31R I/O 31L I/O 32R I/O 32L V DDQR

V SS I/O 33R I/O 33L I/O 34R I/O 34L V S S

V D D Q L

I /O 35R

I /O 35L

P L /F T R

N C C O L R

I N T R

N C N C A 17R (1)

A 16R (2)

A 15R

A 14R

A 13R

A 12R

A 11R

A 10R

A 9R

A 8R

A 7R

B E 3R B E 2R

B E 1R

B E 0R

C E 1R

C E 0R

V D D

V S S

C L K R

O E R

R /W R

A D S R

C N T E N R

R E P E A T R

A 6R

A 5R

A 4R

A 3R

A 2R

A 1R

A 0R

V D D

V S S

N C O P T R

I /O 0L

I /O 0R

V D D Q L

V S S

I/O 16L I/O 16R I/O 15L I/O 15R V SS V DDQL I/O 14L I/O 14R I/O 13L I/O 13R V SS V DDQR I/O 12L I/O 12R I/O 11L I/O 11R V SS V DDQL I/O 10L I/O 10R I/O 9L I/O 9R V SS V DDQR V DD V DD V SS V SS ZZ L V DDQL I/O 8R I/O 8L I/O 7R I/O 7L V SS V DDQR I/O 6R I/O 6L I/O 5R I/O 5L V SS V DDQL I/O 4R I/O 4L I/O 3R I/O 3L V SS V DDQR I/O 2R I/O 2L I/O 1R I/O 1L

V S S

V D D Q R

I /O 18R

I /O 18L

V S S

P L /F T L C O L L

I N T L

N C N C A 17L (1)

A 16L (2)

A 15L

A 14L

A 13L

A 12L

A 11L

A 10L

A 9L

A 8L

A 7L

B E 3L

B E 2L

B E 1L B E 0L

C E 1L

C E 0L

V D D

V S S

C L K L

O E L

R /W L

A D S L

C N T E N L

R E P E A T L

A 6L

A 5L

A 4L

A 3L

A 2L

A 1L

A 0L

V D D

N C O P T L

I /O 17L

I /O 17R

V D D Q R

V S S drw 02a

06/19/02

Pin Configuration (3,4,5,6,9,10) (con't.)

NOTES:

3.All V DD pins must be connected to 2.5V power supply.

4.All V DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DD (2.5V), and 2.5V if OPT pin for that port is set to V ss (0V).

5.All V SS pins must be connected to ground supply.

6.Package body is approximately 28mm x 28mm x 3.5mm.

7.This package code is used to reference the package diagram.

8.This text does not indicate orientation of the actual part-marking.

9.Due to limited pin count, JTAG is not supported in the DR-208 package.

10.Pins 162 and 99 will be V REFL and V REFR respectively for future HSTL device.

1.Pin is a NC for IDT70T3599 and IDT70T3589.

2.Pin is a NC for IDT70T3589.

Pin Configuration (3,4,5,6,9) (con't.)

01/23/03

5666drw02c NOTES:

1.Pin is a NC for IDT70T3599 and IDT70T3589.

2.Pin is a NC for IDT70T3589.

3.All V DD pins must be connected to 2.5V power supply.

4.All V DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DD (2.5V), and 2.5V if OPT pin for that port is

set to V SS (0V).

5.All V SS pins must be connected to ground supply.

6.Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

7.This package code is used to reference the package diagram.

8.This text does not indicate orientation of the actual part-marking.

9.Pins B14 and R14 will be V REFL and V REFR respectively for future HSTL device.

Pin Names

Left Port Right Port Names

CE0L, CE1L CE0R, CE1R Chip Enables (Input)(7)

R/W L R/W R Read/Write Enable (Input)

OE L OE R Output Enable (Input)

A0L - A17L(6)A0R - A17R(6)Address (Input)

I/O0L - I/O35L I/O0R - I/O35R Data Input/Output

CLK L CLK R Clock (Input)

PL/FT L PL/FT R Pipeline/Flow-Through (Input)

ADS L ADS R Address Strobe Enable (Input) CNTEN L CNTEN R Counter Enable (Input)

REPEAT L REPEAT R Counter Repeat(3)

BE0L - BE3L BE0R - BE3R Byte Enables (9-bit bytes) (Input)(7) V DDQL V DDQR Power (I/O Bus) (3.3V or 2.5V)(1) (Input) OPT L OPT R Option for selecting V DDQX(1,2) (Input)

ZZ L ZZ R Sleep Mode pin(4) (Input)

V DD Power (2.5V)(1) (Input)

V SS Ground (0V) (Input)

TDI(5)T est Data Input

TDO(5)T est Data Output

TCK(5)T est Logic Clock (10MHz) (Input)

TMS(5)T est Mode Select (Input)

TRST(5)Reset (Initialize T AP Controller) (Input) INT L INT R Interrupt Flag (Output)

COL L COL R Collision Alert (Output)

5666 tbl 01NOTES:

1.V DD, OPT X, and V DDQX must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2.OPT X selects the operating voltage levels for the I/Os and controls on that port.

If OPT X is set to V DD (2.5V), then that port's I/Os and controls will operate at 3.3V levels and V DDQX must be supplied at 3.3V. If OPT X is set to V SS (0V), then that port's I/Os and address controls will operate at 2.5V levels and V DDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V.

3.When REPEAT X is asserted, the counter will reset to the last valid address loaded

via ADS X.

4.The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when

asserted. All static inputs, i.e., PL/FT x and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundry scan not be operated during sleep mode.

5.Due to limited pin count, JTAG is not supported in the DR-208 package.

6.Address A17x is a NC for the IDT70T3599. Also, Addresses A17x and A16x are

NC's for the IDT 70T3589.

7.Chip Enables and Byte Enables are double buffered when PL/FT = V IH, i.e., the

signals take two cycles to deselect.

NOTES:

1."H" = V IH, "L" = V IL, "X" = Don't Care.

2.ADS , CNTEN , REPEAT = V IH .

3.OE and ZZ are asynchronous input signals.

4.It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table I—Read/Write and Enable Control (1,2,3,4)

OE CLK CE 0CE 1BE 3BE 2BE 1BE 0

R/W ZZ Byte 3I/O 27-35Byte 2I/O 18-26Byte 1I/O 9-17Byte 0I/O 0-8MODE

X ↑H X X X X X

X L High-Z High-Z High-Z High-Z Deselected–Power Down X ↑X L X X X X X L High-Z High-Z High-Z High-Z Deselected–Power Down X ↑L H H H H H X L High-Z High-Z High-Z High-Z All Bytes Deselected X ↑L H H H H L L L High-Z High-Z High-Z D IN Write to Byte 0 Only X ↑L H H H L H L L High-Z High-Z D IN High-Z Write to Byte 1 Only X ↑L H H L H H L L High-Z D IN High-Z High-Z Write to Byte 2 Only X ↑L H L H H H L L D IN High-Z High-Z High-Z Write to Byte 3 Only X ↑L H H H L L L L High-Z High-Z D IN D IN Write to Lower 2 Bytes Only X ↑L H L L H H L L D IN D IN High-Z High-Z Write to Upper 2 bytes Only X ↑L H L L L L L L D IN D IN D IN D IN Write to All Bytes L ↑L H H H H L H L High-Z High-Z High-Z D OUT Read Byte 0 Only L ↑L H H H L H H L High-Z High-Z D OUT High-Z Read Byte 1 Only L ↑L H H L H H H L High-Z D OUT High-Z High-Z Read Byte 2 Only L ↑L H L H H H H L D OUT High-Z High-Z High-Z Read Byte 3 Only L ↑L H H H L L H L High-Z High-Z D OUT D OUT Read Lower 2 Bytes Only L ↑L H L L H H H L D OUT D OUT High-Z High-Z Read Upper 2 Bytes Only L ↑L H L L L L H L D OUT D OUT D OUT D OUT Read All Bytes H ↑X X X X X X X L High-Z High-Z High-Z High-Z

Outputs Disabled

High-Z

High-Z Sleep Mode

5666 tbl 02

Truth Table II—Address Counter Control (1,2)

NOTES:

1."H" = V IH, "L" = V IL, "X" = Don't Care.

2.Read and write operations are controlled by the appropriate setting of R/W , CE 0, CE 1, BE n and OE .

3.Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.

4.ADS and REPEAT are independent of all other memory control signals including CE 0, CE 1 and BE n

5.The address counter advances if CNTEN = V IL on the rising edge of CLK, regardless of all other memory control signals including CE 0, CE 1, BE n.

6.When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS . This value is not set at power-up: a known location should be loaded

via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.

Address Previous Internal Address Internal Address Used CLK ADS CNTEN REPEAT (6)

I/O (3)MODE

An X An ↑ L (4)X H D I/O (n)External Address Used

X An An + 1↑H

L (5)H D I/O (n+1)Counter Enabled—Internal Address generation

X An + 1An + 1↑H H H D I/O (n+1)External Address Blocked—Counter disab led (An + 1 reused)X

↑

L (4)

D I/O (n)

Counter Set to last valid ADS load

5666 tbl 03

Recommended Operating

(1)

NOTES:

1.This is the parameter TA. This is the "instant on" case temperature.

5666 tbl 04

Recommended DC Operating Conditions with V DDQ at 3.3V

NOTES:

1.V IL (min.) = -1.0V for pulse width less than t CYC /2, or 5ns, whichever is less.

2.V IH (max.) = V DDQ + 1.0V for pulse width less than t CYC /2 or 5ns, whichever is less.

3.To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to V DD (2.5V), and V DDQX for that port must be supplied as indicated above.

Symbol Parameter Min.Typ.Max.Unit V DD Core Supply Voltage 2.4 2.5 2.6V V DDQ I/O Supply Voltage (3) 3.15 3.3 3.45V V SS Ground

V V IH

Input High Voltage (Address, Control &Data I/O Inputs)(3) 2.0

____

V DDQ + 150mV (2)

V IH Input High Voltage _JT AG

1.7____

V DD + 100mV (2)V V IH Input High Voltage -ZZ, OPT , PIPE/FT V DD - 0.2V ____

V DD + 100mV (2)

V V IL Input Low Voltage -0.3(1)____

0.8V V IL

Input Low Voltage -ZZ, OPT , PIPE/FT

-0.3(1)

____

0.2

5666 tbl 05b

Recommended DC Operating Conditions with V DDQ at 2.5V

NOTES:

1.V IL (min.) = -1.0V for pulse width less than t CYC /2 or 5ns, whichever is less.

2.V IH (max.) = V DDQ + 1.0V for pulse width less than t CYC /2 or 5ns, whichever is less.

3.To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT

pin for that port must be set to V ss (0V), and V DDQX for that port must be supplied as indicated above.

Symbol Parameter Min.Typ.Max.Unit V DD Core Supply Voltage 2.4 2.5 2.6V V DDQ I/O Supply Voltage (3) 2.4 2.5 2.6V V SS Ground

V V IH

Input High Volltage (Address, Control &Data I/O Inputs)(3) 1.7

____

V DDQ + 100mV (2)

V IH Input High Voltage _JT AG

1.7____

V DD + 100mV (2)V V IH Input High Voltage -ZZ, OPT , PIPE/FT V DD - 0.2V ____

V DD + 100mV (2)

V V IL Input Low Voltage -0.3(1)____

0.7V V IL

Input Low Voltage -ZZ, OPT , PIPE/FT

-0.3(1)

____

0.2

5666 tbl 05a

Absolute Maximum Ratings (1)

Symbol Rating

Commercial & Industrial Unit V TERM (V DD )V DD T erminal Voltage with Respect to GND -0.5 to 3.6V V TERM (2)(V DDQ )

V DDQ T erminal Voltage with Respect to GND -0.3 to V DDQ + 0.3V V TERM (2)

(INPUTS and I/O's)Input and I/O T erminal

Voltage with Respect to GND -0.3 to V DDQ + 0.3

T BIAS (3)Temperature Under Bias -55 to +125o C T STG Storage Temperature -65 to +150o C T JN

Junction Temperature

+150o

I OUT (For V DDQ = 3.3V)DC Output Current 50mA I OUT (For V DDQ = 2.5V)DC Output Current

5666 tbl 06

NOTES:

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.This is a steady-state DC parameter that applies after the power supply has reached its

nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed V DDQ during power supply ramp up.3.Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.

NOTES:

1.These parameters are determined by device characterization, but are not production tested.

2.3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V.

3.C OUT also references C I/O .

Capacitance (1)

(T A = +25°C, F = 1.0MH Z ) PQFP ONLY

Symbol Parameter Conditions (2)Max.Unit C IN Input Capacitance V IN = 3dV 8pF C OUT (3)

Output Capacitance

V OUT = 3dV

10.5

5666 tbl 07

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (V DD = 2.5V ± 100mV)

Symbol Parameter

Test Conditions

70T3519/99/89S

Unit Min.

Max.|I LI |Input Leakage Current (1)

V DDQ = Max., V IN = 0V to V DDQ ___10μA |I LI |JT AG & ZZ Input Leakage Current (1,2)V DD = Max., V IN = 0V to V DD

___±30μA |I LO |Output Leakage Current (1,3)CE 0 = V IH or CE 1 = V IL , V OUT = 0V to V DDQ ___10μA V OL (3.3V)Output Low Voltage (1)I OL = +4mA, V DDQ = Min.___

0.4

V V OH (3.3V)Output High Voltage (1)I OH = -4mA, V DDQ = Min. 2.4

___

V V OL (2.5V)Output Low Voltage (1)I OL = +2mA, V DDQ = Min.___

0.4

V V OH (2.5V)

Output High Voltage (1)

I OH = -2mA, V DDQ = Min.

2.0

___

5666 tbl 08

NOTES:

1.V DDQ is selectable (3.3V/

2.5V) via OPT pins. Refer to p.5 for details.2.Applicable only for TMS, TDI and TRST inputs.

3.Outputs tested in tri-state mode.

DC Electrical Characteristics Over the Operating

(3)

1.At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t CYC, using "AC TEST CONDITIONS".

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3.Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4.V DD = 2.5V, T A = 25°C for Typ, and are not production tested. I DD DC(f=0)= 15mA (Typ).

5.CE X = V IL means CE0X = V IL and CE1X = V IH

CE X = V IH means CE0X = V IH or CE1X = V IL

CE X < 0.2V means CE0X < 0.2V and CE1X > V DD - 0.2V

CE X > V DD - 0.2V means CE0X > V DD - 0.2V or CE1X - 0.2V

"X" represents "L" for left port or "R" for right port.

6.I SB1, I SB2 and I SB4 will all reach full standby levels (I SB3) on the appropriate port(s) if ZZ L and/or ZZ R = V IH.

7.166MHz I-Temp is not available in the BF-208 package.

8. 200Mhz is not available in the BF-208 and DR-208 packages.

AC Test Conditions (V DDQ - 3.3V/2.5V)

Figure 1. AC Output Test load.

Input Pulse Levels (Address & Controls)Input Pulse Levels (I/Os)Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load

GND to 3.0V/GND to 2.4V GND to 3.0V/GND to 2.4V

2ns 1.5V/1.25V

1.5V/1.25V Figure 1

5666 tbl 10

1.5V/1.25

5666drw 03

DATA OUT

Capacitance (pF)from AC Test Load

5666drw 04

?tCD

(Typical,ns)

AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) (2,3) (V DD = 2.5V ± 100mV, T A = 0°C to +70°C)

NOTES:

1.The Pipelined output parameters (t CYC2, t CD2) apply to either or both left and right ports when FT /PIPE X = V DD (

2.5V). Flow-through parameters (t CYC1, t CD1)apply when FT /PIPE = V ss (0V) for that port.

2.All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE ), FT /PIPE and OPT. FT /PIPE and OPT should be treated as DC signals, i.e. steady state during operation.

3.These values are valid for either level of V DDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.

4.166MHz I-Temp is not available in the BF-208 package.

5.200Mhz is not available in the BF-208 and DR-208 packages.70T3519/99/89

S200Com'l Only (5)

70T3519/99/89

S166Com'l & Ind (4)70T3519/99/89

S133Com'l & Ind Symbol Parameter

Min.Max.

Unit t CYC1Clock Cycle Time (Flow-Through)(1)15____20____25____ns t CYC2Clock Cycle Time (Pipelined)(1)5____6____7.5____ns t CH1Clock High Time (Flow-Through)(1)6____8____10____ns t CL1Clock Low Time (Flow-Through)(1)6____8____10____ns t CH2Clock High Time (Pipelined)(2)2____ 2.4____3____ns t CL2Clock Low Time (Pipelined)(1)2____ 2.4____3____ns t SA Address Setup Time 1.5____ 1.7____ 1.8____ns t HA Address Hold Time 0.5____0.5____0.5____ns t SC Chip Enable Setup Time 1.5____ 1.7____ 1.8____ns t HC Chip Enable Hold Time 0.5____0.5____0.5____ns t SB Byte Enable Setup Time 1.5____ 1.7____ 1.8____ns t HB Byte Enable Hold Time 0.5____0.5____0.5____ns t SW R/W Setup Time 1.5____ 1.7____ 1.8____ns t HW R/W Hold Time 0.5____0.5____0.5____ns t SD Input Data Setup Time 1.5____ 1.7____ 1.8____ns t HD Input Data Hold Time 0.5____0.5____0.5____ns t SAD ADS Setup Time 1.5____ 1.7____ 1.8____ns t HAD ADS Hold Time 0.5____0.5____0.5____ns t SCN CNTEN Setup Time 1.5____ 1.7____ 1.8____ns t HCN CNTEN Hold Time 0.5____0.5____0.5____ns t SRPT REPEA T Setup Time 1.5____ 1.7____ 1.8____ns t HRPT REPEA T Hold Time 0.5

____

0.5

____

0.5

____

ns t OE Output Enable to Data Valid ____

4.4

____

4.4

____

4.6

ns t OLZ (6)Output Enable to Output Low-Z 1____

1____

ns t OHZ (6)Output Enable to Output High-Z 1

3.41

3.61

4.2ns t CD1Clock to Data Valid (Flow-Through)(1)____10____12____15ns t CD2Clock to Data Valid (Pipelined)(1)____

3.4

____

3.6

____

4.2

ns t DC Data Output Hold After Clock High 1____

1____

ns t CKHZ (6)Clock High to Output High-Z 1 3.4

1 3.6

1 4.2

ns t CKLZ (6)Clock High to Output Low-Z 1

____

ns t INS Interrupt Flag Set Time ____7____7____7ns t INR Interrupt Flag Reset Time ____7____7____7ns t COLS Collision Flag Set Time ____ 3.4____ 3.6____ 4.2ns t COLR Collision Flag Reset Time ____

3.4

____

3.6

____

4.2

ns t ZZSC Sleep Mode Set Cycles 2____2____2____cycles t ZZRC

Sleep Mode Recovery Cycles

____

cycles

Port-to-Port Delay t CO Clock-to-Clock Offset

____

t OFS

Clock-to-Clock Offset for Collision Detection

Please refer to Collision Detection Timing T able on Page 21

5666 tbl 11

R/W

ADDRESS

CE 0

CLK

CE 1

BE n

DATA OUT OE

5666drw 05

Timing Waveform of Read Cycle for Pipelined Operation (FT 'X' IH (1,2)

NOTES:

1.OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.

2.ADS = V IL , CNTEN and REPEAT = V IH .

3.The output is disabled (High-Impedance state) by CE 0 = V IH , CE 1 = V IL , BE n = V IH following the next rising edge of the clock. Refer to

Truth Table 1.

4.Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.

5. If BE n was HIGH, then the appropriate Byte of DATA OUT for Qn + 2 would be disabled (High-Impedance state).

6."x" denotes Left or Right port. The diagram is with respect to that port.

Timing Waveform of Read Cycle for Flow-through Output (FT /PIPE

(1,2,6)

R/W

ADDRESS

DATA OUT CE 0

CLK

CE 1

BE n

CE 0(B1)

ADDRESS (B1)

CLK

DATA OUT(B1)

ADDRESS (B2)

CE 0(B2)

DATA OUT(B2)

5666drw 07

(1,2)

NOTES:

1. B1 Represents Device #1; B2 Represents Device #

2. Each Device consists of one IDT70T3519/99/89 for this waveform, and are setup for depth expansion in this example. ADDRESS (B1) = ADDRESS (B2) in this situation.2. BE n , OE , and ADS = V IL ; CE 1(B1), CE 1(B2), R/W , CNTEN , and REPEAT = V IH .

Timing Waveform of a Multi-Device Flow-Through Read (1,2)

CE 0(B1)

ADDRESS (B1)

CLK

DATA OUT(B1)

ADDRESS (B2)

CE 0(B2)

DATA OUT(B2)

CLK "A"

R/W "A"

ADDRESS "A"

DATA IN"A"

CLK "B"

R/W "B"

ADDRESS "B"

DATA OUT"B"

Timing Waveform of Left Port Write to Pipelined Right Port Read (1,2,4)

NOTES:

1.CE 0, BE n , and ADS = V IL ; CE 1, CNTEN , and REPEAT = V IH .

2.OE = V IL for Port "B", which is being read from. OE = V IH for Port "A", which is being written to.

3.If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be

t CO + 2 t CYC2 + t CD2). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port will be t CO + t CYC2 + t CD2).

4.All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"

Timing Waveform with Port-to-Port Flow-Through Read (1,2,4)

DATA IN "A"

CLK "B"

R/W "B"

ADDRESS "A"

R/W "A"

CLK "A"

ADDRESS "B"

DATA OUT "B"

NOTES:

1.CE 0, BE n, and ADS = V IL ; CE 1, CNTEN , and REPEAT = V IH .

2.OE = V IL for the Right Port, which is being read from. OE = V IH for the Left Port, which is being written to.

3.If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be

t CO + t CYC + t CD1). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will be t CO + t CD1).

4.All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".

R/W

ADDRESS

DATA IN

CE 0

CLK

DATA OUT

CE 1

BE n

Timing Waveform of Pipelined Read-to-Write-to-Read

(OE = V IL )NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE 0, BE n , and ADS = V IL ; CE 1, CNTEN , and REPEAT = V IH . "NOP" is "No Operation".

3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

R/W

ADDRESS

DATA IN

CE 0

CLK DATA OUT

CE 1

BE n

(2)

NOTES:

1.Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2.CE 0, BE n , and ADS = V IL ; CE 1, CNTEN , and REPEAT = V IH .

3.Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.

4.This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.

Timing Waveform of Flow-Through Read-to-Write-to-Read ( OE = V IL)(2)

(2) NOTES:

1.Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2.CE0, BE n, and ADS = V IL; CE1, CNTEN, and REPEAT = V IH.

3.Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

4."NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

R/W

ADDRESS

DATA IN

CE0

CLK

DATA OUT

CE1

BE n

R/W

DATA IN

CE0

CLK

DATA OUT

CE1

BE n

ADDRESS

CLK

DATA OUT

ADS CNTEN

5666drw 15

Timing Waveform of Pipelined Read with Address Counter Advance (1)

NOTES:

1.CE 0, OE , BE n = V IL ; CE 1, R/W , and REPEAT = V IH .

2.If there is no address change via ADS = V IL (loading a new address) or CNTEN = V IL (advancing the address), i.e. ADS = V IH and CNTEN = V IH , then

the data output remains constant for subsequent clocks.

Timing Waveform of Flow-Through Read with Address Counter Advance (1)

ADDRESS

CLK

DATA OUT

ADS CNTEN

5666drw 16

ADDRESS

COUNTER

5666drw 18

ADDRESS

WRITE TO An+1

WRITE TO An+2

ADS ADDRESS

READ An+1

READ An+2

Timing Waveform of Write with Address Counter Advance (Flow-through or Pipelined Inputs) (1)

Timing Waveform of Counter Repeat (2,6)

ADDRESS

CLK

DATA IN

ADS

CNTEN

INTERNAL ADDRESS

NOTES:

1.CE 0, BE n , and R/W = V IL ; CE 1 and REPEAT = V IH .

2.CE 0, BE n = V IL ; CE 1 = V IH .

3.The "Internal Address" is equal to the "External Address" when ADS = V IL and equals the counter output when ADS = V IH .

4.No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.

https://www.doczj.com/doc/f93162371.html,TEN = V IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is

written to during this cycle.

6.For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.

Truth Table III — Interrupt Flag (1)

Left Port

Right Port Function

CLK L R/W L (2)

CE L (2)A 17L -A 0L (3,4,5)

INT L CLK R R/W R (2)

CE R (2)A 17R -A 0R (3,4,5)

INT R ↑L L 3FFFF X ↑X X X L Set Right INT R Flag ↑X X X X ↑H L 3FFFF H Reset Right INT R Flag ↑X X X L ↑L L 3FFFE X Set Left INT L Flag ↑

3FFFE

↑

Reset Left INT L Flag

5666 tbl 12

NOTES:

1.INT L and INT R must be initialized at power-up by Resetting the flags.

2.CE 0 = V IL and CE 1 = V IH . R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.

3.A17X is a NC for IDT70T3599, therefore Interrupt Addresses are 1FFFF and 1FFFE.

4.A17X and A16X are NC's for IDT70T3589, therefore Interrupt Addresses are FFFF and FFFE.

5.Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

Waveform of Interrupt Timing (2)

NOTES:

1.CE 0 = V IL and CE 1 = V IH

2.All timing is the same for Left and Right ports.

Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

CLK R

CE R (1)

ADDRESS R (3)

CLK L

R/W L

ADDRESS L (3)

CE L (1)

5666drw 19

INT R

R/W R