TEXAS INSTRUMENTS-PRODUCTION DATA
Stellaris?LM3S5662Microcontroller
DATA SHEET
Copyright?2007-2011 DS-LM3S5662-11107
Copyright
Copyright?2007-2011Texas Instruments Incorporated All rights reserved.Stellaris?and StellarisWare?are registered trademarks of Texas Instruments Incorporated.ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited.Other names and brands may be claimed as the property of others.
PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
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Austin,TX78746
https://www.doczj.com/doc/e218942551.html,/stellaris
https://www.doczj.com/doc/e218942551.html,/sc/technical-support/product-information-centers.htm
Stellaris?LM3S5662Microcontroller
Table of Contents
Revision History (26)
About This Document (32)
Audience (32)
About This Manual (32)
Related Documents (32)
Documentation Conventions (33)
1Architectural Overview (35)
1.1Product Features (35)
1.2Target Applications (44)
1.3High-Level Block Diagram (44)
1.4Functional Overview (46)
1.4.1ARM Cortex?-M3 (46)
1.4.2Motor Control Peripherals (47)
1.4.3Analog Peripherals (48)
1.4.4Serial Communications Peripherals (48)
1.4.5System Peripherals (49)
1.4.6Memory Peripherals (50)
1.4.7Additional Features (51)
1.4.8Hardware Details (51)
2The Cortex-M3Processor (52)
2.1Block Diagram (53)
2.2Overview (54)
2.2.1System-Level Interface (54)
2.2.2Integrated Configurable Debug (54)
2.2.3Trace Port Interface Unit(TPIU) (55)
2.2.4Cortex-M3System Component Details (55)
2.3Programming Model (56)
2.3.1Processor Mode and Privilege Levels for Software Execution (56)
2.3.2Stacks (56)
2.3.3Register Map (57)
2.3.4Register Descriptions (58)
2.3.5Exceptions and Interrupts (71)
2.3.6Data Types (71)
2.4Memory Model (71)
2.4.1Memory Regions,Types and Attributes (73)
2.4.2Memory System Ordering of Memory Accesses (73)
2.4.3Behavior of Memory Accesses (73)
2.4.4Software Ordering of Memory Accesses (74)
2.4.5Bit-Banding (75)
2.4.6Data Storage (77)
2.4.7Synchronization Primitives (78)
2.5Exception Model (79)
2.5.1Exception States (80)
2.5.2Exception Types (80)
2.5.3Exception Handlers (83)
Table of Contents
2.5.4Vector Table (83)
2.5.5Exception Priorities (84)
2.5.6Interrupt Priority Grouping (85)
2.5.7Exception Entry and Return (85)
2.6Fault Handling (87)
2.6.1Fault Types (88)
2.6.2Fault Escalation and Hard Faults (88)
2.6.3Fault Status Registers and Fault Address Registers (89)
2.6.4Lockup (89)
2.7Power Management (89)
2.7.1Entering Sleep Modes (90)
2.7.2Wake Up from Sleep Mode (90)
2.8Instruction Set Summary (91)
3Cortex-M3Peripherals (94)
3.1Functional Description (94)
3.1.1System Timer(SysTick) (94)
3.1.2Nested Vectored Interrupt Controller(NVIC) (95)
3.1.3System Control Block(SCB) (97)
3.1.4Memory Protection Unit(MPU) (97)
3.2Register Map (102)
3.3System Timer(SysTick)Register Descriptions (104)
3.4NVIC Register Descriptions (108)
3.5System Control Block(SCB)Register Descriptions (121)
3.6Memory Protection Unit(MPU)Register Descriptions (148)
4JTAG Interface (158)
4.1Block Diagram (159)
4.2Signal Description (159)
4.3Functional Description (160)
4.3.1JTAG Interface Pins (160)
4.3.2JTAG TAP Controller (161)
4.3.3Shift Registers (162)
4.3.4Operational Considerations (162)
4.4Initialization and Configuration (165)
4.5Register Descriptions (165)
4.5.1Instruction Register(IR) (165)
4.5.2Data Registers (167)
5System Control (170)
5.1Signal Description (170)
5.2Functional Description (170)
5.2.1Device Identification (170)
5.2.2Reset Control (170)
5.2.3Non-Maskable Interrupt (174)
5.2.4Power Control (175)
5.2.5Clock Control (175)
5.2.6System Control (181)
5.3Initialization and Configuration (182)
5.4Register Map (182)
5.5Register Descriptions (184)
Stellaris?LM3S5662Microcontroller 6Hibernation Module (238)
6.1Block Diagram (239)
6.2Signal Description (239)
6.3Functional Description (240)
6.3.1Register Access Timing (240)
6.3.2Clock Source (240)
6.3.3Battery Management (242)
6.3.4Real-Time Clock (242)
6.3.5Battery-Backed Memory (242)
6.3.6Power Control (243)
6.3.7Initiating Hibernate (243)
6.3.8Interrupts and Status (243)
6.4Initialization and Configuration (244)
6.4.1Initialization (244)
6.4.2RTC Match Functionality(No Hibernation) (244)
6.4.3RTC Match/Wake-Up from Hibernation (244)
6.4.4External Wake-Up from Hibernation (245)
6.4.5RTC/External Wake-Up from Hibernation (245)
6.5Register Map (245)
6.6Register Descriptions (246)
7Internal Memory (260)
7.1Block Diagram (260)
7.2Functional Description (260)
7.2.1SRAM Memory (260)
7.2.2ROM Memory (261)
7.2.3Flash Memory (261)
7.3Flash Memory Initialization and Configuration (263)
7.3.1Flash Programming (263)
7.3.2Nonvolatile Register Programming (263)
7.4Register Map (264)
7.5ROM Register Descriptions(System Control Offset) (265)
7.6Flash Register Descriptions(Flash Control Offset) (266)
7.7Flash Register Descriptions(System Control Offset) (274)
8Micro Direct Memory Access(μDMA) (289)
8.1Block Diagram (290)
8.2Functional Description (290)
8.2.1Channel Assigments (291)
8.2.2Priority (291)
8.2.3Arbitration Size (291)
8.2.4Request Types (292)
8.2.5Channel Configuration (292)
8.2.6Transfer Modes (294)
8.2.7Transfer Size and Increment (302)
8.2.8Peripheral Interface (302)
8.2.9Software Request (302)
8.2.10Interrupts and Errors (303)
8.3Initialization and Configuration (303)
8.3.1Module Initialization (303)
Table of Contents
8.3.2Configuring a Memory-to-Memory Transfer (303)
8.3.3Configuring a Peripheral for Simple Transmit (305)
8.3.4Configuring a Peripheral for Ping-Pong Receive (306)
8.4Register Map (309)
8.5μDMA Channel Control Structure (310)
8.6μDMA Register Descriptions (316)
9General-Purpose Input/Outputs(GPIOs) (350)
9.1Signal Description (350)
9.2Functional Description (353)
9.2.1Data Control (354)
9.2.2Interrupt Control (355)
9.2.3Mode Control (356)
9.2.4Commit Control (356)
9.2.5Pad Control (356)
9.2.6Identification (357)
9.3Initialization and Configuration (357)
9.4Register Map (358)
9.5Register Descriptions (360)
10General-Purpose Timers (397)
10.1Block Diagram (398)
10.2Signal Description (398)
10.3Functional Description (399)
10.3.1GPTM Reset Conditions (399)
10.3.232-Bit Timer Operating Modes (399)
10.3.316-Bit Timer Operating Modes (401)
10.4Initialization and Configuration (404)
10.4.132-Bit One-Shot/Periodic Timer Mode (404)
10.4.232-Bit Real-Time Clock(RTC)Mode (405)
10.4.316-Bit One-Shot/Periodic Timer Mode (405)
10.4.416-Bit Input Edge Count Mode (406)
10.4.516-Bit Input Edge Timing Mode (406)
10.4.616-Bit PWM Mode (407)
10.5Register Map (407)
10.6Register Descriptions (408)
11Watchdog Timer (431)
11.1Block Diagram (432)
11.2Functional Description (432)
11.3Initialization and Configuration (433)
11.4Register Map (433)
11.5Register Descriptions (434)
12Analog-to-Digital Converter(ADC) (455)
12.1Block Diagram (455)
12.2Signal Description (456)
12.3Functional Description (456)
12.3.1Sample Sequencers (457)
12.3.2Module Control (457)
12.3.3Hardware Sample Averaging Circuit (458)
Stellaris?LM3S5662Microcontroller 12.3.4Analog-to-Digital Converter (458)
12.3.5Differential Sampling (459)
12.3.6Internal Temperature Sensor (461)
12.4Initialization and Configuration (462)
12.4.1Module Initialization (462)
12.4.2Sample Sequencer Configuration (462)
12.5Register Map (463)
12.6Register Descriptions (464)
13Universal Asynchronous Receivers/Transmitters(UARTs) (491)
13.1Block Diagram (492)
13.2Signal Description (492)
13.3Functional Description (493)
13.3.1Transmit/Receive Logic (493)
13.3.2Baud-Rate Generation (493)
13.3.3Data Transmission (494)
13.3.4Serial IR(SIR) (494)
13.3.5FIFO Operation (495)
13.3.6Interrupts (496)
13.3.7Loopback Operation (497)
13.3.8DMA Operation (497)
13.3.9IrDA SIR block (497)
13.4Initialization and Configuration (497)
13.5Register Map (498)
13.6Register Descriptions (499)
14Synchronous Serial Interface(SSI) (534)
14.1Block Diagram (535)
14.2Signal Description (535)
14.3Functional Description (536)
14.3.1Bit Rate Generation (536)
14.3.2FIFO Operation (536)
14.3.3Interrupts (537)
14.3.4Frame Formats (537)
14.3.5DMA Operation (545)
14.4Initialization and Configuration (545)
14.5Register Map (546)
14.6Register Descriptions (547)
15Controller Area Network(CAN)Module (574)
15.1Block Diagram (575)
15.2Signal Description (575)
15.3Functional Description (576)
15.3.1Initialization (577)
15.3.2Operation (577)
15.3.3Transmitting Message Objects (578)
15.3.4Configuring a Transmit Message Object (578)
15.3.5Updating a Transmit Message Object (580)
15.3.6Accepting Received Message Objects (580)
15.3.7Receiving a Data Frame (580)
15.3.8Receiving a Remote Frame (581)
Table of Contents
15.3.9Receive/Transmit Priority (581)
15.3.10Configuring a Receive Message Object (581)
15.3.11Handling of Received Message Objects (582)
15.3.12Handling of Interrupts (585)
15.3.13Test Mode (585)
15.3.14Bit Timing Configuration Error Considerations (587)
15.3.15Bit Time and Bit Rate (587)
15.3.16Calculating the Bit Timing Parameters (589)
15.4Register Map (592)
15.5CAN Register Descriptions (594)
16Universal Serial Bus(USB)Controller (620)
16.1Block Diagram (621)
16.2Signal Description (621)
16.3Functional Description (622)
16.3.1Operation as a Device (622)
16.3.2Operation as a Host (627)
16.3.3OTG Mode (631)
16.3.4DMA Operation (633)
16.4Initialization and Configuration (634)
16.4.1Pin Configuration (634)
16.4.2Endpoint Configuration (634)
16.5Register Map (635)
16.6Register Descriptions (638)
17Pulse Width Modulator(PWM) (718)
17.1Block Diagram (719)
17.2Signal Description (720)
17.3Functional Description (720)
17.3.1PWM Timer (720)
17.3.2PWM Comparators (721)
17.3.3PWM Signal Generator (722)
17.3.4Dead-Band Generator (723)
17.3.5Interrupt/ADC-Trigger Selector (723)
17.3.6Synchronization Methods (723)
17.3.7Fault Conditions (724)
17.3.8Output Control Block (725)
17.4Initialization and Configuration (725)
17.5Register Map (726)
17.6Register Descriptions (728)
18Pin Diagram (762)
19Signal Tables (763)
19.1Connections for Unused Signals (773)
20Operating Characteristics (774)
21Electrical Characteristics (775)
21.1DC Characteristics (775)
21.1.1Maximum Ratings (775)
21.1.2Recommended DC Operating Conditions (775)
21.1.3On-Chip Low Drop-Out(LDO)Regulator Characteristics (776)
Stellaris?LM3S5662Microcontroller 21.1.4GPIO Module Characteristics (776)
21.1.5Power Specifications (776)
21.1.6Flash Memory Characteristics (778)
21.1.7Hibernation (778)
21.1.8USB (778)
21.2AC Characteristics (779)
21.2.1Load Conditions (779)
21.2.2Clocks (779)
21.2.3JTAG and Boundary Scan (781)
21.2.4Reset (782)
21.2.5Sleep Modes (784)
21.2.6Hibernation Module (784)
21.2.7General-Purpose I/O(GPIO) (785)
21.2.8Analog-to-Digital Converter (785)
21.2.9Synchronous Serial Interface(SSI) (786)
21.2.10Universal Serial Bus(USB)Controller (788)
A Boot Loader (789)
A.1Boot Loader (789)
A.2Interfaces (789)
A.2.1UART (789)
A.2.2SSI (790)
A.3Packet Handling (790)
A.3.1Packet Format (790)
A.3.2Sending Packets (790)
A.3.3Receiving Packets (791)
A.4Commands (791)
A.4.1COMMAND_PING(0X20) (791)
A.4.2COMMAND_DOWNLOAD(0x21) (791)
A.4.3COMMAND_RUN(0x22) (792)
A.4.4COMMAND_GET_STATUS(0x23) (792)
A.4.5COMMAND_SEND_DATA(0x24) (792)
A.4.6COMMAND_RESET(0x25) (793)
B ROM DriverLib Functions (794)
B.1DriverLib Functions Included in the Integrated ROM (794)
C Register Quick Reference (805)
D Ordering and Contact Information (835)
D.1Ordering Information (835)
D.2Part Markings (835)
D.3Kits (836)
D.4Support Information (836)
E Package Information (837)
E.164-Pin LQFP Package (837)
E.1.1Package Dimensions (837)
E.1.2Tray Dimensions (839)
E.1.3Tape and Reel Dimensions (840)
Table of Contents
List of Figures
Figure1-1.Stellaris LM3S5662Microcontroller High-Level Block Diagram (45)
Figure2-1.CPU Block Diagram (54)
Figure2-2.TPIU Block Diagram (55)
Figure2-3.Cortex-M3Register Set (57)
Figure2-4.Bit-Band Mapping (77)
Figure2-5.Data Storage (78)
Figure2-6.Vector Table (84)
Figure2-7.Exception Stack Frame (86)
Figure3-1.SRD Use Example (100)
Figure4-1.JTAG Module Block Diagram (159)
Figure4-2.Test Access Port State Machine (162)
Figure4-3.IDCODE Register Format (168)
Figure4-4.BYPASS Register Format (168)
Figure4-5.Boundary Scan Register Format (169)
Figure5-1.Basic RST Configuration (172)
Figure5-2.External Circuitry to Extend Power-On Reset (172)
Figure5-3.Reset Circuit Controlled by Switch (173)
Figure5-4.Main Clock Tree (177)
Figure6-1.Hibernation Module Block Diagram (239)
Figure6-2.Clock Source Using Crystal (241)
Figure6-3.Clock Source Using Dedicated Oscillator (241)
Figure7-1.Flash Block Diagram (260)
Figure8-1.μDMA Block Diagram (290)
Figure8-2.Example of Ping-Pong DMA Transaction (295)
Figure8-3.Memory Scatter-Gather,Setup and Configuration (297)
Figure8-4.Memory Scatter-Gather,μDMA Copy Sequence (298)
Figure8-5.Peripheral Scatter-Gather,Setup and Configuration (300)
Figure8-6.Peripheral Scatter-Gather,μDMA Copy Sequence (301)
Figure9-1.Digital I/O Pads (353)
Figure9-2.Analog/Digital I/O Pads (354)
Figure9-3.GPIODATA Write Example (355)
Figure9-4.GPIODATA Read Example (355)
Figure10-1.GPTM Module Block Diagram (398)
Figure10-2.16-Bit Input Edge Count Mode Example (402)
Figure10-3.16-Bit Input Edge Time Mode Example (403)
Figure10-4.16-Bit PWM Mode Example (404)
Figure11-1.WDT Module Block Diagram (432)
Figure12-1.ADC Module Block Diagram (456)
Figure12-2.Differential Sampling Range,V IN_ODD=1.5V (460)
Figure12-3.Differential Sampling Range,V IN_ODD=0.75V (460)
Figure12-4.Differential Sampling Range,V IN_ODD=2.25V (461)
Figure12-5.Internal Temperature Sensor Characteristic (462)
Figure13-1.UART Module Block Diagram (492)
Figure13-2.UART Character Frame (493)
Figure13-3.IrDA Data Modulation (495)
Figure14-1.SSI Module Block Diagram (535)
Stellaris?LM3S5662Microcontroller Figure14-2.TI Synchronous Serial Frame Format(Single Transfer) (538)
Figure14-3.TI Synchronous Serial Frame Format(Continuous Transfer) (539)
Figure14-4.Freescale SPI Format(Single Transfer)with SPO=0and SPH=0 (539)
Figure14-5.Freescale SPI Format(Continuous Transfer)with SPO=0and SPH=0 (540)
Figure14-6.Freescale SPI Frame Format with SPO=0and SPH=1 (541)
Figure14-7.Freescale SPI Frame Format(Single Transfer)with SPO=1and SPH=0 (541)
Figure14-8.Freescale SPI Frame Format(Continuous Transfer)with SPO=1and SPH=0 (542)
Figure14-9.Freescale SPI Frame Format with SPO=1and SPH=1 (543)
Figure14-10.MICROWIRE Frame Format(Single Frame) (543)
Figure14-11.MICROWIRE Frame Format(Continuous Transfer) (544)
Figure14-12.MICROWIRE Frame Format,SSIFss Input Setup and Hold Requirements (545)
Figure15-1.CAN Controller Block Diagram (575)
Figure15-2.CAN Data/Remote Frame (576)
Figure15-3.Message Objects in a FIFO Buffer (584)
Figure15-4.CAN Bit Time (588)
https://www.doczj.com/doc/e218942551.html,B Module Block Diagram (621)
Figure17-1.PWM Unit Diagram (719)
Figure17-2.PWM Module Block Diagram (720)
Figure17-3.PWM Count-Down Mode (721)
Figure17-4.PWM Count-Up/Down Mode (722)
Figure17-5.PWM Generation Example In Count-Up/Down Mode (722)
Figure17-6.PWM Dead-Band Generator (723)
Figure18-1.64-Pin LQFP Package Pin Diagram (762)
Figure21-1.Load Conditions (779)
Figure21-2.JTAG Test Clock Input Timing (782)
Figure21-3.JTAG Test Access Port(TAP)Timing (782)
Figure21-4.External Reset Timing(RST) (783)
Figure21-5.Power-On Reset Timing (783)
Figure21-6.Brown-Out Reset Timing (783)
Figure21-7.Software Reset Timing (783)
Figure21-8.Watchdog Reset Timing (784)
Figure21-9.Hibernation Module Timing (785)
Figure21-10.ADC Input Equivalency Diagram (786)
Figure21-11.SSI Timing for TI Frame Format(FRF=01),Single Transfer Timing
Measurement (787)
Figure21-12.SSI Timing for MICROWIRE Frame Format(FRF=10),Single Transfer (787)
Figure21-13.SSI Timing for SPI Frame Format(FRF=00),with SPH=1 (788)
Figure E-1.Stellaris LM3S566264-Pin LQFP Package (837)
Figure E-2.64-Pin LQFP Tray Dimensions (839)
Figure E-3.64-Pin LQFP Tape and Reel Dimensions (840)
Table of Contents
List of Tables
Table1.Revision History (26)
Table2.Documentation Conventions (33)
Table2-1.Summary of Processor Mode,Privilege Level,and Stack Use (57)
Table2-2.Processor Register Map (58)
Table2-3.PSR Register Combinations (63)
Table2-4.Memory Map (71)
Table2-5.Memory Access Behavior (73)
Table2-6.SRAM Memory Bit-Banding Regions (76)
Table2-7.Peripheral Memory Bit-Banding Regions (76)
Table2-8.Exception Types (81)
Table2-9.Interrupts (82)
Table2-10.Exception Return Behavior (87)
Table2-11.Faults (88)
Table2-12.Fault Status and Fault Address Registers (89)
Table2-13.Cortex-M3Instruction Summary (91)
Table3-1.Core Peripheral Register Regions (94)
Table3-2.Memory Attributes Summary (97)
Table3-3.TEX,S,C,and B Bit Field Encoding (100)
Table3-4.Cache Policy for Memory Attribute Encoding (101)
Table3-5.AP Bit Field Encoding (101)
Table3-6.Memory Region Attributes for Stellaris Microcontrollers (101)
Table3-7.Peripherals Register Map (102)
Table3-8.Interrupt Priority Levels (127)
Table3-9.Example SIZE Field Values (155)
Table4-1.JTAG_SWD_SWO Signals(64LQFP) (159)
Table4-2.JTAG Port Pins Reset State (160)
Table4-3.JTAG Instruction Register Commands (166)
Table5-1.System Control&Clocks Signals(64LQFP) (170)
Table5-2.Reset Sources (171)
Table5-3.Clock Source Options (176)
Table5-4.Possible System Clock Frequencies Using the SYSDIV Field (178)
Table5-5.Examples of Possible System Clock Frequencies Using the SYSDIV2Field (178)
Table5-6.System Control Register Map (182)
Table5-7.RCC2Fields that Override RCC fields (200)
Table6-1.Hibernate Signals(64LQFP) (239)
Table6-2.Hibernation Module Register Map (245)
Table7-1.Flash Protection Policy Combinations (262)
https://www.doczj.com/doc/e218942551.html,er-Programmable Flash Memory Resident Registers (264)
Table7-3.Flash Register Map (264)
Table8-1.DMA Channel Assignments (291)
Table8-2.Request Type Support (292)
Table8-3.Control Structure Memory Map (293)
Table8-4.Channel Control Structure (293)
Table8-5.μDMA Read Example:8-Bit Peripheral (302)
Table8-6.μDMA Interrupt Assignments (303)
Table8-7.Channel Control Structure Offsets for Channel30 (304)
Stellaris?LM3S5662Microcontroller Table8-8.Channel Control Word Configuration for Memory Transfer Example (304)
Table8-9.Channel Control Structure Offsets for Channel7 (305)
Table8-10.Channel Control Word Configuration for Peripheral Transmit Example (306)
Table8-11.Primary and Alternate Channel Control Structure Offsets for Channel8 (307)
Table8-12.Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example (308)
Table8-13.μDMA Register Map (309)
Table9-1.GPIO Pins With Non-Zero Reset Values (351)
Table9-2.GPIO Pins and Alternate Functions(64LQFP) (351)
Table9-3.GPIO Signals(64LQFP) (352)
Table9-4.GPIO Pad Configuration Examples (357)
Table9-5.GPIO Interrupt Configuration Example (358)
Table9-6.GPIO Register Map (359)
Table10-1.Available CCP Pins (398)
Table10-2.General-Purpose Timers Signals(64LQFP) (399)
Table10-3.16-Bit Timer With Prescaler Configurations (401)
Table10-4.Timers Register Map (408)
Table11-1.Watchdog Timer Register Map (433)
Table12-1.ADC Signals(64LQFP) (456)
Table12-2.Samples and FIFO Depth of Sequencers (457)
Table12-3.Differential Sampling Pairs (459)
Table12-4.ADC Register Map (463)
Table13-1.UART Signals(64LQFP) (492)
Table13-2.UART Register Map (499)
Table14-1.SSI Signals(64LQFP) (536)
Table14-2.SSI Register Map (547)
Table15-1.Controller Area Network Signals(64LQFP) (575)
Table15-2.CAN Protocol Ranges (588)
Table15-3.CANBIT Register Values (588)
Table15-4.CAN Register Map (592)
https://www.doczj.com/doc/e218942551.html,B Signals(64LQFP) (621)
Table16-2.Remainder(MAXLOAD/4) (633)
Table16-3.Actual Bytes Read (633)
Table16-4.Packet Sizes That Clear RXRDY (633)
Table16-5.Universal Serial Bus(USB)Controller Register Map (635)
Table17-1.PWM Signals(64LQFP) (720)
Table17-2.PWM Register Map (726)
Table19-1.Signals by Pin Number (763)
Table19-2.Signals by Signal Name (766)
Table19-3.Signals by Function,Except for GPIO (769)
Table19-4.GPIO Pins and Alternate Functions (772)
Table19-5.Connections for Unused Signals(64-pin LQFP) (773)
Table20-1.Temperature Characteristics (774)
Table20-2.Thermal Characteristics (774)
Table20-3.ESD Absolute Maximum Ratings (774)
Table21-1.Maximum Ratings (775)
Table21-2.Recommended DC Operating Conditions (775)
Table21-3.LDO Regulator Characteristics (776)
Table of Contents
Table21-4.GPIO Module DC Characteristics (776)
Table21-5.Detailed Power Specifications (777)
Table21-6.Flash Memory Characteristics (778)
Table21-7.Hibernation Module DC Characteristics (778)
https://www.doczj.com/doc/e218942551.html,B Controller DC Characteristics (778)
Table21-9.Phase Locked Loop(PLL)Characteristics (779)
Table21-10.Actual PLL Frequency (779)
Table21-11.Clock Characteristics (780)
Table21-12.Crystal Characteristics (780)
Table21-13.System Clock Characteristics with ADC Operation (781)
Table21-14.System Clock Characteristics with USB Operation (781)
Table21-15.JTAG Characteristics (781)
Table21-16.Reset Characteristics (782)
Table21-17.Sleep Modes AC Characteristics (784)
Table21-18.Hibernation Module AC Characteristics (784)
Table21-19.GPIO Characteristics (785)
Table21-20.ADC Characteristics (785)
Table21-21.ADC Module Internal Reference Characteristics (786)
Table21-22.SSI Characteristics (786)
Table D-1.Part Ordering Information (835)
Stellaris?LM3S5662Microcontroller
List of Registers
The Cortex-M3Processor (52)
Register1:Cortex General-Purpose Register0(R0) (59)
Register2:Cortex General-Purpose Register1(R1) (59)
Register3:Cortex General-Purpose Register2(R2) (59)
Register4:Cortex General-Purpose Register3(R3) (59)
Register5:Cortex General-Purpose Register4(R4) (59)
Register6:Cortex General-Purpose Register5(R5) (59)
Register7:Cortex General-Purpose Register6(R6) (59)
Register8:Cortex General-Purpose Register7(R7) (59)
Register9:Cortex General-Purpose Register8(R8) (59)
Register10:Cortex General-Purpose Register9(R9) (59)
Register11:Cortex General-Purpose Register10(R10) (59)
Register12:Cortex General-Purpose Register11(R11) (59)
Register13:Cortex General-Purpose Register12(R12) (59)
Register14:Stack Pointer(SP) (60)
Register15:Link Register(LR) (61)
Register16:Program Counter(PC) (62)
Register17:Program Status Register(PSR) (63)
Register18:Priority Mask Register(PRIMASK) (67)
Register19:Fault Mask Register(FAULTMASK) (68)
Register20:Base Priority Mask Register(BASEPRI) (69)
Register21:Control Register(CONTROL) (70)
Cortex-M3Peripherals (94)
Register1:SysTick Control and Status Register(STCTRL),offset0x010 (105)
Register2:SysTick Reload Value Register(STRELOAD),offset0x014 (107)
Register3:SysTick Current Value Register(STCURRENT),offset0x018 (108)
Register4:Interrupt0-31Set Enable(EN0),offset0x100 (109)
Register5:Interrupt32-47Set Enable(EN1),offset0x104 (110)
Register6:Interrupt0-31Clear Enable(DIS0),offset0x180 (111)
Register7:Interrupt32-47Clear Enable(DIS1),offset0x184 (112)
Register8:Interrupt0-31Set Pending(PEND0),offset0x200 (113)
Register9:Interrupt32-47Set Pending(PEND1),offset0x204 (114)
Register10:Interrupt0-31Clear Pending(UNPEND0),offset0x280 (115)
Register11:Interrupt32-47Clear Pending(UNPEND1),offset0x284 (116)
Register12:Interrupt0-31Active Bit(ACTIVE0),offset0x300 (117)
Register13:Interrupt32-47Active Bit(ACTIVE1),offset0x304 (118)
Register14:Interrupt0-3Priority(PRI0),offset0x400 (119)
Register15:Interrupt4-7Priority(PRI1),offset0x404 (119)
Register16:Interrupt8-11Priority(PRI2),offset0x408 (119)
Register17:Interrupt12-15Priority(PRI3),offset0x40C (119)
Register18:Interrupt16-19Priority(PRI4),offset0x410 (119)
Register19:Interrupt20-23Priority(PRI5),offset0x414 (119)
Register20:Interrupt24-27Priority(PRI6),offset0x418 (119)
Register21:Interrupt28-31Priority(PRI7),offset0x41C (119)
Register22:Interrupt32-35Priority(PRI8),offset0x420 (119)
Table of Contents
Register23:Interrupt36-39Priority(PRI9),offset0x424 (119)
Register24:Interrupt40-43Priority(PRI10),offset0x428 (119)
Register25:Interrupt44-47Priority(PRI11),offset0x42C (119)
Register26:Software Trigger Interrupt(SWTRIG),offset0xF00 (121)
Register27:CPU ID Base(CPUID),offset0xD00 (122)
Register28:Interrupt Control and State(INTCTRL),offset0xD04 (123)
Register29:Vector Table Offset(VTABLE),offset0xD08 (126)
Register30:Application Interrupt and Reset Control(APINT),offset0xD0C (127)
Register31:System Control(SYSCTRL),offset0xD10 (129)
Register32:Configuration and Control(CFGCTRL),offset0xD14 (131)
Register33:System Handler Priority1(SYSPRI1),offset0xD18 (133)
Register34:System Handler Priority2(SYSPRI2),offset0xD1C (134)
Register35:System Handler Priority3(SYSPRI3),offset0xD20 (135)
Register36:System Handler Control and State(SYSHNDCTRL),offset0xD24 (136)
Register37:Configurable Fault Status(FAULTSTAT),offset0xD28 (140)
Register38:Hard Fault Status(HFAULTSTAT),offset0xD2C (146)
Register39:Memory Management Fault Address(MMADDR),offset0xD34 (147)
Register40:Bus Fault Address(FAULTADDR),offset0xD38 (148)
Register41:MPU Type(MPUTYPE),offset0xD90 (149)
Register42:MPU Control(MPUCTRL),offset0xD94 (150)
Register43:MPU Region Number(MPUNUMBER),offset0xD98 (152)
Register44:MPU Region Base Address(MPUBASE),offset0xD9C (153)
Register45:MPU Region Base Address Alias1(MPUBASE1),offset0xDA4 (153)
Register46:MPU Region Base Address Alias2(MPUBASE2),offset0xDAC (153)
Register47:MPU Region Base Address Alias3(MPUBASE3),offset0xDB4 (153)
Register48:MPU Region Attribute and Size(MPUATTR),offset0xDA0 (155)
Register49:MPU Region Attribute and Size Alias1(MPUATTR1),offset0xDA8 (155)
Register50:MPU Region Attribute and Size Alias2(MPUATTR2),offset0xDB0 (155)
Register51:MPU Region Attribute and Size Alias3(MPUATTR3),offset0xDB8 (155)
System Control (170)
Register1:Device Identification0(DID0),offset0x000 (185)
Register2:Brown-Out Reset Control(PBORCTL),offset0x030 (187)
Register3:LDO Power Control(LDOPCTL),offset0x034 (188)
Register4:Raw Interrupt Status(RIS),offset0x050 (189)
Register5:Interrupt Mask Control(IMC),offset0x054 (190)
Register6:Masked Interrupt Status and Clear(MISC),offset0x058 (191)
Register7:Reset Cause(RESC),offset0x05C (192)
Register8:Run-Mode Clock Configuration(RCC),offset0x060 (193)
Register9:XTAL to PLL Translation(PLLCFG),offset0x064 (197)
Register10:GPIO High-Performance Bus Control(GPIOHBCTL),offset0x06C (198)
Register11:Run-Mode Clock Configuration2(RCC2),offset0x070 (200)
Register12:Main Oscillator Control(MOSCCTL),offset0x07C (202)
Register13:Deep Sleep Clock Configuration(DSLPCLKCFG),offset0x144 (203)
Register14:Device Identification1(DID1),offset0x004 (204)
Register15:Device Capabilities0(DC0),offset0x008 (206)
Register16:Device Capabilities1(DC1),offset0x010 (207)
Register17:Device Capabilities2(DC2),offset0x014 (209)
Register18:Device Capabilities3(DC3),offset0x018 (210)
Stellaris?LM3S5662Microcontroller Register19:Device Capabilities4(DC4),offset0x01C (212)
Register20:Device Capabilities5(DC5),offset0x020 (213)
Register21:Device Capabilities6(DC6),offset0x024 (214)
Register22:Device Capabilities7(DC7),offset0x028 (215)
Register23:Run Mode Clock Gating Control Register0(RCGC0),offset0x100 (217)
Register24:Sleep Mode Clock Gating Control Register0(SCGC0),offset0x110 (219)
Register25:Deep Sleep Mode Clock Gating Control Register0(DCGC0),offset0x120 (221)
Register26:Run Mode Clock Gating Control Register1(RCGC1),offset0x104 (223)
Register27:Sleep Mode Clock Gating Control Register1(SCGC1),offset0x114 (225)
Register28:Deep Sleep Mode Clock Gating Control Register1(DCGC1),offset0x124 (227)
Register29:Run Mode Clock Gating Control Register2(RCGC2),offset0x108 (229)
Register30:Sleep Mode Clock Gating Control Register2(SCGC2),offset0x118 (231)
Register31:Deep Sleep Mode Clock Gating Control Register2(DCGC2),offset0x128 (233)
Register32:Software Reset Control0(SRCR0),offset0x040 (235)
Register33:Software Reset Control1(SRCR1),offset0x044 (236)
Register34:Software Reset Control2(SRCR2),offset0x048 (237)
Hibernation Module (238)
Register1:Hibernation RTC Counter(HIBRTCC),offset0x000 (247)
Register2:Hibernation RTC Match0(HIBRTCM0),offset0x004 (248)
Register3:Hibernation RTC Match1(HIBRTCM1),offset0x008 (249)
Register4:Hibernation RTC Load(HIBRTCLD),offset0x00C (250)
Register5:Hibernation Control(HIBCTL),offset0x010 (251)
Register6:Hibernation Interrupt Mask(HIBIM),offset0x014 (254)
Register7:Hibernation Raw Interrupt Status(HIBRIS),offset0x018 (255)
Register8:Hibernation Masked Interrupt Status(HIBMIS),offset0x01C (256)
Register9:Hibernation Interrupt Clear(HIBIC),offset0x020 (257)
Register10:Hibernation RTC Trim(HIBRTCT),offset0x024 (258)
Register11:Hibernation Data(HIBDATA),offset0x030-0x12C (259)
Internal Memory (260)
Register1:ROM Control(RMCTL),offset0x0F0 (266)
Register2:Flash Memory Address(FMA),offset0x000 (267)
Register3:Flash Memory Data(FMD),offset0x004 (268)
Register4:Flash Memory Control(FMC),offset0x008 (269)
Register5:Flash Controller Raw Interrupt Status(FCRIS),offset0x00C (271)
Register6:Flash Controller Interrupt Mask(FCIM),offset0x010 (272)
Register7:Flash Controller Masked Interrupt Status and Clear(FCMISC),offset0x014 (273)
Register8:USec Reload(USECRL),offset0x140 (275)
Register9:Flash Memory Protection Read Enable0(FMPRE0),offset0x130and0x200 (276)
Register10:Flash Memory Protection Program Enable0(FMPPE0),offset0x134and0x400 (277)
Register11:User Debug(USER_DBG),offset0x1D0 (278)
Register12:User Register0(USER_REG0),offset0x1E0 (279)
Register13:User Register1(USER_REG1),offset0x1E4 (280)
Register14:User Register2(USER_REG2),offset0x1E8 (281)
Register15:User Register3(USER_REG3),offset0x1EC (282)
Register16:Flash Memory Protection Read Enable1(FMPRE1),offset0x204 (283)
Register17:Flash Memory Protection Read Enable2(FMPRE2),offset0x208 (284)
Register18:Flash Memory Protection Read Enable3(FMPRE3),offset0x20C (285)
Register19:Flash Memory Protection Program Enable1(FMPPE1),offset0x404 (286)
Table of Contents
Register20:Flash Memory Protection Program Enable2(FMPPE2),offset0x408 (287)
Register21:Flash Memory Protection Program Enable3(FMPPE3),offset0x40C (288)
Micro Direct Memory Access(μDMA) (289)
Register1:DMA Channel Source Address End Pointer(DMASRCENDP),offset0x000 (311)
Register2:DMA Channel Destination Address End Pointer(DMADSTENDP),offset0x004 (312)
Register3:DMA Channel Control Word(DMACHCTL),offset0x008 (313)
Register4:DMA Status(DMASTAT),offset0x000 (317)
Register5:DMA Configuration(DMACFG),offset0x004 (319)
Register6:DMA Channel Control Base Pointer(DMACTLBASE),offset0x008 (320)
Register7:DMA Alternate Channel Control Base Pointer(DMAALTBASE),offset0x00C (321)
Register8:DMA Channel Wait on Request Status(DMAWAITSTAT),offset0x010 (322)
Register9:DMA Channel Software Request(DMASWREQ),offset0x014 (323)
Register10:DMA Channel Useburst Set(DMAUSEBURSTSET),offset0x018 (324)
Register11:DMA Channel Useburst Clear(DMAUSEBURSTCLR),offset0x01C (326)
Register12:DMA Channel Request Mask Set(DMAREQMASKSET),offset0x020 (327)
Register13:DMA Channel Request Mask Clear(DMAREQMASKCLR),offset0x024 (329)
Register14:DMA Channel Enable Set(DMAENASET),offset0x028 (330)
Register15:DMA Channel Enable Clear(DMAENACLR),offset0x02C (332)
Register16:DMA Channel Primary Alternate Set(DMAALTSET),offset0x030 (333)
Register17:DMA Channel Primary Alternate Clear(DMAALTCLR),offset0x034 (335)
Register18:DMA Channel Priority Set(DMAPRIOSET),offset0x038 (336)
Register19:DMA Channel Priority Clear(DMAPRIOCLR),offset0x03C (338)
Register20:DMA Bus Error Clear(DMAERRCLR),offset0x04C (339)
Register21:DMA Peripheral Identification0(DMAPeriphID0),offset0xFE0 (341)
Register22:DMA Peripheral Identification1(DMAPeriphID1),offset0xFE4 (342)
Register23:DMA Peripheral Identification2(DMAPeriphID2),offset0xFE8 (343)
Register24:DMA Peripheral Identification3(DMAPeriphID3),offset0xFEC (344)
Register25:DMA Peripheral Identification4(DMAPeriphID4),offset0xFD0 (345)
Register26:DMA PrimeCell Identification0(DMAPCellID0),offset0xFF0 (346)
Register27:DMA PrimeCell Identification1(DMAPCellID1),offset0xFF4 (347)
Register28:DMA PrimeCell Identification2(DMAPCellID2),offset0xFF8 (348)
Register29:DMA PrimeCell Identification3(DMAPCellID3),offset0xFFC (349)
General-Purpose Input/Outputs(GPIOs) (350)
Register1:GPIO Data(GPIODATA),offset0x000 (361)
Register2:GPIO Direction(GPIODIR),offset0x400 (362)
Register3:GPIO Interrupt Sense(GPIOIS),offset0x404 (363)
Register4:GPIO Interrupt Both Edges(GPIOIBE),offset0x408 (364)
Register5:GPIO Interrupt Event(GPIOIEV),offset0x40C (365)
Register6:GPIO Interrupt Mask(GPIOIM),offset0x410 (366)
Register7:GPIO Raw Interrupt Status(GPIORIS),offset0x414 (367)
Register8:GPIO Masked Interrupt Status(GPIOMIS),offset0x418 (368)
Register9:GPIO Interrupt Clear(GPIOICR),offset0x41C (369)
Register10:GPIO Alternate Function Select(GPIOAFSEL),offset0x420 (370)
Register11:GPIO2-mA Drive Select(GPIODR2R),offset0x500 (372)
Register12:GPIO4-mA Drive Select(GPIODR4R),offset0x504 (373)
Register13:GPIO8-mA Drive Select(GPIODR8R),offset0x508 (374)
Register14:GPIO Open Drain Select(GPIOODR),offset0x50C (375)
Register15:GPIO Pull-Up Select(GPIOPUR),offset0x510 (376)
Stellaris?LM3S5662Microcontroller Register16:GPIO Pull-Down Select(GPIOPDR),offset0x514 (377)
Register17:GPIO Slew Rate Control Select(GPIOSLR),offset0x518 (378)
Register18:GPIO Digital Enable(GPIODEN),offset0x51C (379)
Register19:GPIO Lock(GPIOLOCK),offset0x520 (381)
Register20:GPIO Commit(GPIOCR),offset0x524 (382)
Register21:GPIO Analog Mode Select(GPIOAMSEL),offset0x528 (384)
Register22:GPIO Peripheral Identification4(GPIOPeriphID4),offset0xFD0 (385)
Register23:GPIO Peripheral Identification5(GPIOPeriphID5),offset0xFD4 (386)
Register24:GPIO Peripheral Identification6(GPIOPeriphID6),offset0xFD8 (387)
Register25:GPIO Peripheral Identification7(GPIOPeriphID7),offset0xFDC (388)
Register26:GPIO Peripheral Identification0(GPIOPeriphID0),offset0xFE0 (389)
Register27:GPIO Peripheral Identification1(GPIOPeriphID1),offset0xFE4 (390)
Register28:GPIO Peripheral Identification2(GPIOPeriphID2),offset0xFE8 (391)
Register29:GPIO Peripheral Identification3(GPIOPeriphID3),offset0xFEC (392)
Register30:GPIO PrimeCell Identification0(GPIOPCellID0),offset0xFF0 (393)
Register31:GPIO PrimeCell Identification1(GPIOPCellID1),offset0xFF4 (394)
Register32:GPIO PrimeCell Identification2(GPIOPCellID2),offset0xFF8 (395)
Register33:GPIO PrimeCell Identification3(GPIOPCellID3),offset0xFFC (396)
General-Purpose Timers (397)
Register1:GPTM Configuration(GPTMCFG),offset0x000 (409)
Register2:GPTM TimerA Mode(GPTMTAMR),offset0x004 (410)
Register3:GPTM TimerB Mode(GPTMTBMR),offset0x008 (412)
Register4:GPTM Control(GPTMCTL),offset0x00C (414)
Register5:GPTM Interrupt Mask(GPTMIMR),offset0x018 (417)
Register6:GPTM Raw Interrupt Status(GPTMRIS),offset0x01C (419)
Register7:GPTM Masked Interrupt Status(GPTMMIS),offset0x020 (420)
Register8:GPTM Interrupt Clear(GPTMICR),offset0x024 (421)
Register9:GPTM TimerA Interval Load(GPTMTAILR),offset0x028 (423)
Register10:GPTM TimerB Interval Load(GPTMTBILR),offset0x02C (424)
Register11:GPTM TimerA Match(GPTMTAMATCHR),offset0x030 (425)
Register12:GPTM TimerB Match(GPTMTBMATCHR),offset0x034 (426)
Register13:GPTM TimerA Prescale(GPTMTAPR),offset0x038 (427)
Register14:GPTM TimerB Prescale(GPTMTBPR),offset0x03C (428)
Register15:GPTM TimerA(GPTMTAR),offset0x048 (429)
Register16:GPTM TimerB(GPTMTBR),offset0x04C (430)
Watchdog Timer (431)
Register1:Watchdog Load(WDTLOAD),offset0x000 (435)
Register2:Watchdog Value(WDTVALUE),offset0x004 (436)
Register3:Watchdog Control(WDTCTL),offset0x008 (437)
Register4:Watchdog Interrupt Clear(WDTICR),offset0x00C (438)
Register5:Watchdog Raw Interrupt Status(WDTRIS),offset0x010 (439)
Register6:Watchdog Masked Interrupt Status(WDTMIS),offset0x014 (440)
Register7:Watchdog Test(WDTTEST),offset0x418 (441)
Register8:Watchdog Lock(WDTLOCK),offset0xC00 (442)
Register9:Watchdog Peripheral Identification4(WDTPeriphID4),offset0xFD0 (443)
Register10:Watchdog Peripheral Identification5(WDTPeriphID5),offset0xFD4 (444)
Register11:Watchdog Peripheral Identification6(WDTPeriphID6),offset0xFD8 (445)
Register12:Watchdog Peripheral Identification7(WDTPeriphID7),offset0xFDC (446)
Table of Contents
Register13:Watchdog Peripheral Identification0(WDTPeriphID0),offset0xFE0 (447)
Register14:Watchdog Peripheral Identification1(WDTPeriphID1),offset0xFE4 (448)
Register15:Watchdog Peripheral Identification2(WDTPeriphID2),offset0xFE8 (449)
Register16:Watchdog Peripheral Identification3(WDTPeriphID3),offset0xFEC (450)
Register17:Watchdog PrimeCell Identification0(WDTPCellID0),offset0xFF0 (451)
Register18:Watchdog PrimeCell Identification1(WDTPCellID1),offset0xFF4 (452)
Register19:Watchdog PrimeCell Identification2(WDTPCellID2),offset0xFF8 (453)
Register20:Watchdog PrimeCell Identification3(WDTPCellID3),offset0xFFC (454)
Analog-to-Digital Converter(ADC) (455)
Register1:ADC Active Sample Sequencer(ADCACTSS),offset0x000 (465)
Register2:ADC Raw Interrupt Status(ADCRIS),offset0x004 (466)
Register3:ADC Interrupt Mask(ADCIM),offset0x008 (467)
Register4:ADC Interrupt Status and Clear(ADCISC),offset0x00C (468)
Register5:ADC Overflow Status(ADCOSTAT),offset0x010 (469)
Register6:ADC Event Multiplexer Select(ADCEMUX),offset0x014 (470)
Register7:ADC Underflow Status(ADCUSTAT),offset0x018 (474)
Register8:ADC Sample Sequencer Priority(ADCSSPRI),offset0x020 (475)
Register9:ADC Processor Sample Sequence Initiate(ADCPSSI),offset0x028 (477)
Register10:ADC Sample Averaging Control(ADCSAC),offset0x030 (478)
Register11:ADC Sample Sequence Input Multiplexer Select0(ADCSSMUX0),offset0x040 (479)
Register12:ADC Sample Sequence Control0(ADCSSCTL0),offset0x044 (481)
Register13:ADC Sample Sequence Result FIFO0(ADCSSFIFO0),offset0x048 (484)
Register14:ADC Sample Sequence Result FIFO1(ADCSSFIFO1),offset0x068 (484)
Register15:ADC Sample Sequence Result FIFO2(ADCSSFIFO2),offset0x088 (484)
Register16:ADC Sample Sequence Result FIFO3(ADCSSFIFO3),offset0x0A8 (484)
Register17:ADC Sample Sequence FIFO0Status(ADCSSFSTAT0),offset0x04C (485)
Register18:ADC Sample Sequence FIFO1Status(ADCSSFSTAT1),offset0x06C (485)
Register19:ADC Sample Sequence FIFO2Status(ADCSSFSTAT2),offset0x08C (485)
Register20:ADC Sample Sequence FIFO3Status(ADCSSFSTAT3),offset0x0AC (485)
Register21:ADC Sample Sequence Input Multiplexer Select1(ADCSSMUX1),offset0x060 (486)
Register22:ADC Sample Sequence Input Multiplexer Select2(ADCSSMUX2),offset0x080 (486)
Register23:ADC Sample Sequence Control1(ADCSSCTL1),offset0x064 (487)
Register24:ADC Sample Sequence Control2(ADCSSCTL2),offset0x084 (487)
Register25:ADC Sample Sequence Input Multiplexer Select3(ADCSSMUX3),offset0x0A0 (489)
Register26:ADC Sample Sequence Control3(ADCSSCTL3),offset0x0A4 (490)
Universal Asynchronous Receivers/Transmitters(UARTs) (491)
Register1:UART Data(UARTDR),offset0x000 (500)
Register2:UART Receive Status/Error Clear(UARTRSR/UARTECR),offset0x004 (502)
Register3:UART Flag(UARTFR),offset0x018 (504)
Register4:UART IrDA Low-Power Register(UARTILPR),offset0x020 (506)
Register5:UART Integer Baud-Rate Divisor(UARTIBRD),offset0x024 (507)
Register6:UART Fractional Baud-Rate Divisor(UARTFBRD),offset0x028 (508)
Register7:UART Line Control(UARTLCRH),offset0x02C (509)
Register8:UART Control(UARTCTL),offset0x030 (511)
Register9:UART Interrupt FIFO Level Select(UARTIFLS),offset0x034 (513)
Register10:UART Interrupt Mask(UARTIM),offset0x038 (515)
Register11:UART Raw Interrupt Status(UARTRIS),offset0x03C (517)
Register12:UART Masked Interrupt Status(UARTMIS),offset0x040 (518)