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翻译日期： 2017.02.14
Design of the Temperature Control System Based on AT89C51
ABSTRACT
The principle and functions of the temperature control system based on micro controller AT89C51 are studied, and the temperature measurement unit consists of the 1-Wire bus digital temperature sensor DS18B20. The system can be expected to detect the preset temperature, display time and save monitoring data. An alarm will be given by system if the temperature exceeds the upper and lower limit value of the temperature which can be set discretionarily and then automatic control is achieved, thus the temperature is achieved monitoring intelligently within a certain range. Basing on principle of the system, it is easy to make a variety of other non-linear control systems so long as the software design is reasonably changed. The system has been proved to be accurate, reliable and satisfied through field practice. KEYWORDS: AT89C51; micro controller; DS18B20; temperature
1 INTRODUCTION
Temperature is a very important parameter in human life. In the modern society, temperature control (TC) is not only used in industrial production, but also widely used in other fields. With the improvement of the life quality, we can find the TC appliance in hotels, factories and home as well. And the trend that TC will better serve the whole society, so it is of great significance to measure and control the temperature. Based on the AT89C51 and temperature sensor DS18B20, this system controls the condition temperature intelligently. The temperature can be set discretionarily within a certain range. The system can show the time on LCD, and save monitoring data; and automatically control the temperature when the condition temperature exceeds the upper and lower limit value. By doing so it is to keep the temperature unchanged. The system is of high anti-jamming, high control precision and flexible design; it also fits the rugged environment. It is mainly used in people's life to improve the quality of the work and life. It is also versatile, so that it can be convenient to extend the use of the system. So the design is of profound importance. The general design, hardware design and software design of the system are covered.
1.1 Introduction
The 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically
used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device.
1.2 The AT89C51 provides the following standard features
4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duple ser-ial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the
RAM contents but freezes the oscil–lator disabling all other chip functions until the next hardware reset.
1.3Pin Description
VCC Supply voltage.
GND Ground.
Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull ups are required during program verification.
Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output buffers can sink/so -urce four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals durin Flash programming and verification.
Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/sou -rce four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port
3 pins that are externally being pulled low will source current (IIL) because of the pull ups.
Port 3 also serves the functions of various special features of the AT89C51 as listed below:
RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped duri-ng each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN：Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin alsreceives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.
XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2 ：Output from the inverting oscillator amplifier. Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
Power-down Mode
In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRS but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. The AT89C51 code memory array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.
2 Programming Algorithm
Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written
Statistical hypothesis testing Adriana Albu，Loredana Ungureanu Politehnica University Timisoara,adrianaa@aut.utt.ro Politehnica University Timisoara,loredanau@aut.utt.ro Abstract In this article,we present a Bayesian statistical hypothesis testing inspection, testing theory and the process Mentioned hypothesis testing in the real world and the importance of, and successful test of the Notes. Key words Bayesian hypothesis testing; Bayesian inference;Test of significance Introduction A statistical hypothesis test is a method of making decisions using data, whether from a controlled experiment or an observational study (not controlled). In statistics, a result is called statistically significant if it is unlikely to have occurred by chance alone, according to a pre-determined threshold probability, the significance level. The phrase "test of significance" was coined by Ronald Fisher: "Critical tests of this kind may be called tests of significance, and when such tests are available we may discover whether a second sample is or is not significantly different from the first."[1] Hypothesis testing is sometimes called confirmatory data analysis, in contrast to exploratory data analysis. In frequency probability,these decisions are almost always made using null-hypothesis tests. These are tests that answer the question Assuming that the null hypothesis is true, what is the probability of observing a value for the test statistic that is at [] least as extreme as the value that was actually observed?) 2 More formally, they represent answers to the question, posed before undertaking an experiment,of what outcomes of the experiment would lead to rejection of the null hypothesis for a pre-specified probability of an incorrect rejection. One use of hypothesis testing is deciding whether experimental results contain enough information to cast doubt on conventional wisdom. Statistical hypothesis testing is a key technique of frequentist statistical inference. The Bayesian approach to hypothesis testing is to base rejection of the hypothesis on the posterior probability.[3][4]Other approaches to reaching a decision based on data are available via decision theory and optimal decisions. The critical region of a hypothesis test is the set of all outcomes which cause the null hypothesis to be rejected in favor of the alternative hypothesis. The critical region is usually denoted by the letter C. One-sample tests are appropriate when a sample is being compared to the population from a hypothesis. The population characteristics are known from theory or are calculated from the population.
外文翻译 专业机械设计制造及其自动化学生姓名刘链柱 班级机制111 学号1110101102 指导教师葛友华
外文资料名称： Design and performance evaluation of vacuum cleaners using cyclone technology 外文资料出处：Korean J. Chem. Eng., 23(6), (用外文写) 925-930 (2006) 附件： 1.外文资料翻译译文 2.外文原文
应用旋风技术真空吸尘器的设计和性能介绍 吉尔泰金，洪城铱昌，宰瑾李， 刘链柱译 摘要：旋风型分离器技术用于真空吸尘器 - 轴向进流旋风和切向进气道流旋风有效地收集粉尘和降低压力降已被实验研究。优化设计等因素作为集尘效率，压降，并切成尺寸被粒度对应于分级收集的50％的效率进行了研究。颗粒切成大小降低入口面积，体直径，减小涡取景器直径的旋风。切向入口的双流量气旋具有良好的性能考虑的350毫米汞柱的低压降和为1.5μm的质量中位直径在1米3的流量的截止尺寸。一使用切向入口的双流量旋风吸尘器示出了势是一种有效的方法，用于收集在家庭中产生的粉尘。 摘要及关键词：吸尘器; 粉尘; 旋风分离器 引言 我们这个时代的很大一部分都花在了房子，工作场所，或其他建筑，因此，室内空间应该是既舒适情绪和卫生。但室内空气中含有超过室外空气因气密性的二次污染物，毒物，食品气味。这是通过使用产生在建筑中的新材料和设备。真空吸尘器为代表的家电去除有害物质从地板到地毯所用的商用真空吸尘器房子由纸过滤，预过滤器和排气过滤器通过洁净的空气排放到大气中。虽然真空吸尘器是方便在使用中，吸入压力下降说唱空转成比例地清洗的时间，以及纸过滤器也应定期更换，由于压力下降，气味和细菌通过纸过滤器内的残留粉尘。 图1示出了大气气溶胶的粒度分布通常是双峰形，在粗颗粒（>2.0微米）模式为主要的外部来源，如风吹尘，海盐喷雾，火山，从工厂直接排放和车辆废气排放，以及那些在细颗粒模式包括燃烧或光化学反应。表1显示模式，典型的大气航空的直径和质量浓度溶胶被许多研究者测量。精细模式在0.18?0.36 在5.7到25微米尺寸范围微米尺寸范围。质量浓度为2?205微克，可直接在大气气溶胶和 3.85至36.3μg/m3柴油气溶胶。
Inventory management Inventory Control On the so-called "inventory control", many people will interpret it as a "storage management", which is actually a big distortion. The traditional narrow view, mainly for warehouse inventory control of materials for inventory, data processing, storage, distribution, etc., through the implementation of anti-corrosion, temperature and humidity control means, to make the custody of the physical inventory to maintain optimum purposes. This is just a form of inventory control, or can be defined as the physical inventory control. How, then, from a broad perspective to understand inventory control? Inventory control should be related to the company's financial and operational objectives, in particular operating cash flow by optimizing the entire demand and supply chain management processes (DSCM), a reasonable set of ERP control strategy, and supported by appropriate information processing tools, tools to achieved in ensuring the timely delivery of the premise, as far as possible to reduce inventory levels, reducing inventory and obsolescence, the risk of devaluation. In this sense, the physical inventory control to achieve financial goals is just a means to control the entire inventory or just a necessary part; from the perspective of organizational functions, physical inventory control, warehouse management is mainly the responsibility of The broad inventory control is the demand and supply chain management, and the whole company's responsibility. Why until now many people's understanding of inventory control, limited physical inventory control? The following two reasons can not be ignored: First, our enterprises do not attach importance to inventory control. Especially those who benefit relatively good business, as long as there is money on the few people to consider the problem of inventory turnover. Inventory control is simply interpreted as warehouse management, unless the time to spend money, it may have been to see the inventory problem, and see the results are often very simple procurement to buy more, or did not do warehouse departments . Second, ERP misleading. Invoicing software is simple audacity to call it ERP, companies on their so-called ERP can reduce the number of inventory, inventory control, seems to rely on their small software can get. Even as SAP, BAAN ERP world, the field of
吉林化工学院理学院 毕业论文外文翻译English Title（Times New Roman ，三号） 学生学号：08810219 学生姓名：袁庚文 专业班级：信息与计算科学0802 指导教师：赵瑛 职称副教授 起止日期：2012.2.27～2012.3.14 吉林化工学院 Jilin Institute of Chemical Technology
1 外文翻译的基本内容 应选择与本课题密切相关的外文文献（学术期刊网上的），译成中文，与原文装订在一起并独立成册。在毕业答辩前，同论文一起上交。译文字数不应少于3000个汉字。 2 书写规范 2.1 外文翻译的正文格式 正文版心设置为：上边距：3.5厘米，下边距：2.5厘米，左边距：3.5厘米，右边距：2厘米，页眉：2.5厘米，页脚：2厘米。 中文部分正文选用模板中的样式所定义的“正文”，每段落首行缩进2字；或者手动设置成每段落首行缩进2字，字体：宋体，字号：小四，行距：多倍行距1.3，间距：前段、后段均为0行。 这部分工作模板中已经自动设置为缺省值。 2.2标题格式 特别注意：各级标题的具体形式可参照外文原文确定。 1．第一级标题（如：第1章绪论）选用模板中的样式所定义的“标题1”，居左；或者手动设置成字体：黑体，居左，字号：三号，1.5倍行距，段后11磅，段前为11磅。 2．第二级标题（如：1.2 摘要与关键词）选用模板中的样式所定义的“标题2”，居左；或者手动设置成字体：黑体，居左，字号：四号，1.5倍行距，段后为0，段前0.5行。 3．第三级标题（如：1.2.1 摘要）选用模板中的样式所定义的“标题3”，居左；或者手动设置成字体：黑体，居左，字号：小四，1.5倍行距，段后为0，段前0.5行。 标题和后面文字之间空一格（半角）。 3 图表及公式等的格式说明 图表、公式、参考文献等的格式详见《吉林化工学院本科学生毕业设计说明书（论文）撰写规范及标准模版》中相关的说明。
外文文献： Knowledge of the stepper motor What is a stepper motor： Stepper motor is a kind of electrical pulses into angular displacement of the implementing agency. Popular little lesson: When the driver receives a step pulse signal, it will drive a stepper motor to set the direction of rotation at a fixed angle (and the step angle). You can control the number of pulses to control the angular displacement, so as to achieve accurate positioning purposes; the same time you can control the pulse frequency to control the motor rotation speed and acceleration, to achieve speed control purposes. What kinds of stepper motor sub-： In three stepper motors: permanent magnet (PM), reactive (VR) and hybrid (HB) permanent magnet stepper usually two-phase, torque, and smaller, step angle of 7.5 degrees or the general 15 degrees; reaction step is generally three-phase, can achieve high torque output, step angle of 1.5 degrees is generally, but the noise and vibration are large. 80 countries in Europe and America have been eliminated; hybrid stepper is a mix of permanent magnet and reactive advantages. It consists of two phases and the five-phase: two-phase step angle of 1.8 degrees while the general five-phase step angle of 0.72 degrees generally. The most widely used Stepper Motor. What is to keep the torque (HOLDING TORQUE) How much precision stepper motor? Whether the cumulative： The general accuracy of the stepper motor step angle of 3-5%, and not cumulative.
使用高级分析法的钢框架创新设计 1．导言 在美国，钢结构设计方法包括允许应力设计法(ASD)，塑性设计法(PD)和荷载阻力系数设计法(LRFD)。在允许应力设计中，应力计算基于一阶弹性分析，而几何非线性影响则隐含在细部设计方程中。在塑性设计中，结构分析中使用的是一阶塑性铰分析。塑性设计使整个结构体系的弹性力重新分配。尽管几何非线性和逐步高产效应并不在塑性设计之中，但它们近似细部设计方程。在荷载和阻力系数设计中，含放大系数的一阶弹性分析或单纯的二阶弹性分析被用于几何非线性分析，而梁柱的极限强度隐藏在互动设计方程。所有三个设计方法需要独立进行检查，包括系数K计算。在下面，对荷载抗力系数设计法的特点进行了简要介绍。 结构系统内的内力及稳定性和它的构件是相关的，但目前美国钢结构协会（AISC）的荷载抗力系数规范把这种分开来处理的。在目前的实际应用中，结构体系和它构件的相互影响反映在有效长度这一因素上。这一点在社会科学研究技术备忘录第五录摘录中有描述。 尽管结构最大内力和构件最大内力是相互依存的（但不一定共存），应当承认，严格考虑这种相互依存关系，很多结构是不实际的。与此同时，众所周知当遇到复杂框架设计中试图在柱设计时自动弥补整个结构的不稳定（例如通过调整柱的有效长度）是很困难的。因此，社会科学研究委员会建议在实际设计中，这两方面应单独考虑单独构件的稳定性和结构的基础及结构整体稳定性。图28.1就是这种方法的间接分析和设计方法。
在目前的美国钢结构协会荷载抗力系数规范中，分析结构体系的方法是一阶弹性分析或二阶弹性分析。在使用一阶弹性分析时，考虑到二阶效果，一阶力矩都是由B1,B2系数放大。在规范中，所有细部都是从结构体系中独立出来，他们通过细部内力曲线和规范给出的那些隐含二阶效应，非弹性，残余应力和挠度的相互作用设计的。理论解答和实验性数据的拟合曲线得到了柱曲线和梁曲线，同时Kanchanalai发现的所谓“精确”塑性区解决方案的拟合曲线确定了梁柱相互作用方程。 为了证明单个细部内力对整个结构体系的影响，使用了有效长度系数，如图28.2所示。有效长度方法为框架结构提供了一个良好的设计。然而，有效长度方法的
软件专业毕业论文外文文献中英文翻译 Object landscapes and lifetimes Tech nically, OOP is just about abstract data typing, in herita nee, and polymorphism, but other issues can be at least as importa nt. The rema in der of this sect ion will cover these issues. One of the most importa nt factors is the way objects are created and destroyed. Where is the data for an object and how is the lifetime of the object con trolled? There are differe nt philosophies at work here. C++ takes the approach that con trol of efficie ncy is the most importa nt issue, so it gives the programmer a choice. For maximum run-time speed, the storage and lifetime can be determined while the program is being written, by placing the objects on the stack (these are sometimes called automatic or scoped variables) or in the static storage area. This places a priority on the speed of storage allocatio n and release, and con trol of these can be very valuable in some situati ons. However, you sacrifice flexibility because you must know the exact qua ntity, lifetime, and type of objects while you're writing the program. If you are trying to solve a more general problem such as computer-aided desig n, warehouse man ageme nt, or air-traffic con trol, this is too restrictive. The sec ond approach is to create objects dyn amically in a pool of memory called the heap. In this approach, you don't know un til run-time how many objects you n eed, what their lifetime is, or what their exact type is. Those are determined at the spur of the moment while the program is runnin g. If you n eed a new object, you simply make it on the heap at the point that you n eed it. Because the storage is man aged dyn amically, at run-time, the amount of time required to allocate storage on the heap is sig ni fica ntly Ion ger tha n the time to create storage on the stack. (Creat ing storage on the stack is ofte n a si ngle assembly in structio n to move the stack poin ter dow n, and ano ther to move it back up.) The dyn amic approach makes the gen erally logical assumpti on that objects tend to be complicated, so the extra overhead of finding storage and releas ing that storage will not have an importa nt impact on the creati on of an object .In additi on, the greater flexibility is esse ntial to solve the gen eral program ming problem. Java uses the sec ond approach, exclusive". Every time you want to create an object, you use the new keyword to build a dyn amic in sta nee of that object. There's ano ther issue, however, and that's the lifetime of an object. With Ian guages that allow objects to be created on the stack, the compiler determines how long the object lasts and can automatically destroy it. However, if you create it on the heap the compiler has no kno wledge of its lifetime. In a Ianguage like C++, you must determine programmatically when to destroy the
at89c52单片机简介 中英文资料对照外文翻译文献综述 A T89C52 Single-chip microprocessor introduction Selection of Single-chip microprocessor 1. Development of Single-chip microprocessor The main component part of Single-chip microprocessor as a result of by such centralize to be living to obtain on the chip，In immediate future middle processor CPU。Storage RAM immediately﹑memoy read ROM﹑Interrupt system、Timer /'s counter along with I/O's rim electric circuit awaits the main microcomputer section，The lumping is living on the chip。Although the Single-chip microprocessor r is only a chip，Yet through makes up and the meritorous service be able to on sees，It had haveed the calculating machine system property，calling it for this reason act as Single-chip microprocessor r minisize calculating machine SCMS and abbreviate the Single-chip microprocessor。 1976Year the Inter corporation put out 8 MCS－48Set Single-chip microprocessor computer，After being living more than 20 years time in development that obtain continuously and wide-ranging application。1980Year that corporation put out high performance MCS －51Set Single-chip microprocessor。This type of Single-chip microprocessor meritorous service capacity、The addressing range wholly than early phase lift somewhat，Use also comparatively far more at the moment。1982Year that corporation put out the taller 16 Single-chip microprocessor MCS of performance once
毕业论文（设计）外文翻译 题目：中国上市公司偏好股权融资：非制度性因素 系部名称：经济管理系专业班级:会计082班 学生姓名：任民学号： 200880444228 指导教师：冯银波教师职称:讲师 年月日
译文： 中国上市公司偏好股权融资：非制度性因素 国际商业管理杂志 2009.10 摘要：本文把重点集中于中国上市公司的融资活动，运用西方融资理论，从非制度性因素方面，如融资成本、企业资产类型和质量、盈利能力、行业因素、股权结构因素、财务管理水平和社会文化，分析了中国上市公司倾向于股权融资的原因，并得出结论，股权融资偏好是上市公司根据中国融资环境的一种合理的选择。最后，针对公司的股权融资偏好提出了一些简明的建议。 关键词：股权融资，非制度性因素，融资成本 一、前言 中国上市公司偏好于股权融资，根据中国证券报的数据显示，1997年上市公司在资本市场的融资金额为95.87亿美元，其中股票融资的比例是72.5％，，在1998年和1999年比例分别为72.6％和72.3％，另一方面，债券融资的比例分别是17.8％，24.9％和25.1％。在这三年，股票融资的比例，在比中国发达的资本市场中却在下跌。以美国为例，当美国企业需要的资金在资本市场上，于股权融资相比他们宁愿选择债券融资。统计数据显示，从1970年到1985年，美日企业债券融资占了境外融资的91.7％，比股权融资高很多。阎达五等发现，大约中国3/4的上市公司偏好于股权融资。许多研究的学者认为，上市公司按以下顺序进行外部融资：第一个是股票基金，第二个是可转换债券，三是短期债务，最后一个是长期负债。许多研究人员通常分析我国上市公司偏好股权是由于我们国家的经济改革所带来的制度性因素。他们认为，上市公司的融资活动违背了西方古典融资理论只是因为那些制度性原因。例如，优序融资理论认为，当企业需要资金时，他们首先应该转向内部资金（折旧和留存收益），然后再进行债权融资，最后的选择是股票融资。在这篇文章中，笔者认为，这是因为具体的金融环境激活了企业的这种偏好，并结合了非制度性因素和西方金融理论，尝试解释股权融资偏好的原因。
1. Introduction America is one of the countries that speak English. Because of the special North American culture, developing history and the social environment, American English has formed its certain unique forms and the meaning. Then it turned into American English that has the special features of the United States. American English which sometimes also called United English or U.S English is the form of the English language that used widely in the United States .As the rapid development of American economy, and its steady position and strong power in the world, American English has become more and more widely used. As in 2005, more than two-thirds of English native speakers use various forms of American English. The philologists of the United States had divided the English of the United States into four major types: “America n creating”; “Old words given the new meaning”; “Words that eliminated by English”;“The phonetic foreign phrases and the languages that are not from the English immigrates”[1]. Compared to the other languages, American English is much simple on word spelling, usage and grammar, and it is one of the reasons that American English is so popular in the world. The thesis analyzes the differences between American English and British English. With the main part, it deals with the development of American English, its peculiarities compared to that of British English, its causes and tendency. 2. Analyses the Differences As we English learners, when we learning English in our junior or senior school, we already came across some words that have different spellings, different pronunciations or different expressions, which can be represented by following contrasted words: spellings in "color" vs. "colour"; pronunciations in "sec-re-ta-ry" vs. "sec-re-try";
Advantages of Managed Code Microsoft intermediate language shares with Java byte code the idea that it is a low-level language witha simple syntax , which can be very quickly translated intonative machine code. Having this well-defined universal syntax for code has significant advantages. Platform independence First, it means that the same file containing byte code instructions can be placed on any platform; atruntime the final stage of compilation can then be easily accomplished so that the code will run on thatparticular platform. In other words, by compiling to IL we obtain platform independence for .NET, inmuch the same way as compiling to Java byte code gives Java platform independence. Performance improvement IL is actually a bit more ambitious than Java bytecode. IL is always Just-In-Time compiled (known as JIT), whereas Java byte code was ofteninterpreted. One of the disadvantages of Java was that, on execution, the process of translating from Javabyte code to native executable resulted in a loss of performance. Instead of compiling the entire application in one go (which could lead to a slow start-up time), the JITcompiler simply compiles each portion of code as it is called (just-in-time). When code has been compiled.once, the resultant native executable is stored until the application exits, so that it does not need to berecompiled the next time that portion of code is run. Microsoft argues that this process is more efficientthan compiling the entire application code at the start, because of the likelihood that large portions of anyapplication code will not actually be executed in any given run. Using the JIT compiler, such code willnever be compiled.
本科毕业设计（论文）中英文对照翻译 院（系部）电气工程与自动化 专业名称电子信息工程 年级班级 04级7班 学生姓名 指导老师
Infrared Remote Control System Abstract Red outside data correspondence the technique be currently within the scope of world drive extensive usage of a kind of wireless conjunction technique,drive numerous hardware and software platform support. Red outside the transceiver product have cost low, small scaled turn, the baud rate be quick, point to point SSL, be free from electromagnetism thousand Raos etc.characteristics, can realization information at dissimilarity of the product fast, convenience, safely exchange and transmission, at short distance wireless deliver aspect to own very obvious of advantage.Along with red outside the data deliver a technique more and more mature, the cost descend, red outside the transceiver necessarily will get at the short distance communication realm more extensive of application. The purpose that design this system is transmit cu stomer’s operation information with infrared rays for transmit media, then demodulate original signal with receive circuit. It use coding chip to modulate signal and use decoding chip to demodulate signal. The coding chip is PT2262 and decoding chip is PT2272. Both chips are made in Taiwan. Main work principle is that we provide to input the information for the PT2262 with coding keyboard. The input information was coded by PT2262 and loading to high frequent load wave whose frequent is 38 kHz, then modulate infrared transmit dioxide and radiate space outside when it attian enough power. The receive circuit receive the signal and demodulate original information. The original signal was decoded by PT2272, so as to drive some circuit to accomplish