1
ICLab
ICLab Layout
Fully Custom IC Design Flow
HSPICE Laker Calibre Calibre Calibre HSPICE
Composer
2
ICLab
ICLab Layout
IC Fabrication Process Overview
Wafer : 200 ~ 300 mm in diameter and about 0.35 ~ 1.25 mm thick Process steps : 20 ~ 30
Layout
Masks
Wafers
Chemicals
Fabrication
Processed wafer
Chips
Oxidation
Etch
Ion
implantation
Diffusion
Chemical vapor deposition
3
ICLab
ICLab Layout
IC Photolithographic Process
Apply material to wafer to be patterned
Spin on positive photoresist
Pattern photoresist with UV light through glass mask
Etch and apply specific processing step
Wash off photoresist
Wafer
Material Patterned
material
Material
Photoresist Soluble
photoresist
UV light Glass mask
Chrome pattern Etch away unwanted
material
4ICLab
ICLab Layout CMOS P-Substrate Process Flow
Cross section view
NMOS process steps
Active region, poly gate, p+/n+ implant, metal contact/line PMOS process steps
N well, active region, poly gate, p+/n+ implant, metal contact/line
p substrate
Substrate Well
5ICLab
ICLab Layout
N well
Active region
NWELL layer (NW)
DIFF layer (OD)
p substrate
p substrate
Well Contact
6ICLab
ICLab Layout
Poly gate (self-aligned gate)
POLY1 layer (PO)
p substrate
p substrate
7ICLab
ICLab Layout
P+/N+ implant
PIMP layer (PP)
NIMP layer (NP)
p substrate
p
p p
p substrate
n
p substrate
Polycide: silicide on poly
Salicide: self-aligned silicide on drain/source
8ICLab
ICLab Layout
Metal contacts/lines
CONT layer (CO)
METAL1 layer (M1)
p substrate
Contact widows
P substrate
G
Well D
S
Metal: Al or Cu
Metal vias/lines VIA12 layer (VIA1)
METAL2 layer (M2)
P substrate
Via widows P substrate
9ICLab
ICLab Layout
10
ICLab
ICLab Layout Tolerate nonideal effects and guarantee device successful fabrication
Mask alignment error
Ex: alignment of N well and active region masks
p substrate
p substrate
p substrate
p substrate
11
ICLab
ICLab Layout
Exposure and etching variation
Ex: different contact windows
different contact resistance
Two types of design rules
P substrate
Contact widows
Minimum width Poly overlap
Poly-contact spacing Contact overlap Resolution
Alignment
Minimum channel width CO.W.1 + 2 × CO.E.1 Minimize S/D diffusion width (x d)
CO.W.1 + CO.E.1 + CO.C.1
x
d
x
d
12ICLab
ICLab Layout
Layout v.s. Schematic (LVS)
Guarantee the fabricated circuits is the same as the simulated one Check device parameters
Model name
Channel width
Channel length
VDD
VO
VI
GND
13ICLab
ICLab Layout
14
ICLab
ICLab Layout
Parasitic Extraction (PEX)
Evaluate interconnection RC
effects
VI VO
Only C effect
Only R effect
GND
VI VO
CMOS static logic
Noise insensitive
Use substrate/well contact to provide
body bias voltage
Substrate/well contact needed but not
important Analog circuits
Noise sensitive
Use substrate/well contact to absorb
noise and provide body bias voltage
Guard ring
Well contact
Substrate contact
Guard ring
(Avoid any
current flows
through it)
15ICLab
ICLab Layout
CMOS static logic
Noise insensitive
Share N well for adjacent devices
Reduce area Analog circuits
Noise sensitive
Separate N well for adjacent devices
Reduce coupling effect
16ICLab
ICLab Layout
17ICLab
ICLab Layout
CMOS static logic
Only consider RC delay
Use minimum metal width
Analog circuits
Metal width is decided by
Current density
o Ex: 1 mA/μm for M1 Parasitic resistance
o Ex: M1 < 0.13 ?/square
Parasitic capacitance
o Ex: M1-Sub (0.4 μm width)
~ 0.073 fF/μ
m
||| RC constant
18ICLab
ICLab Layout
CMOS static logic
Contact/Via resistance is minor effect
in RC delay
One contact/via can be used .
Analog circuits
Contact/Via resistance may degrade
circuit performance
At least two contact/via Current density
Ex: 0.6 mA/via for VIA12
P substrate
Contact widows
OD CO M1
19ICLab
ICLab Layout Capacitance
Capacitance types
Area - Area ∝ area (W ×L ), 1/distance (1/d 2) Fringe - Area ∝ length (L ), 1/distance (1/d 2) Fringe - Fringe
∝ length (L ),
1/distance (1/d 1)
20ICLab
ICLab Layout Double-Poly Capacitors
Poly1-Poly2 capacitor
EX: C a = 864 aF/μm 2
C f
= 0.89 aF/μm
P substrate
)
22(L W C L W C C f a total +×+××=POLY2 layer (PO2)