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Controlled Part-To-Substrate Micro-Assembly Via Electrochemical Modulation of Surface Energ

Controlled Part-To-Substrate Micro-Assembly Via Electrochemical Modulation of Surface Energ
Controlled Part-To-Substrate Micro-Assembly Via Electrochemical Modulation of Surface Energ

CONTROLLED PART-TO-SUBSTRATE MICRO-ASSEMBLY VIA

ELECTROCHEMICAL MODULATION OF SURFACE ENERGY Xiaorong Xiong*, Yael Hanein*, Weihua Wang**, Daniel T. Schwartz** and Karl F. B?hringer* *Electrical Engineering Department, **Chemical Engineering Department

University of Washington, Seattle, WA 98195-2500, USA

ABSTRACT

A process designed for repeated parallel micro-assembly has been achieved by controlling the hydro-phobicity of the binding sites between micro-parts and substrates. Active assembly sites consist of hydrophobic surfaces made of alkanethiol-coated gold, while inactive sites are clean, hydrophilic gold surfaces. Electrochemi-cal reduction of the alkanethiolate monolayer on sub-strates with addressable binding sites returns the se-lected sites to their inactive, hydrophilic state. The parts are attracted, aligned, and anchored to the binding sites by a heat curable lubricant in an aqueous environment. The entire sequence is then repeated with a different set of active binding sites and parts. A two-batch assembly process is described in this paper. Principles for estab-lishing electrical connections using electroplating are also demonstrated and discussed. This process forms the basis for a general technique to batch-assemble complex microstructures from simple components.

Keywords: self-assembly, micro-assembly, hydropho-bic, surface modulation.

INTRODUCTION

Recent developments in micro electro mechanical sys-tems (MEMS) research offer the prospects to produce complex systems with a wide range of functionalities (mechanical, electrical, optical, chemical, etc.). Mono-lithic integration of such systems is often limited by the poor compatibility between their fabrication processes. Recently, a number of techniques have been developed to assemble components into complex systems [1-6]. Conventional “pick and place” serial assembly methods [2] use miniaturized robots and tools for organizing parts. Such serial assembly strategies are rather limited when a large number of parts must be assembled, due to the large number of required manipulators. In order to accomplish efficient micro-assembly, two classes of parallel assembly approaches have emerged: determinis-tic and stochastic. In the first class, assembly is achieved by transferring microstructures between aligned wafers [3]. In stochastic parallel micro-assembly, parts are assembled in a random manner, and a large number of parts are supplied to the process in order to obtain good yield. Various driving forces have been employed for stochastic assembly. Yeh and Smith developed a process to assemble trapezoidal micro-components into complementary holes in substrates using fluidic flow and gravitation [4]. Srinivasan et al. adopted the surface tension driven assembly technique first described by Whitesides and coworkers [5] to as-semble microscopic parts onto silicon and quartz sub-strates [6]. This approach has accomplished massively parallel assembly of equal micro parts with sub-micrometer precision.

In this paper, a new multi-step parallel micro-assembly technique is presented. As in [6], the driving force for the assembly is surface tension. By controlling the hy-drophobicity of the binding sites the process can be re-peated and multiple batches of micro-components can be organized onto desired sites on a single substrate. Electroplating is explored as a post assembly process to establish electrical connections for active components such as surface mount light emitting diodes (LEDs).

PRINCIPLE AND APPROACH Figure 1 illustrates the schematic flow of our microas-sembly approach. Substrate and parts are fabricated with exposed clean hydrophilic gold patterns. When both the parts and substrate are soaked in ethanolic alkanethiol solution, a hydrophobic alkanethiolate self-assembled monolayer (SAM) is formed on gold patterns. This is the result of adsorption of alkanethiol organosulfur compounds on noble metals such as gold. The remain-ing areas on the substrate remain hydrophilic. The abil-ity to electrochemically desorb alkanethiolate SAM from gold [7,8], i.e., CH3(CH2)n SAu + e–→Au + CH3(CH2)n S– provides in-situ control of hydrophobic-ity. Thus, assembly can be controlled to occur only at sites without SAM desorption. The hydrophilic gold sites on the substrate can be reserved for future assem-bly. By repeating the SAM adsorption and assembly process, another batch of micro-components can be as-sembled in those regions.

In the assembly step, a hydrocarbon-based lubricant is spread on the substrate before it is immersed in water. The lubricant, which wets only the hydrophobic patterns in water, reduces friction, increases the capillary forces, and thus produces alignment between parts and sub-strate (Figure 1d). Detailed information about the multi-batch micro-assembly process is described in the fol-lowing experimental section.

Figure 1. Schematics of assembly steps: (a) Substrate with electrically isolated regions of gold sites. (b) SAM ad-sorption on all gold patterns. (c) Selective SAM desorption by cyclic voltammetry (CV). On the right regions, SAM is removed from the gold pattern by electrochemical modulation. (d) Lubricant spread and assembly.

EXPERIMENTAL

Substrates and Parts Preparation

The substrate is prepared by sputtering 1100? TiW/Au on a 3″ (100) Si wafer with a thermal oxidation layer of approximately 4000?. The wafer is patterned with elec-trically isolated gold stripes in a lift-off process. Then a passivation layer of spin-on glass (SOG) (311, Honey-well) is patterned by photolithography and reactive ion etching (RIE) until gold squares (1 by 1mm) on the stripes are exposed (Figure 2a,b). Sputtered silicon ni-tride and silicon dioxide have been shown to be com-patible for our microassembly process. Square test parts (1 by 1mm) are fabricated by dicing 3″ (100) Si wafers

with sputtered Cr/Au as thick as 1100?

(Figure 2).

Figure 2. Fabricated part and substrate (a) Cross-section of part and substrate. (b) Top view of a fabri-cated substrate.

Alkanethiolate SAMs are deposited on exposed gold by soaking the substrates and the parts in 1mM ethanolic alkanethiol solution for two to twenty-four hours. The substrate is cleaned by O 2 plasma for two minutes be-fore being immersed into the ethanolic alkanethiol solu-tion.

SAM Desorption Characterization and Optimization Reductive desorption of SAMs is performed in a con-ventional three-electrode electrochemical cell (Figure 3). The counter electrode is a platinum mesh. A satu-rated calomel electrode (SCE) is used as the reference electrode. The working electrodes are test samples. The electrolyte is 0.5 M aqueous KOH solution. Cyclic volt-ammetry (i.e., the repeated scanning of the working electrode potential) was performed to both characterize

and to desorb SAMs from electrode surfaces [8]. In all cases, the potential window for the cyclic voltammetry (CV) was from 0 V to –1.4 V vs. SCE. Characterization

scan rates were 100 mV/s for the characterization ex-periments, and approximately 70 mV/s for the desorp-tion of SAMs from actual patterned substrates.

To find the optimal alkanethiol forming stable SAMs with reasonable desorption times, reductive desorption of different alkanethiolate SAMs, C 3H 8S, C 8H 18S, C 12H 26S and C 18H 38S (Aldrich), was characterized. Cy-clic voltammograms (CVs) obtained from Au (111) textured thin films on mica [9] were used for characteri-zation. The negative current peaks on the CVs in the potential range from –1.1 to –1.4 V (Figure 4a-c) indi-cate the reductive desorption of alkanethiolate SAMs from the surfaces. The peaks become smaller with de-creasing coverage of SAMs on the gold surface. De-sorption is complete when the peak is no longer visible in the CV. The reduced alkanethiol dissolves into the electrolyte. Re-adsorption is unlikely to affect the sur-face hydrophobicity because the reduced alkanethiol is satisfied electronically (i.e., it no longer forms chemical bonds with the gold), and because of its low solution concentration.

The SAM of propanethiol (C 3H 8S) does not form stable hydrophobic surfaces in these electrolytes. Therefore, propanethiol was ruled out as a choice for the assembly experiment. By comparing desorption time and stability of the different alkanethiolate SAMs, dodecanethiol

(d)

(a)

(C 12H 26S) was chosen for the assembly experiments. The dodecanethiol forms stable hydrophobic SAMs on gold, and desorption of the SAMs takes approximately twenty minutes compared to six hours for octadec-anethiol (C 18H 38S). Desorption of dodecanethiolate (C 12H 26S) SAM on specific polycrystalline gold patterns of the Si substrate is shown in Figure 4d. The CV for desorption of SAMs from polycrystalline gold on a Si substrate has broader peaks, compared to CVs for de-

sorption of SAMs from single crystalline gold on mica.

Figure 4. CVs from desorption of n-alkanethiolate SAMs on Au. Solid and dashed curves in each figure are first and second CVs for desorption. Dotted curves are CVs from desorption after ten minutes in (a), fifteen minutes in (b), one hour and a half in (c) and twenty minutes in (d).

Assembly Experiments

After desorption of SAMs from specific sites, the sub-strate was removed from the electrochemical bath, rinsed with DI water and dried with N 2. A hydrocarbon lubricant was spread on the whole substrate. The lubri-cant is heat-curable, and composed of 97wt.% triethyle-neglycol dimethacrylate (Sigma) as crosslinker, and 3wt.% benzoyl peroxide (Sigma) as thermal initiator. Then the substrate was immersed in water in a petri-dish. The lubricant wetted only the SAM-coated hydro-phobic binding sites. The differences between the gold regions with and without SAM desorption are readily seen in Figure 5a. Then the parts were cleaned and added into the water in the container. The petri-dish was placed on an orbital shaker. With agitation, the assem-bly took place exclusively on the hydrophobic areas with lubricant. The lubricant, polymerized at 80o C for approximately half an hour, permanently bonded the parts to their sites (Figure 5b). The gold squares with SAM desorption on the substrate remained clean (Fig-ure 5a). A second assembly step has been achieved by repeating the SAM formation and the assembly process on these clean binding sites (Figure 6).

Figure 5. (a) A substrate with lubricant in water after selective SAM desorption. The SAM desorption has happened on the gold squares on the left column. Lubri-cant wets the gold squares without SAM desorption. (b) Thin 1mm 2 parts (fabricated by M. Cohn) were assem-bled and bonded only to gold patterns with adsorbed SAM on the right.

By repeating SAM adsorption, selective desorption, and assembly, controlled micro-assembly is feasible in prin-ciple for a large number of batches. In the next section, the issue of establishing electrical connection between the assembled parts and substrate is discussed.

Figure 6. Side view of two-batch controlled micro-assembly. Foreground: Second batch of 1mm 2 parts assembled (approximate 0.5mm thick; unpolished back-side is visible). Background: First batch 1mm 2 thin parts assembled.

CURRENT AND FUTURE WORK

Currently, we are investigating electroplating methods to establish electrical connections between assembled electrically active parts such as surface mount LEDs (Lumex) and the substrate. Figures 7a-c show a binding site design for a given LED, and electrically isolated seed sites for electroplating. To verify the feasibility of the electroplating process, we measure the gap between the assembled LED (Figure 7d) and the substrate to be approximately 20μm. An electroplated alloy on gold

seeds is seen in Figure 7d.

(a)

(b)

Our future work includes: optimization of the electroplating process, improving the binding site de-signs [10], improvement of the assembly setup for better yield, and generalization of the assembly process for various micro-parts and substrates.

Figure 7. (a) Binding site on the substrate with electro-plating seed. (b) Plating seed with SAM desorption, without lubricant, compared to binding site wetted with lubricant. (c) Assembled LED on the binding site. (d) ESEM image of assembled LED (e) Alloy electro-plated on exposed gold.

CONCLUSIONS

We have proposed a technique for repeated multi-batch parallel micro assembly via electrochemical modulation of surface hydrophobicity. Two-batch micro assembly has been successfully demonstrated. Presented were the principle, fabrication and assembly processes of this approach. Optimization of the desorption process was also accomplished, based on alkanethiolate SAM de-sorption characterization. With improvement of the as-sembly process and optimization of electroplating, it is anticipated that this technique can be applicable to a wide range of micro or nano components and materials, for the integration and packaging of complex systems.

ACKNOWLEDGEMENTS

We would like to thank Roger T. Howe and Uthara Srinivasan for inspiring discussions, and Shaoyi Jiang and Shengfu Chen for their help with the mica sample preparation.

This research is supported in part by NSF Career Award ECS9875367 to K. B?hringer and by donations from Agilent Technologies, Intel Corporation, Microsoft Re-search and Tanner Research Inc. D. Schwartz acknowl-edges partial support by an NSF Presidential Young Investigator Award CTS-9457097. Y. Hanein acknowl-edges partial support by an NSF CISE Postdoctoral Re-search Associateship EIA-0072744.

REFERENCES

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(e)

Seeds

常用贴片元件封装尺寸图

常用贴片元件封装尺寸图 目录 1 TO-268AA 41 D-7343 2 TO-26 3 D2PAK 42 C-6032 3 TO-263-7 43 B-3528 4 TO-263- 5 44 A-3216 5 TO-263-3 45 SOT883 6 TO-252 DPAK 46 SOT753 7 TO-252-5 47 SOT666 8 TO252-3 48 SOT663 9 2010 49 SOT552-1 10 4020 50 1SOT523 11 0603 51 SOT505-1 12 0805 52 SOT490-SC89 13 01005 53 SOT457 SC74 14 1008 54 SOT428 15 1206 55 SOT416/SC75 16 1210 56 SOT663 SMD 17 1406 57 SOT363 SC706L 18 1812 58 SOT353/sc70 5L 19 1808 59 SOT346/SC59 20 1825 60 SOT343 SMD 21 2010 61 SOT323/SC70-3 SMD 22 2225 62 SOT233 SMD 23 2308 63 SOT-223/TO-261AA SMD 24 2512 64 SOT89/TO243AA SC62 SMD 25 DO-215AB 65 SOT23-8 26 DO-215AA 66 SOT23-6 27 DO-214AC 67 SOT23-5 28 DO-214AB 68 SOT23 29 DO-214AA 69 SOT143/TO253 SMD 30 DO-214 31 DO-213AB 32 DO-213AA 33 SOD123H 34 SOD723 35 SOD523 36 SOD323 37 SOD-123F 38 SOD123 39 SOD110 40 DO-214AC SOD106

芯片常用封装及尺寸说明

A、常用芯片封装介绍 来源:互联网作者: 关键字:芯片封装 1、BGA 封装(ball grid array) 球形触点陈列,表面贴装型封装之一。在印刷基板的背面按陈列方式制作出球形凸点用以代替引脚,在印刷基板的正面装配 LSI 芯片,然后用模压树脂或灌封方法进行密封。也称为凸点陈列载体(PAC)。引脚可超过200,是多引脚 LSI 用的一种封装。封装本体也可做得比 QFP(四侧引脚扁平封装)小。例如,引脚中心距为 1.5mm 的360 引脚 BGA 仅为31mm 见方;而引脚中心距为0.5mm 的304 引脚 QFP 为 40mm 见方。而且 BGA 不用担心 QFP 那样的引脚变形问题。该封装是美国 Motorola 公司开发的,首先在便携式电话等设备中被采用,今后在美国有可能在个人计算机中普及。最初,BGA 的引脚(凸点)中心距为 1.5mm,引脚数为225。现在也有一些 LSI 厂家正在开发500 引脚的 BGA。 BGA 的问题是回流焊后的外观检查。 现在尚不清楚是否有效的外观检查方法。有的认为,由于焊接的中心距较大,连接可以看作是稳定的,只能通过功能检查来处理。美国 Motorola 公司把用模压树脂密封的封装称为 OMPAC,而把灌封方法密封的封装称为 GPAC(见 OMPAC 和 GPAC)。 2、BQFP 封装(quad flat package with bumper) 带缓冲垫的四侧引脚扁平封装。QFP 封装之一,在封装本体的四个角设置突起(缓冲垫) 以防止在运送过程中引脚发生弯曲变形。美国半导体厂家主要在微处理器和 ASIC 等电路中采用此封装。引脚中心距0.635mm,引脚数从84 到196 左右(见 QFP)。

常用元器件封装尺寸大小

封装形式图片国际统一简称 LDCC LGA LQFP PDIP TO5 TO52 TO71 TO71 TO78 PGA Plastic PIN Grid Array 封装形式图片国际统一简称 TSOP Thin Small OUtline Package QFP Quad Flat Package PQFP 100L QFP Quad Flat Package SOT143 SOT220 Thin Shrink Qutline Package uBGA Micro Ball Grid Array uBGA Micro Ball Grid Array PCDIP

PLCC LQFP LQFP 100L TO8 TO92 TO93 T099 EBGA 680L QFP Quad Flat Package TQFP 100L ZIP Zig-Zag Inline Packa SOT223 SOT223 SOT23 SOT23/SOT323 SOT25/SOT353 SOT26/SOT363 FBGA FDIP SOJ

SBGA LBGA 160L PBGA 217L Plastic Ball Grid Array SBGA 192L TSBGA 680L CLCC SC-705L SDIP SIP Single Inline Package SO Small Outline Package SOP EIAJ TYPE II 14L SSOP 16L SSOP SOJ 32L Flat Pack HSOP28 ITO220 ITO3P TO220 TO247

PCB中常见的元器件封装大全参考word

PCB中常见的元器件封装大全 一、常用元器件: 1.元件封装电阻 AXIAL 2.无极性电容 RAD 3.电解电容 RB- 4.电位器 VR 5.二极管 DIODE 6.三极管 TO 7.电源稳压块78和79系列 TO-126H和TO-126V 8.场效应管和三极管一样 9.整流桥 D-44 D-37 D-46 10.单排多针插座 CON SIP 11.双列直插元件 DIP 12.晶振 XTAL1 电阻:RES1,RES2,RES3,RES4;封装属性为axial系列 无极性电容:cap;封装属性为RAD-0.1到rad-0.4 电解电容:electroi;封装属性为rb.2/.4到rb.5/1.0 电位器:pot1,pot2;封装属性为vr-1到vr-5 二极管:封装属性为diode-0.4(小功率)diode-0.7(大功率) 三极管:常见的封装属性为to-18(普通三极管)to-22(大功率三极管)to-3(大功率达林 顿管) 电源稳压块有78和79系列;78系列如7805,7812,7820等;79系列有7905,7912,7920等.常见的封装属性有to126h和to126v 整流桥:BRIDGE1,BRIDGE2: 封装属性为D系列(D-44,D-37,D-46) 电阻:AXIAL0.3-AXIAL0.7 其中0.4-0.7指电阻的长度,一般用AXIAL0.4 瓷片电容:RAD0.1-RAD0.3。其中0.1-0.3指电容大小,一般用RAD0.1 电解电容:RB.1/.2-RB.4/.8 其中.1/.2-.4/.8指电容大小。一般<100uF用RB.1/.2,100uF-470uF用RB.2/.4,>470uF用RB.3/.6 二极管:DIODE0.4-DIODE0.7 其中0.4-0.7指二极管长短,一般用DIODE0.4 发光二极管:RB.1/.2 集成块:DIP8-DIP40, 其中8-40指有多少脚,8脚的就是DIP8

常用贴片元件封装尺寸图

目录 TO-268AA贴片元件封装形式图片 (3) TO-263 D2PAK封装尺寸图 (4) TO-263-7封装尺寸图 (5) TO-263-5封装尺寸图 (6) TO-263-3封装尺寸图 (7) TO-252 DPAK封装尺寸图 (8) TO-252-5封装尺寸图 (9) TO252-3封装尺寸图 (10) 0201封装尺寸 (11) 0402封装尺寸图片 (12) 0603封装尺寸图 (13) 0805封装尺寸图 (14) 01005封装尺寸图 (15) 1008封装尺寸图 (16) 1206封装尺寸图 (17) 1210封装尺寸图 (18) 1406封装尺寸图 (19) 1812封装尺寸图 (20) 1808封装尺寸图 (21) 1825封装尺寸图 (22) 2010封装尺寸图 (23) 2225封装尺寸图 (24) 2308封装尺寸图 (25) 2512封装尺寸图 (26) DO-215AB封装尺寸图 (27) DO-215AA封装尺寸图 (28) DO-214AC封装尺寸图 (29) DO-214AB封装尺寸图 (30) DO-214AA封装尺寸图 (31) DO-214封装尺寸图 (32) DO-213AB封装尺寸图 (33) DO-213AA封装尺寸图 (34) SOD123H封装图 (35) SOD723封装尺寸图 (36) SOD523封装尺寸图 (37) SOD323封装尺寸图 (38) SOD-123F封装尺寸图 (39) SOD123封装尺寸图 (40) SOD110封装尺寸图 (41) DO-214AC SOD106封装尺寸图 (42) D-7343封装尺寸图 (43)

常用芯片封装方式及说明(例图+文字版)

芯片封装方式大全 各种IC封装形式图片 BGA Ball Grid Array EBGA 680L LBGA 160L PBGA 217L Plastic Ball Grid Array SBGA 192L QFP Quad Flat Package TQFP 100L SBGA SC-70 5L SDIP SIP Single Inline Package SO Small Outline Package

TSBGA 680L CLCC CNR Communication and Networking Riser Specification Revision 1.2 CPGA Ceramic Pin Grid Array DIP Dual Inline Package SOJ 32L SOJ SOP EIAJ TYPE II 14L SOT220 SSOP 16L SSOP TO18

DIP-tab Dual Inline Package with Metal Heatsink FBGA FDIP FTO220 Flat Pack HSOP28 ITO220 TO220 TO247 TO264 TO3 TO5 TO52 TO71

ITO3p JL LCC LDCC LGA LQFP PCDIP PGA Plastic Pin Grid Array TO72 TO78 TO8 TO92 TO93 TO99 TSOP Thin Small Outline Package

PLCC 详细规格 P PS LQFP 100L 详细规格 METAL QUAD 100L 详细规格 PQFP 100L 详细规格 QFP Quad Flat Package TSSOP or TSOP II Thin Shrink Outline Package uBGA Micro Ball Grid Array uBGA Micro Ball Grid Array ZIP Zig-Zag Inline Package TEPBGA 288L TEPBGA C-Bend Lead

最新SMT常见贴片元器件封装类型和尺寸资料

1、SMT表面封装元器件图示索引(完善)

2、SMT物料基础知识 一. 常用电阻、电容换算: 1.电阻(R): 电阻:定义:导体对电流的阻碍作用就叫导体的电阻。 无方向,用字母R表示,单位是欧姆(Ω),分:欧(Ω)、千欧(KΩ)、兆欧(MΩ)1MΩ=1000KΩ=1000000Ω 1).换算方法: ①.前面两位为有效数字(照写),第三位表示倍数10n次方(即“0”的个数) 103=10*103=10000Ω=10KΩ 471=47*101=470Ω 100=10*100=10Ω 101=10×101=100Ω 120=12×100=12Ω ②.前面三位为有效数字(照写),第四位表示倍数倍数10n次方(即“0”的个数). 1001=100*101=1000Ω=1KΩ 1632=163*102=16300Ω=16.3KΩ 1470=147×100=147Ω 1203=120×103Ω=120KΩ 4702=470×102Ω=47KΩ

2.电容(C): 电容的特性是可以隔直流电压,而通过交流电压。它分为极性和非极性,用C表示。 2.1三种类型:电解电容钽质电容有极性, 贴片电容无极性。 用字母C表示,单位是法(F),毫法(MF),微法(UF),纳法(NF)皮法(PF) 1F=103MF=106UF=109NF=1012PF 2.2换算方法: 前面两位为有效数字(照写),第三位倍数10n次方(即“0”的个数) 104=10*104=100000PF=0.1UF 100=10*100=10PF 473=47×103=47000pF=47nF=0.047uF 103=10×103=10000pF=10nF=0.01uF 104=10×104=100000pF=10nF=0.1uF 221=22×101=220pF 330=33×100=33pF 2.3钽电容: 它用金属钽或者铌做正极,用稀流酸等配液做负极,用钽或铌表面生成的氧化膜做成介质制成,其特点是体积小、容量大、性能稳定、寿命长、绝缘电阻大、温度特性好,用在要求较高的设备中。钽电容表面有字迹表明其方向、容值,通常有一条横线的那边标志钽电容的正极。钽电容规格通常有:A型、B型、C型、P型。 2.4 电容的误差表示 2.4.1常用钽电容代换参照表. 1UF:105、A6、CA6 2.2UF:225 3.3UF:335、AN6、CN6、JN6、CN69 4.7UF:475、JS6 10UF:106、JA7、AA7、GA7 22UF:226、GJ7、AJ7、JJ7 47UF:476 3. 电感(L)

(整理)常用PCB封装图解

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2020年芯片封装大全(图文对照)

芯片封装大全(图文对照)

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SMT贴片元器件封装类型的识别 封装类型是元件的外观尺寸和形状的集合,它是元件的重要属性之一。相同电子参数的元件可能有不同的封装类型。厂家按照相应封装标准生产元件以保证元件的装配使用和特殊用途。 由于封装技术日新月异且封装代码暂无唯一标准,本指导只给出通用的电子元件封装类型和图示,与SMT工序无关的封装暂不涉及。 1、常见SMT封装 以公司内部产品所用元件为例,如下表: 通常封装材料为塑料,陶瓷。元件的散热部分可能由金属组成。元件的引脚分为有铅和无铅区别。

2、SMT封装图示索引 以公司内部产品所用元件为例,如下图示: 名称图示常用于备注Chip 电阻,电容,电感 MLD 钽电容,二极管 CAE 铝电解电容 Melf 圆柱形玻璃二极管, 电阻(少见) SOT 三极管,效应管JEDEC(TO) EIAJ(SC) TO 电源模块JEDEC(TO) OSC 晶振 Xtal 晶振 SOD 二极管JEDEC SOIC 芯片,座子 SOP 芯片前缀: S:Shrink T:Thin SOJ 芯片 PLCC 芯片含LCC座子(SOCKET) DIP 变压器,开关QFP 芯片 BGA 芯片塑料:P 陶瓷:C QFN 芯片

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常见元件的封装形式.

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常用电子元件封装、尺寸、规格汇总

常用电子元件封装、尺寸、规格汇总 贴片电阻规格 贴片电阻常见封装有9种,用两种尺寸代码来表示。一种尺寸代码是由4位数字表示的EIA(美国电子工业协会)代码,前两位与后两位分别表示电阻的长与宽,以英寸为单位。我们常说的0603封装就是指英制代码。另一种是米制代码,也由4位数字表示,其单位为毫米。下表列出贴片电阻封装英制和公制的关系及详细的尺寸: 贴片元件的封装 一、零件规格: (a)、零件规格即零件的外形尺寸,SMT发展至今,业界为方便作业,已经形成了一个标准零件系列,各家零件供货商皆是按这一标准制造。标准零件之尺寸规格有英制与公制两种表示方法,如下表英制表示法1206 0805 0603 0402 公制表示法3216 2125 1608 1005含义L:1.2inch(3.2mm)W:0.6inch(1.6mm) L:0.8inch(2.0mm)W:0.5inch(1.25mm)

L:0.6inch(1.6mm)W:0.3inch(0.8mm) L:0.4inch(1.0mm)W:0.2inch(0.5mm) 注: a、L(Length):长度;W(Width):宽度;inch:英寸 b、1inch=25.4mm(b)、在(1)中未提及零件的厚度,在这一点上因零件不同而有所差异,在生产时应以实际量测为准。(c)、以上所讲的主要是针对电子产品中用量最大的电阻(排阻)和电容(排容),其它如电感、二极管、晶体管等等因用量较小,且形状也多种多样,在此不作讨论。(d)、SMT发展至今,随着电子产品集成度的不断提高,标准零件逐步向微型化发展,如今最小的标准零件已经到了0201。二、常用元件封装1)电阻:最为常见的有0805、0603两类,不同的是,它可以以排阻的身份出现,四位、八位都有,具体封装样式可参照MD16仿真版,也可以到设计所内部PCB库查询。注: ABCD四类型的封装形式则为其具体尺寸,标注形式为L X S X H 1210具体尺寸与电解电容B类3528类型相同 0805具体尺寸:2.0 X 1.25 X 0.5(公制表示法) 1206具体尺寸:3.0 X 1.5 0X 0.5(公制表示法)2)电阻的命名方法1、5%精度的命名:RS – 05 K 102 JT 2、1%精度的命名:RS – 05 K 1002 FT R -表示电阻 S -表示功率 0402是1/16W、 0603是1/10W、 0805是1/8W、 1206是1/4W、 1210是1/3W、 1812是1/2W、 2010是3/4W、 2512是1W。 05 -表示尺寸(英寸): 02表示0402、 03表示0603、05表示0805、 06表示1206、 1210表示1210、 1812表示1812、 10表示1210、 12表示2512。 K -表示温度系数为100PPM。 102 -5%精度阻值表示法:前两位表示有效数字,第三位表示有多少个零,基本单位是Ω,102=1000Ω=1KΩ。 1002 是1%阻值表示法:前三位表示有效数字,第四位表示有多少个零,基本单位是Ω,1002=10000Ω=10KΩ。 J -表示精度为5%、 F-表示精度为1%。 T -表示编带包装 3)电容:可分为无极性和有极性两类:

贴片元器件封装尺寸

【SMD贴片元件的封装尺寸】 公制:3216——2012——1608——1005——0603——0402 英制:1206——0805——0603——0402——0201——01005 注意: 0603有公制,英制的区分 公制0603的英制是英制0201, 英制0603的公制是公制1608 还要注意1005与01005的区分, 1005也有公制,英制的区分 英制1005的公制是公制2512 公制1005的英制是英制0402 像在ProtelDXP(Protel2004)及以后版本中已经有SMD贴片元件的封装库了,如 CC1005-0402:用于贴片电容,公制为1005,英制为0402的封装 CC1310-0504:用于贴片电容,公制为1310,英制为0504的封装 CC1608-0603:用于贴片电容,公制为1608,英制为0603的封装 CR1608-0603:用于贴片电阻,公制为1608,英制为0603的封装,与CC16-8-0603尺寸是一样的,只是方便识别。 【贴片电阻规格、封装、尺寸】 英制(inch) 公制 (mm) 长(L) (mm) 宽(W) (mm) 高(t) (mm) a (mm) b (mm) 0201 0603 0.60±0.05 0.30±0.05 0.23±0.05 0.10±0.05 0.15±0.05 0402 1005 1.00±0.10 0.50±0.10 0.30±0.10 0.20±0.10 0.25±0.10 0603 1608 1.60±0.15 0.80±0.15 0.40±0.10 0.30±0.20 0.30±0.20 0805 2012 2.00±0.20 1.25±0.15 0.50±0.10 0.40±0.20 0.40±0.20 1206 3216 3.20±0.20 1.60±0.15 0.55±0.10 0.50±0.20 0.50±0.20 1210 3225 3.20±0.20 2.50±0.20 0.55±0.10 0.50±0.20 0.50±0.20 1812 4832 4.50±0.20 3.20±0.20 0.55±0.10 0.50±0.20 0.50±0.20 2010 5025 5.00±0.20 2.50±0.20 0.55±0.10 0.60±0.20 0.60±0.20 2512 6432 6.40±0.20 3.20±0.20 0.55±0.10 0.60±0.20 0.60±0.20 国内贴片电阻的命名方法:

芯片封装知识

1.DIP双列直插式封装 DIP(DualIn-line Package)是指采用双列直插形式封装的集成电路芯片,绝大多数中小规模集成电路(IC)均采用这种封装形式,其引脚数一般不超过100个。采用DIP封装的CPU芯片有两排引脚,需要插入到具有DIP结构的芯片插座上。当然,也可以直接插在有相同焊孔数和几何排列的电路板上进行焊接。DIP封装的芯片在从芯片插座上插拔时应特别小心,以免损坏引脚。 DIP封装具有以下特点 ⒈合在PCB(印刷电路板)上穿孔焊接,操作方便。 ⒉封装面积与芯片面积之间的比值较大,故体积也较大。 Intel系列CPU中8088就采用这种封装形式,缓存(Cache)和早期的内存芯片也是这种封装形式。 2.PQFP/PFP组件式封装 PQFP(Plastic Quad Flat Package)封装的芯片引脚之间距离很小,管脚很细,一般大规模或超大型集成电路都采用这种封装形式,其引脚数一般在100个以上。用这种形式封装的芯片必须采用SMD(表面安装设备技术)将芯片与主板焊接起来。采用SMD安装的芯片不必在主板上打孔,一般在主板表面上有设计好的相应管脚的焊点。将芯片各脚对准相应的焊点,即可实现与主板的焊接。用这种方法焊上去的芯片,如果不用专用工具是很难拆卸下来的。 PFP(Plastic Flat Package)方式封装的芯片与PQFP方式基本相同。唯一的区别是PQFP一般为正方形,而PFP既可以是正方形,也可以是长方形。 PQFP/PFP封装特点 ⒈适用于SMD表面安装技术在PCB电路板上安装布线。 ⒉适合高频使用。 ⒊操作方便,可靠性高。 ⒋芯片面积与封装面积之间的比值较小。 Intel系列CPU中80286、80386和某些486主板采用这种封装形式。3.PGA插针网格阵列封装 PGA(Pin Grid Array Package)芯片封装形式在芯片的内外有多个方阵形的插针,每个方阵形插针沿芯片的四周间隔一定距离排列。根据引脚数目的多少,可以围成2-5圈。安装时,将芯片插入专门的PGA插座。为使CPU能够更方便地安装和拆卸,从486芯片开始,出现一种名为ZIF的CPU插座,专门用来满足PGA 封装的CPU在安装和拆卸上的要求。 ZIF(Zero Insertion Force Socket)是指零插拔力的插座。把这种插座上的扳手轻轻抬起,CPU就可很容易、轻松地插入插座中。然后将扳手压回原处,利用插座本身的特殊结构生成的挤压力,将CPU的引脚与插座牢牢地接触,绝对不存在接触不良的问题。而拆卸CPU芯片只需将插座的扳手轻轻抬起,则压力解除,CPU 芯片即可轻松取出。 PGA封装具有以下特点 ⒈插拔操作更方便,可靠性高。 ⒉可适应更高的频率。 Intel系列CPU中,80486和Pentium、Pentium Pro均采用这种封装形式。

常用贴片元件封装

常用贴片元件封装 1 电阻: 最为常见的有0201、0402、0805、0603、1206、1210、1812、2010、2512几类1)贴片电阻的封装与尺寸如下表: 英制(mil) 公制(mm) 长(L)(mm) 宽(W)(mm) 高(t)(mm) 0201 0603 ±±± 0402 1005 ±±± 0603 1608 ±±± 0805 2012 ±±± 1206 3216 ±±± 1210 3225 ±±± 1812 4832 ±±± 2010 5025 ±±± 2512 6432 ±±± 2)贴片电阻的封装、功率与电压关系如下表: 英制(mil)公制(mm)额定功率@ 70°C 最大工作电压(V) 0201 0603 1/20W 25 0402 1005 1/16W 50 0603 1608 1/10W 50 0805 2012 1/8W 150 1206 3216 1/4W 200 1210 3225 1/3W 200 1812 4832 1/2W 200 2010 5025 3/4W 200 2512 6432 1W 200 3)贴片电阻的精度与阻值 贴片电阻阻值误差精度有±1%、±2%、±5%、±10%精度, J -表示精度为5%、 F-表示精度为1%。 T -表示编带包装 阻值范围从0R-100M 4)贴片电阻的特性 ·体积小,重量轻; ·适应再流焊与波峰焊; ·电性能稳定,可靠性高; ·装配成本低,并与自动装贴设备匹配; ·机械强度高、高频特性优越。 2电容: 1)贴片电容可分为无极性和有极性两种,容值范围从 无极性电容下述两类封装最为常见,即0805、0603; 英制尺寸公制尺寸长度宽度厚度 0402 1005 ± ± ± 0603 1608 ± ±±

SMT常见贴片元器件封装类型和尺寸.docx

1、 SMT表面封装元器件图示索引(完善) 名称图示常用于备注 电阻,电容, Chip片式元件 电感 MLD:钽电容,二极 模制本体元件Molded Body管 CAE: Aluminum 铝电解电容有极性Electrolytic Capacitor Melf :圆柱形玻璃二 Metal Electrode极管 ,二个金属电极Face电阻(少见) SOT:小型晶体管 三极管,效应 Small Outline JEDEC(TO) 管 Transistor EIAJ(SC) TO:晶体管外形的贴Transistor电源模块片元件Outline JEDEC(TO) OSC: 晶振晶体振荡器Oscillator Xtal :Crystal晶振二引脚晶振SOD:二极管小型二极管(相

Small Outline Diode SOIC:Small Outline IC SOP:Small Outline Package SOJ:Small Outline J-Lead LCC:Leadless Chip carrier 比插件元件) JEDEC 芯片,座子小型集成芯片 小型封装,也称 SO,SOIC 引脚从封装 两侧引出呈芯片 海鸥翼状 (L 字形 ) 前缀: S: Shrink T: Thin J 型引脚的小芯芯片 片【也成丁字形】 无引脚芯片载 体: 指陶瓷基板的四 个侧面只有电极 芯片 接触而无引脚的 表面贴装型封 装。也称为陶瓷 QFN 或 QFN-C

PLCC:plastic leaded Chip carrier DIP: Dual In-line Package QFP: Quad Flat Package BGA: Ball Grid Array QFN: Quad Flat No-lead 引脚从封装的四 芯片 个侧面引出,呈 丁字形或 J型, 是塑料制品。 双列直插式封变压器,开关 , 装:引脚从封装 芯片 两侧引出 四方扁平封装: 引脚从四个侧面 引出呈海鸥翼芯片 (L) 型。基材有陶 瓷、金属和塑料 三种。 球形栅格阵 列:在印刷基芯片板的背面按陈塑料: P列方式制作出陶瓷: C球形凸点用以 代替引脚 四方扁平无引芯片 脚器件

常用贴片元件封装.

常用贴片元件封装 1 电阻: 最为常见的有 0201 、040 2 、 0805 、060 3 、1206 、 1210 、1812 、2010 、2512 几类 1)贴片电阻的封装与尺寸如下表: 英制(mil)公制(mm)长(L)(mm)宽(W)(mm) 高(t)(mm) 英制(mil)公制(mm)额定功率@ 70 C 最大工作电压(V) 0201 0603 1/20W 25 0402 1005 1/16W 50 0603 1608 1/10W 50 0805 2012 1/8W 150 **** **** 1/4W 200 1210 3225 1/3W 200 1812 4832 1/2W 200 0201 0603 0.60 ±0.05 0.30 ±0.05 0.23 ±0.05 0402 1005 1.00 ±0.10 0.50 ±0.10 0.30 ±0.10 0603 1608 1.60 ±0.15 0.80 ±0.15 0.40 ±0.10 0805 2012 2.00 ±0.20 1.25 ±0.15 0.50 ±0.10 1206 3216 3.20 ±0.20 1.60 ±0.15 0.55 ±0.10 1210 3225 3.20 ±0.20 2.50 ±0.20 0.55 ±0.10 1812 4832 4.50 ±0.20 3.20 ±0.20 0.55 ±0.10 2010 5025 5.00 ±0.20 2.50 ±0.20 0.55 ±0.10 2512 6432 6.40 ±0.20 3.20 ±0.20 0.55 ±0.10 功率与电压关系如下表: 2)贴片电阻的封装、

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