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MT8732_MT6325_MT6169_EMMC_LPDDR3_3M8B_TDD_CSFB_DSDS_REF_SCH_V04

10_BB_ POWER

MTK Confidential

Friday, July 18, 2014

Sheet

11_BB_1

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12_BB_2

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13_BB_3

D_GND

MICBIAS1MICBIAS0

D_GND VIO18_PMU

D_GND

VBAT

D_GND

Sheet

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20_POWER_MT6325

Friday, July 18, 2014

single via to GND plane directly

The Layout constraint requires sufficient bypass cap. LDO will not have stability problems

J18J17N16N17K16

H16

M16L15L16T19H18H13C2027

1

C2042

C / 1 / uF / 0201C0201

21

C2044C / 1 / uF / 0201C02012

1

C2036

C / 1 / uF / 0201C0201

2

1

C2022

C / 1 / uF / 0201C0201

21

C2038

C / 2.2 / uF / 0402C0402

21

D_GND

Sheet

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21_POWER_TBD

Friday, July 18, 2014

R / 0.01 / ohm / 1206 / 1%

31_RF_MT6169_PIN_OUT

Friday, July 18, 2014

54Sheet

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32_RF_MT6169_RF_TX

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Friday, July 18, 2014

Sheet

33_RF_MT6169_RF_PRX

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Friday, July 18, 2014

Sheet

34_RF_MT6169_RF_DRX

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Friday, July 18, 2014

Sheet

41_Memory_eMMC_LPDDR3 MTK Confidential

Friday, July 18, 2014

Sheet

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