MOSEL VITELIC V53C317405A
4M X 4 EDO PAGE MODE
CMOS DYNAMIC RAM
V53C317405A5060 Max. RAS Access Time, (t RAC)50 ns60 ns Max. Column Address Access Time, (t CAA)25 ns30 ns Min. Extended Data Out Page Mode Cycle Time, (t PC)20 ns25 ns Min. Read/Write Cycle Time, (t RC)84 ns104 ns
Features
s4M x 4-bit organization
s EDO Page Mode for a sustained data rate of 50 MHz
s RAS access time: 50, 60, 70 ns
s Low power dissipation
s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, Hidden Refresh s Refresh Interval: 2048 cycles/32 ms
s Available in 24/26-pin 300 mil SOJ, and 24/26-pin 300 mil TSOP-II
s Single +3.3 V ±10% Power Supply
s TTL Interface Description
The V53C317405A is a 4,194,304 x 4 bit high-performance CMOS dynamic random access memory. The V53C317405A offers Page mode operation with Extended Data Output. The V53C317405A has a symmetric address, 11-bit row and 11-bit column.
All inputs are TTL compatible. EDO Page Mode operation allows random access up to 2048 x 4 bits, within a page, with cycle times as short as 20ns. These features make the V53C317405A ideally suited for a wide variety of high performance computer systems and peripheral applications.
Device Usage Chart
Operating Temperature Range Package Outline Access Time (ns)Power
Temperature
Mark
K T5060Std.
0°C to 70°C?????Blank
MOSEL VITELIC V53C317405A
Pin Names
A0–A10Row, Column Address Inputs
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
OE Output Enable
I/O1–I/O4Data Input, Output
V CC+3.3V Supply
V SS0V Supply
NC No Connect
Description Pkg.Pin Count
SOJ K24/26
TSOP-II T24/26
24/26 Pin Plastic SOJ /TSOP-II
PIN CONFIGURATION
Top View
MOSEL VITELIC V53C317405A
Absolute Maximum Ratings*
Operating temperature range..................0 to 70 °C Storage temperature range...............-55 to 150 °C Input/output voltage....-0.5 to min (V CC+0.5, 4.6) V Power supply voltage.........................-1.0V to 4.6V Power dissipation..........................................0.5 W Data out current (short circuit)......................50 mA *Note:Operation above Absolute Maximum Ratings can adversely affect device reliability.Capacitance*
T A = 25°C, V CC = 3.3 V ± 10%, V SS = 0 V, f = 1 MHz *Note: Capacitance is sampled and not 100% tested.
Symbol Parameter Min.Max.Unit
C IN1Address Input—5pF
C IN2RAS, CAS, WE, OE—7pF
C OUT Data Input/Output—7pF
Block Diagram
MOSEL VITELIC V53C317405A DC and Operating Characteristics (1-2)
T A = 0°C to 70°C, V CC = 3.3 V ± 10%, V SS = 0 V, t T = 2ns, unless otherwise specified.
Symbol Parameter Access
Time
V53C317405A
Unit Test Conditions Notes Min.Typ.Max.
I LI Input Leakage Current
(any input pin)
–1010m A V SS￡ V IN￡ V CC + 0.5V1
I LO Output Leakage Current
(for High-Z State)–1010m A V SS ￡ V OUT￡ V CC + 0.5V
RAS, CAS at V IH
other input 3 V SS
1
I CC1V CC Supply Current,
Operating 50120mA t RC = t RC (min.)2, 3, 4 60110
I CC2V CC Supply Current,
TTL Standby 2mA RAS, CAS at V IH
other inputs 3 V SS
I CC3V CC Supply Current,
RAS-Only Refresh 50120mA t RC = t RC (min.)2, 4 60110
I CC4V CC Supply Current,
EDO Page Mode
Operation 5070mA Minimum Cycle2, 3, 4 6055
I CC5V CC Supply Current,
during CAS-before-RAS
Refresh 50120mA2, 4 60110
I CC6V CC Supply Current,
CMOS Standby 1.0mA RAS 3 V CC – 0.2 V,
CAS 3 V CC – 0.2 V
other input 3 V SS
1
V CC Power Supply Voltage 3.0 3.3 3.6V
V IL Input Low Voltage –0.50.8V1 V IH Input High Voltage 2.0V CC+0.5V1 V OL Output Low Voltage0.4V I OL = 2 mA1 V OH Output High Voltage 2.4—V I OH = –2 mA1
MOSEL VITELIC V53C317405A
AC Characteristics(5, 6)
T A = 0 to 70 ?C,V CC = 3.3 V ± 10 %, t T = 2 ns
#Symbol Parameter
-50-60
Unit Note min.max.min.max.
Common Parameters
1t RC Random read or write cycle time84–104–ns
2t RP RAS precharge time30–40–ns
3t RAS RAS pulse width5010k6010k ns
4t CAS CAS pulse width810k1010k ns
5t ASR Row address setup time0–0–ns
6t RAH Row address hold time8–10–ns
7t ASC Column address setup time0–0–ns
8t CAH Column address hold time8–10–ns
9t RCD RAS to CAS delay time 12371445ns
10t RAD RAS to column address delay 10251230ns
11t RSH RAS hold time1315–ns
12t CSH CAS hold time4050–ns
13t CRP CAS to RAS precharge time5–5–ns
14t T Transition time (rise and fall) 150150ns7 15t REF Refresh period–32–32ms
Read Cycle
16t RAC Access time from RAS–50–60ns8,9 17t CAC Access time from CAS–13–15ns8,9 18t CAA Access time from column address–25–30ns8,10 19t OEA OE access time–13–15ns
20t RAL Column address to RAS lead time25–30–ns
21t RCS Read command setup time0–0–ns
22t RCH Read command hold time 0–0–ns11 23t RRH Read command hold time referenced to RAS 0–0–ns11 24t CLZ CAS to output in low-Z 0–0–ns8 25t OFF Output buffer turn-off delay 013015ns12 26t OEZ Output turn-off delay from OE013015ns12 27t DZC Data to CAS low delay 0–0–ns13 28t DZO Data to OE low delay0–0–ns13 29t CDD CAS high to data delay 10–13–ns14 30t ODD OE high to data delay 10–13 –ns14
Write Cycle
31t WCH Write command hold time 8–10–ns 32t WP Write command pulse width 8–10–ns 33t WCS Write command setup time 0–0–ns 15
34t RWL Write command to RAS lead time 8–10–ns 35t CWL Write command to CAS lead time 8–10–ns 36t DS Data setup time 0–0–ns 1637
t DH
Data hold time
8
–
10
–
ns
16Read-modify-Write Cycle
38t RWC Read-write cycle time 113–138–ns 39t RWD RAS to WE delay time 64–77–ns 1540t CWD CAS to WE delay time
27–32–ns 1541t AWD Column address to WE delay time 39–47–ns 15
42
t OEH
OE command hold time
10
–
13
–
ns
EDO Page Mode Cycle
43t PC EDO page mode cycle time 20–25–ns 44t CP CAS precharge time
8–10–ns 45t CPA Access time from CAS precharge –27–32ns 7
46t COH Output data hold time
5–5–ns 47t RASP RAS pulse width in EDO mode 50200k 60200k ns 48t RHPC CAS precharge to RAS Delay 27–32–
ns 49
t OES
OE setup time prior to CAS
5
–
5
ns
EDO Page Mode Read-modify-Write Cycle
50t PRWC EDO page mode read-write cycle time
58–68–ns 51
t CPWD
CAS precharge to WE
41
–
49
–
ns
CAS-before-RAS Refresh Cycle
52t CSR CAS setup time 10–10–ns 53t CHR CAS hold time
10–10–ns 54t RPC RAS to CAS precharge time 5–5–ns 55t WRP Write to RAS precharge time 10–10–ns 56
t WRH
Write hold time referenced to RAS
10
–
10
–
ns
AC Characteristics (5, 6)
T A = 0 to 70 ?C,V CC = 3.3 V ± 10 %, t T = 2 ns
#
Symbol
Parameter
-50
-60
Unit Note
min.
max.
min.
max.
CAS-before-RAS Counter Test Cycle
57
t CPT
CAS precharge time
35
–
40
–
ns
Test Mode
61t WTS Write command setup time 10–10–ns 62t WTH Write command hold time 10–10–ns 63t CHRT CAS hold time
30–30–ns 64
t RAHT
RAS hold time in test mode
30
–
30
–
ns
AC Characteristics (5, 6)
T A = 0 to 70 ?C,V CC = 3.3 V ± 10 %, t T = 2 ns
#
Symbol
Parameter
-50
-60
Unit Note
min.
max.
min.
max.
Notes:
1)All voltages are referenced to V SS.
2)I CC1, I CC3, I CC4 and I CC5 depend on cycle rate.
3)I CC1 and I CC4 depend on output loading. Specified values are obtained with the output open.
4)Address can be changed once or less while RAS = V IL. In case of I CC4 it can be changed once or less during a EDO
page mode cycle
5)An initial pause of 200 m s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be
a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum
of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6)AC measurements assume t T = 2 ns.
7)V IH (min.) and V IL (max.) are reference levels for measuring timing of input signals. Transition times are also measured
between V IH and V IL.
8)Measured with the specified current load and 100 pF at V OL = 0.8 V and V OH = 2.0 V. Access time is determined
by the latter of t RAC, t CAC, t CAA,t CPA, t OEA . t CAC is measured from tristate.
9)Operation within the t RCD (max.) limit ensures that t RAC (max.) can be met. t RCD (max.) is specified as a reference point
only. If t RCD is greater than the specified t RCD (max.) limit, then access time is controlled by t CAC.
10)Operation within the t RAD (max.) limit ensures that t RAC (max.) can be met. t RAD (max.) is specified as a reference point
only. If t RAD is greater than the specified t RAD (max.) limit, then access time is controlled by t CAA.
11)Either t RCH or t RRH must be satisfied for a read cycle.
12)t OFF (max.), t OEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced
to output voltage levels. t OFF is referenced from the rising edge of RAS or CAS, whichever occurs last.
13)Either t DZC or t DZO must be satisfied.
14)Either t CDD or t ODD must be satisfied.
15)t WCS, t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electri-
cal characteristics only. If t WCS > t WCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if t RWD > t RWD (min.), t CWD > t CWD (min.) and t AWD > t AWD (min.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in
read-write cycles.
Waveforms of Read Cycle
RAS
CAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
WL1
Waveforms of Write Cycle (Early Write)
CAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
WL2
Waveforms of Write Cycle (OE Controlled Write)
RAS
CAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
V IH
V IL
V V V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
Waveforms of Read-Write (Read-Modify-Write) Cycle
I/O
(Outputs)
I/O
(Inputs)
OE
WE
RAS
CAS
Address
V IH V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V OL
V
Waveforms of EDO Page Mode Read Cycle
RAS
I/O WE
Address
CAS
V IH
V IL
OE
(Output)
V IH
V IL
V IH
V IL
V IH
V IL
V OH
V OL
V IH V IL
Waveforms of EDO Page Mode Early Write Cycle
RAS
I/O (Input)
WE
Address
CAS
OE
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V V V IH
V IL
Waveforms of EDO Page Mode Late Write and Read-Modify-Write Cycle
R A S C A S
W E
O E
A d d r e s s
I /O (I n p u t s )
I /O (O u t p u t s )
WL17
V I V I V I V I V I V I V I V I V I V I V I V I V O V O
Waveforms of RAS Only Refresh Cycle
Address
RAS
CAS
I/O
(Outputs)
V IH V IL
V IH
V IL
V IH
V IL
V V OL
Waveforms of CAS-before-RAS Refresh Cycle
RAS
I/O
(Outputs)I/O
(Inputs)
OE
WE
CAS
WL10
V V IL
V V IL
V V IL
V V IL
V V IL
V V
Waveforms of Hidden Refresh Read Cycle
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
Address
CAS
V V V V V V V V V V V V V V
Waveforms of Hidden Refresh Early Write Cycle
RAS
I/O
(Output)
I/O (Input)
WE
Address
CAS
WL12
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
RAS
I/O
(Inputs)OE WE
Address
CAS
I/O
(Outputs)
I/O
(Outputs)
I/O
(Inputs)WE
OE
Read Cycle:Write Cycle:
V V V V V V V V V V V V V V V V V V V V V V