1/4” 5M Pixel CMOS Image Sensor with ISP
The JT8EV5-AS is a color sensor chip which includes area color image sensor embedded with image signal processor (ISP) . In the sensor area 2560 horizontal and 1944 vertical signal pixels, and the image size meets with 1/4 inch optical Format. Use of the CMOS process enables low power consumption operations. It also provides excellent color reproduction through its primary color filter, and embedded image signal processor enables small and simple camera system. So it is fit to use as an image input device for phone cameras.
Features
General
? Input Clock : 9-27MHz (with built-in PLL, Selectable)
? Frame rate : 5M 7.5 fps@YUV422, 20fps@JPEG ?
1080P 13fps @YUV422, 30fps@JPEG 720P 30fps@YUV422, 60fps @JPEG VGA 100fps@YUV422 and JPEG
? Data formats : YUV422/RGB565/RAW/Jpeg/Jpeg+Thumbnail ? Output formats : CSI-2 (1 lane) / 8bits parallel ? Power supply : Analog 2.6 to 3.0 V
Digital 1.7 to 1.9 V I/O 1.7 to 3.0 V
? Operating temperature : -20 to +60 ℃ ? Storage temperature : -30 to +85 ℃ Sensor
? Optical format : 1/4 inch ? Effective pixel numbers : 2624(H) x 1956(V) (5.13mega pixel) ? Pixel pitch : 1.4μm(H) x 1.4μm(V) (square pixel) ? Image area size : 3774.4μm (H) x2839.2μm (V) ? Color filter : Primary color filter, Bayer arrangement ? Window of interest (Windowing to any arbitrary size fixed center) ? Image sizer (programmable decimation for image down sizing) ? Digital zoom
? Picture flip (Horizontal flip and Vertical flip)
? Picture effects (monochrome, negative, sepia, antique, sketch, emboss) ? Auto luminance control (=Auto exposure) ? Auto white balance ? Bad pixel correction
? Auto flicker detection and correction
? Gamma correction (programmable gamma table) and dynamic gamma correction ? Lens shading correction
? Thumbnail output with JPEG data
? AF (Auto Focus ) function with internal actuator driver ? Analog input for actuator driver ? 8Kbit e-fuse OTP ? Standby mode
? Power down mode for low power consumption
TOSHIBA C 2OS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
JT8EV5-AS-200
V0.3 Mar 8, 2011
Key Specifications
Item
Contents Optical format
1/4 inch
Effective pixel numbers 2624(H) x 1956(V) (5.13mega pixel) Image area size 3774.4μm (H) x2839.2μm (V)
Pixel pitch 1.4μm(H) x 1.4μm(V) (square pixel) Aspect ratio
4(H) : 3(V)
Input clock frequency range 9 to 27 MHz (with PLL, selectable) Signal output order
Progressive scanning Color filter
RGB primary color filter
Bayer arrangement (G checked, R/B in line sequence)
Output data YUV422 /RAW , CSI-2 1lane/ 8bits Parallel output
Frame rate
5M 7.5 fps@YUV422, 20fps@JPEG 1080P 13fps @YUV422, 30fps@JPEG
720P 30fps@YUV422, 60fps@JPEG VGA 100fps@YUV422 and JPEG
Package Reconstructed wafer
Table 1 Key specifications
Table of Contents
Features (1)
General (1)
Sensor (1)
Key Specifications (2)
Table of Contents (3)
1.List of Abbreviation (5)
2.Block Diagram (6)
2.1.Block Diagram (6)
2.2.I/O circuit (7)
3.Pad Description (9)
4.Pixel Arrangement (10)
5.Chip Layout (11)
6.Pad Coordinates (13)
7.I2C Control Interface (14)
7.1.General (14)
7.2.Slave address (15)
8.Power supply (16)
8.1.Power Supply terminals (16)
https://www.doczj.com/doc/bb16609559.html,ing a built-in regulator (17)
9.Readout Modes (18)
10.Clock settings (19)
11.Frame rate (19)
12.Data Formats (20)
13.Functions (21)
13.1.Lens shading correction (21)
13.2.Bad Pixel Correction (21)
13.3.Noise Reduction (21)
13.4.Gamma correction (22)
13.5.Demosaicing (22)
13.6.Detail Enhancer (22)
13.7.YUV matrix (23)
13.8.Color matrix (23)
13.9.ALS (Auto Level Setting) (23)
13.10.Black level correction (23)
13.11.Y level correction ( Brightness, Contrast, Sharpness ) (23)
13.12.Auto Luminance Control (23)
13.13.Analog Gain Control (23)
13.14.Auto White Balance (24)
13.15.Auto Flicker Detection and Correction (24)
13.16.Image sizer (25)
13.17.Windowing (25)
13.18.Digital zooming (25)
13.19.Mirror and Flip (25)
13.20.Picture effects (26)
JT8EV5-AS-200
Preliminary
Data sheet 13.21.Statistical data output (26)
13.22.AF function (27)
13.22.1.Internal actuator driver (27)
13.23.OTP (28)
13.24.Test chart output (28)
13.25.Vender code (28)
14.Timing Chart (29)
14.1.Power management mode (29)
14.2.Power on/off sequence (30)
14.2.1.Power on sequence (w/ built-in regulator) (30)
14.2.2.Power off sequence (w/ built-in regulator) (30)
14.2.3.Output signal waveform (31)
15.Register descriptions (32)
16.Electrical Characteristics (66)
16.1.Maximum Ratings (66)
16.2.Recommended Operating Conditions (66)
16.3.DC Characteristics TBD (67)
16.4.AC Characteristics (68)
16.4.1.Clock (68)
16.4.2.SDA and SCL (69)
16.4.3.DOUT9 to DOUT0, DCLK, HBLK, VBLK (70)
16.5.CSI-2 Characteristics TBD (71)
17.Reference of Application circuit (76)
17.1.Parallel output and using internal actuator driver (76)
17.2.Serial output and using internal actuator driver (77)
18.Spectral Response without IR cut filter (78)
19.Characteristics recommended IR Cut Filter (78)
20.Reference of Chief Ray Angel (79)
RESTRICTIONS ON PRODUCT USE (81)
1.List of Abbreviation
Abbreviation Description
ISP Image Signal Processor
CDS Correlated Double Sampling
ADC Analog to Digital Converter
PLL Phase Locked Loop
VCO Variable Controlled Oscillator
PROcessor
PPRO Pre
MPRO Main
PROcessor
APRO After signal PROcessor
ALC Auto Luminance Control (≒AE)
AE Auto
Exposure
Focus
AF Auto
QSXGA Quad Super XGA (2560 x 2048)
QXGA Quad XGA (2048 x 1536)
UXGA Ultra XGA (1600 x 1200)
SXGA Super XGA (1280 x 1024)
Quad VGA Quad VGA (1280 x 960)
XGA eXtended Graphics Array (1024 x 768)
SVGA Super VGA (800 x 600)
VGA Video Graph Array (640 x 480)
CIF Common Intermediate Format (352 x 288)
QVGA Quarter VGA (320 x 240)
QCIF Quarter CIF (176 x 144)
QQVGA Quarter Quarter VGA (160 x 120)
subQCIF subQCIF (128 x96)
1080P 1920x1080
720P 1280x720
Image area Aperture area of the sensor (2696 x 2028)
Effective pixel area It is the pixel area that is the signal output is available. (2634 x 1956) GPIO General Purpose Input / Output port
Table 2 Abbreviation
2.
Block Diagram
2.1.
Block Diagram
SCL
SDA DA1_P/M
CLK_P/M ADRSEL
DCLK/HSYNC/VSYNC DOUT[9:2]ISINK
V P G M
M O D E
O C D I C K
O C D I O
MSDA/MSCL ADCIN PWM[0:1]
for external actuator driver (e.g. Piezo)
for debugger
for parallel output
for CSI-2 output
Figure 1 Block diagram
2.2. I/O circuit
Figure 2 I/O circuits (1/2)
IOVDD
IOVSS Figure 3 I/O circuits (2/2)
3.Pad Description
Pad
No. Pad name I/O Description Pad
No.Pad name I/O Description
1 AMON1 - Terminal for test45 DVDD1
2 - Power supply for digital circuits
2 AVDD28 - Power supply for analog circuit46 DVDD12 - Power supply for digital circuits
3 BSTNEG - Capacitor connection for booster47 TEST3 I Terminal for test
4 AVSS28 - GND for analog circuits48 DVSS12 - GND for digital and I/O circuits
5 VBSTNREG - Capacitor connection for booster49 DVSS12 - GND for digital and I/O circuits
6 DVDD12 - Power supply for digital circuits50 TEST4 I Terminal for test
7 DVSS12 - GND for digital and I/O circuits 51 XRESET I Low active reset signal input for test
8 RVSS18 - GND for a regulator52 XSHUTDOWN I Low active power down and reset signal input
9 VDIG18 - Power supply for regulator53 AVDD28 - Power supply for analog circuit
10 VDIG18 - Power supply for regulator54 AVSS28 - GND for analog circuits
11 DVCON12 - Regulator output55 DVDD12 - Power supply for digital circuits
12 DVCON12 - Regulator output56 DVSS12 - GND for digital and I/O circuits
13 DVSS12 - GND for digital and I/O circuits 57 OCDIO I/O Terminals for F/W debagging
14 ADRSEL I Slave address select for I2C-bus58 OCDICK I/O Terminals for F/W debagging
15 IOVDD18 - Power supply for I/O circuits59 MODE I Terminals for F/W debagging
16 DCLK O Clock for data output60 IOVDD18 - Power supply for I/O circuits
17 DOUT0 O Parallel data output (10bits)61 PWM0 I/O PWM output
18 DOUT1 O Parallel data output (10bits)62 MSCL I/O I2C-bus for the communication to a external actuator driver
19 DOUT2 O Parallel data output (10bits)63 PWM1 I/O PWM output
20 DOUT3 O Parallel data output (10bits)64 MSDA I/O I2C-bus for the communication to a external actuator driver
21 DOUT4 O Parallel data output (10bits)65 SCAN I Terminal for test
22 DOUT5 O Parallel data output (10bits)66 DVDD12 - Power supply for digital circuits
23 DVDD12 - Power supply for digital circuits67 DVSS12 - GND for digital and I/O circuits
24 DVSS12 - GND for digital and I/O circuits 68 EXTCLK I Master clock input
25 TEST1 I Terminal for test69 LVSS28 - GND for MIPI circuit
26 DOUT6 O Parallel data output (10bits)70 AMON0 - Terminal for test
27 DOUT7 O Parallel data output (10bits)71 LVDD28 - Power supply for MIPI circuits
28 DOUT8 O Parallel data output (10bits)72 DA1_P O Terminals for MIPI output
29 DOUT9 O Parallel data output (10bits)73 DA1_M O Terminals for MIPI output
30 TEST2 I Terminal for test74 LVSS28 - GND for MIPI circuit
31 IOVDD18 - Power supply for I/O circuits75 CLK_P O Terminals for MIPI output
32 HSYNC O Horizontal synchronization pulse76 CLK_M O Terminals for MIPI output
33 VSYNC O Vertical synchronization pulse77 LVDD28 - Power supply for MIPI circuits
34 DVSS12 - GND for digital and I/O circuits 78 DVSS12 - GND for digital and I/O circuits
35 DVDD12 - Power supply for digital circuits79 DVDD12 - Power supply for digital circuits
36 AVSS28 - GND for analog circuits80 AFVSS28 - GND for actuator driver
37 AVDD28 - Power supply for analog circuit81 ADCIN I Input signal for ADC
38 SDA I/O Serial data for I2C-bus82 AFVDD28 - Power supply for actuator driver
39 SCL I Serial clock for I2C-bus83 VCMVSS28 - GND for DAC of actuator driver
40 DVSS12 - GND for digital and I/O circuits 84 VCMVSS28 - GND for DAC of actuator driver
41 DVSS12 - GND for digital and I/O circuits 85 ISINK I Current sink for Actuator
42 VPGM - Power supply for writing OTP86 ISINK I Current sink for Actuator
43 DVDD12 - Power supply for digital circuits87 AVDD28 - Power supply for analog circuit
44 DVDD12 - Power supply for digital circuits88 AVSS28 - GND for analog circuits
- 89 BSTPOS - Capacitor connection for booster
Table 3 Pad description
4.Pixel Arrangement
Image area : 2696 x 2028 pixels (3774.4 x 2839.2 μm)
Effective pixel area : 2624 x 1956 pixels (3673.6 x 3673.6μm)
Figure 4 Pixel arrangement
5. Chip Layout
*Die size: X=6100μm, Y=5900μm (including scribe line) *Thickness of die (wafer): 200 +/-25μm
Figure 5 Chip layout (Do not scale drawing)
42
44
45
49
48
Width of scribe line
100μm
Figure 6 Dicing line
Figure 7 Pad size and aperture
6.
Pad Coordinates
Unit(μm)
Include scribe line Without scribe line
Include scribe line Without scribe line
Pad No. Pad name X Y X Y Pad
No.Pad name X Y X Y 1 AMON1 50.00 406.50 100.00 456.50 45 DVDD12 5854.50 5750.00 5904.50 5800.00 2 AVDD28 50.00 281.50 100.00 331.50 46 DVDD12 5729.50 5750.00 5779.50 5800.00 3 BSTNEG 145.50 50.00 195.50 100.00 47 TEST3 5629.50 5750.00 5679.50 5800.00 4 AVSS28 295.50 50.00 345.50 100.00 48 DVSS12 5529.50 5750.00 5579.50 5800.00 5 VBSTNREG 420.50 50.00 470.50 100.00 49 DVSS12 5404.50 5750.00 5454.50 5800.00 6 DVDD12 545.50 50.00 595.50 100.00 50 TEST4 5304.50 5750.00 5354.50 5800.00 7 DVSS12 695.50 50.00 745.50 100.00 51 XRESET 5204.50 5750.00 5254.50 5800.00 8 RVSS18 1012.80 50.00 1062.80 100.00 52 XSHUTDOWN 5079.50 5750.00 5129.50 5800.00 9 VDIG18 1137.80 50.00 1187.80 100.00 53 AVDD28 4954.50 5750.00 5004.50 5800.00 10 VDIG18 1262.80 50.00 1312.80 100.00 54 AVSS28 4729.50 5750.00 4779.50 5800.00 11 DVCON12 1594.25 50.00 1644.25 100.00 55 DVDD12 4604.50 5750.00 4654.50 5800.00 12 DVCON12 1719.25 50.00 1769.25 100.00 56 DVSS12 4479.50 5750.00 4529.50 5800.00 13 DVSS12 1879.50 50.00 1929.50 100.00 57 OCDIO 4254.50 5750.00 4304.50 5800.00 14 ADRSEL 2004.50 50.00 2054.50 100.00 58 OCDICK 4129.50 5750.00 4179.50 5800.00 15 IOVDD18 2129.50 50.00 2179.50 100.00 59 MODE 4004.50 5750.00 4054.50 5800.00 16 DCLK 2254.50 50.00 2304.50 100.00 60 IOVDD18 3879.50 5750.00 3929.50 5800.00 17 DOUT0 2379.50 50.00 2429.50 100.00 61 PWM0 3754.50 5750.00 3804.50 5800.00 18 DOUT1 2504.50 50.00 2554.50 100.00 62 MSCL 3654.50 5750.00 3704.50 5800.00 19 DOUT2 2629.50 50.00 2679.50 100.00 63 PWM1 3554.50 5750.00 3604.50 5800.00 20 DOUT3 2754.50 50.00 2804.50 100.00 64 MSDA 3454.50 5750.00 3504.50 5800.00 21 DOUT4 2879.50 50.00 2929.50 100.00 65 SCAN 3354.50 5750.00 3404.50 5800.00 22 DOUT5 3004.50 50.00 3054.50 100.00 66 DVDD12 3254.50 5750.00 3304.50 5800.00 23 DVDD12 3129.50 50.00 3179.50 100.00 67 DVSS12 3129.50 5750.00 3179.50 5800.00 24 DVSS12 3254.50 50.00 3304.50 100.00 68 EXTCLK 2959.50 5750.00 3009.50 5800.00 25 TEST1 3354.50 50.00 3404.50 100.00 69 LVSS28 2784.49 5750.00 2834.49 5800.00 26 DOUT6 3454.50 50.00 3504.50 100.00 70 AMON0 2659.49 5750.00 2709.49 5800.00 27 DOUT7 3579.50 50.00 3629.50 100.00 71 LVDD28 2396.49 5750.00 2446.49 5800.00 28 DOUT8 3704.50 50.00 3754.50 100.00 72 DA1_P 2271.49 5750.00 2321.49 5800.00 29 DOUT9 3829.50 50.00 3879.50 100.00 73 DA1_M 2146.49 5750.00 2196.49 5800.00 30 TEST2 3929.50 50.00 3979.50 100.00 74 LVSS28 2021.49 5750.00 2071.49 5800.00 31 IOVDD18 4029.50 50.00 4079.50 100.00 75 CLK_P 1896.49 5750.00 1946.49 5800.00 32 HSYNC 4154.50 50.00 4204.50 100.00 76 CLK_M 1771.49 5750.00 1821.49 5800.00 33 VSYNC 4279.50 50.00 4329.50 100.00 77 LVDD28 1646.49 5750.00 1696.49 5800.00 34 DVSS12 4404.50 50.00 4454.50 100.00 78 DVSS12 1510.50 5750.00 1560.50 5800.00 35 DVDD12 4529.50 50.00 4579.50 100.00 79 DVDD12 1385.50 5750.00 1435.50 5800.00 36 AVSS28 4654.50 50.00 4704.50 100.00 80 AFVSS28 1255.50 5750.00 1305.50 5800.00 37 AVDD28 4879.50 50.00 4929.50 100.00 81 ADCIN 1130.50 5750.00 1180.50 5800.00 38 SDA 5004.50 50.00 5054.50 100.00 82 AFVDD28 1005.50 5750.00 1055.50 5800.00 39 SCL 5129.50 50.00 5179.50 100.00 83 VCMVSS28 880.50 5750.00 930.50 5800.00 40 DVSS12 5254.50 50.00 5304.50 100.00 84 VCMVSS28 755.50 5750.00 805.50 5800.00 41 DVSS12 5379.50 50.00 5429.50 100.00 85 ISINK 630.50 5750.00 680.50 5800.00 42 VPGM 5604.50 50.00 5654.50 100.00 86 ISINK 505.50 5750.00 555.50 5800.00 43 DVDD12 5729.50 50.00 5779.50 100.00 87 AVDD28 270.50 5750.00 320.50 5800.00 44
DVDD12
5854.50
50.00
5904.50
100.00
88 AVSS28 145.50 5750.00 195.50 5800.00
89
BSTPOS
50.00 5505.00
100.00
5555.00
Table 4 Pad coordinates
7. I 2C Control Interface
JT8EV5-AS controls interface configuration is based on fast mode I 2C bus.
Register setting can be changed via I 2
C bus. All register settings are readable via I 2C bus.
7.1.
General
Figure 8 Write/Read mode
Start condition, End condition Bit Transfer
Acknowledge Not Acknowledge
Figure 9 Start/End condition
Note:
The system conforms to the I 2C Standard Specification as defined by Philips.
P SCL
SDA
Start condition End conditon SCL
SDA
S SCL from master SDA
from reciver HiZ SDA from trancemitter 189HiZ ACK
SCL
from master
SDA from reciver
SDA
7.2.Slave address
JT8EV5-AS has a 2 byte address table. Slave address is 78h/7Ah. It is chosen by terminal ADRSEL.
W : 78h (or 7Ah)
R : 79h (or 7Bh)
Bit Data
A6 0
A5 1
A4 1
A3 1
A2 1
A1 0
A0 ADRSEL (Pad 40)
R/W 1/0
Table 5 Slave address
8. Power supply
JT8EV5-AS needs power supply 2.8V, 1.8V and 1.2V.
2.8V is for Analog, 1.8V is for regulator, 1.2V is for digital, and IOVDD is also needed power supply between 1.7V and 3V for interface.
8.1.
Power Supply terminals
Pad No. Signal name
I/O
Description
6 23 35 43 44 45 46 55 66 79 DVDD12 - Power supply for digital circuits (1.1 to 1.3V)
2 37 5
3 87 AVDD28 - Power supply for analog circuits (2.6 to 3.0V) 71 77 LVDD28 - Power supply for MIPI circuits (2.6 to 3.0V) 82 AFVDD28 - Power supply for actuator driver 42 VPGM - Power supply for writing e-fuse OTP 15 31 60 IOVDD18 - Power supply for I/O circuits (1.7 to 3.0V) 9 10 VDIG18 - Power supply for regulator (1.7 to 1.9V) 11 12 DVCON12
-
Regulator output (1.2V)
7 13 24 34 40 41 48 49 56 67 78 DVSS12 - System ground for digital circuits and I/O circuits
4 36 54 88 AVSS28 - System ground for analog circuits 69 74 LVSS28 System ground for MIPI circuit 80 AFVSS28 - System ground for actuator driver 83 84 VCMVSS28 - System ground for DAC of actuator driver 8
RVSS18
-
System ground for a regulator
Table 6 Power supply terminals
8.2.
Using a built-in regulator
JT8EV5-AS has a built-in regulator. If you want to use regulator, you can only supply 2.8V and 1.8V both. Built-in regulator needs 1.8V to VSIG18, then connect to DVDD12 at regulator output DVCON12.
Figure 10 Using built-in regulator
IOVDD (1.8V)AVDD (2.8V)
VDIG (1.8V)
9. Readout Modes
The sensor core of JT8EV5-AS supports horizontal and vertical binning and horizontal cropping.
The horizontal binning mode is 1/2 line averaging, the vertical binning modes are 1/2,1/3,1/4,1/5,1/6,1/7 and 1/8 line averaging. The cropping mode is available to set arbitrary lines by 2lines unit. The every mode can increase frame rate.
About the more details of every modes, please refer to term from 13.18 to 13.20.
Figure 11 No binning and cropping
Figure 12 1/2 binning (Analog averaging)
Figure 13
1/4 binning (Analog averaging)
10. Clock settings
JT8EV5-AS is acceptable input clock frequency between 9MHz and 27MHz.
The clock diagram figure is shown below. The frequency of VCO output is limited from 500MHz to 1GHz. And the frequency of phase comparator input is limited from 2.5MHz to 27MHz.
At power on, the clock circuit generated DCLK (output clock) and internal clock operate at default clock settings. Therefore, there is a possibility that the circuit operates more than the maximum operation frequency because the input frequency is uncertain.
After power on, the user should set PLL settings first, set the other settings afterwards, and do the output permission setting at the end.
Figure 14 Clock diagram
11. Frame rate
JT8EV5-AS can operate 7.5 fps or less in Full output mode.
Setting examples :
Mode
Output Format
EXTCLK (MHz)
Horizontal Biinig
Vretical Binning
HTOTAL
VTOTAL
VCO Output
(MHz)
SPCK (MHz)
DCLK (MHz)
Frame Rate (fps)
Default 2592x1944 YUV422 24.0 1/1 1/1 8416 1976 624 124.8 78.0 7.49 Capture
2592x1944 JPEG +Thumbnail
24.0 1/1 1/1 6320 1976 624 124.8
78.0 9.99 Preview 1080P YUV422 24.0 1/1 1/1
6424 1496 624 124.8
78.0 12.99Preview 1080P JPEG 24.0 1/1 1/1 2784 1496 624 124.8 78.0 29.96Preview 720P YUV422 24.0 1/2 1/2 5424 768 624 124.8 78.0 29.96
Preview
VGA
YUV422 24.0 1/2
1/4 2400 520 624 124.8 78.0
100.0
HTOTAL=HCOUT x 8, VTOTAL=VCOUNT x 8
Table 7 Example of frame rate setting
12.Data Formats
The data formats of JT8EV5-AS are available YUV422, RGB565, Raw 10 and Jpeg output . Data format is
selectable by I2C commands.
Data format
8bit UYVY
8bit YUYV
YUV422
8bit VYUY
8bit YVYU
rf (8bit Blue first)
RGB565
bf (8bit Red first)
Raw 10bit parallel only
Jpeg
Jpeg and Thumbnail Thumbnail is RGB565 data
Table 8 Data formats
ordering
output
YUV422
Mode Data sequence
Normal (Default) U n Y n V n Y n+1
Swapped U-V V n Y n U n Y n+1
Swapped Y-UV Y n U n Y n+1V n
Swapped Y-U-V Y n V n Y n+1U n
ordering
output
RGB565
Red
first
first
Blue
1st 2nd 1st 2nd
DOUT9 G[4] R[7] DOUT9 R[7] G[4]
DOUT8 G[3] R[6] DOUT8 R[6] G[3]
DOUT7 G[2] R[5] DOUT7 R[5] G[2]
DOUT6 B[7] R[4] DOUT6 R[4] B[7]
DOUT5 B[6] R[3] DOUT5 R[3] B[6]
DOUT4 B[5] G[7] DOUT4 G[7] B[5]
DOUT3 B[4] G[6] DOUT3 G[6] B[4]
DOUT2 B[3] G[5] DOUT2 G[5] B[3]
DOUT1 L L DOUT1 L L
DOUT0 L L DOUT0 L L
output
ordering
ordering JPEG
Raw
10bits
output output
DOUT9 RAW[9] DOUT9 DATA[7]
DOUT8 RAW[8] DOUT8 DATA[6]
DOUT7 RAW[7] DOUT7 DATA[5]
DOUT6 RAW[6] DOUT6 DATA[4]
DOUT5 RAW[5] DOUT5 DATA[3]
DOUT4 RAW[4] DOUT4 DATA[2]
DOUT3 RAW[3] DOUT3 DATA[1]
DOUT2 RAW[2] DOUT2 DATA[0]
DOUT1 RAW[1] DOUT1 L
DOUT0 RAW[0] DOUT0 L
Table 9 Output ordering