Data Sheet, Rev.1.0, Apr. 2005
Memory Products
N e v e r s t o p t h i n k i n g.
Edition 2005-04
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
? Infineon Technologies AG 2005.
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Data Sheet, Rev.1.0, Apr. 2005
HYS64D32000HDL–[5/6]–C
HYS64D64020HDL–[5/6]–C
200-Pin Small-Outline Dual-In-Line Memory Modules
SO-DIMM
DDR SDRAM
RoHS Compliant Products
Memory Products
N e v e r s t o p t h i n k i n g.
HYS64D32000HDL–[5/6]–C, HYS64D64020HDL–[5/6]–C
Revision History:Rev.1.02005-04 Previous Version:
Page Subjects (major changes since last revision)
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Template: mp_a4_v2.0_2003-06-06.fm
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Table of Contents
1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Data Sheet5Rev.1.0, 2005-04
Data Sheet 6
Rev.1.0, 2005-04
07122004-E7F5-5R65
200-Pin Small-Outline Dual-In-Line Memory Modules SO-DIMM HYS64D32000HDL–[5/6]–C HYS64D64020HDL–[5/6]–C
1
Overview
1.1
Features
?Non-parity 200-Pin Small-Outline Dual-In-Line Memory Modules ?One rank 32M ×64 and two ranks 64M ×64 organization
?Standard Double Data Rate Synchronous DRAMs (DDR SDRAM)
?Single +2.5V
(±0.2V) power supply and +2.6V (±0.1V) for DDR400
?Built with 512Mbit DDR SDRAMs organized as ×16 in P–TSOPII–66 packages
?Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)?Auto Refresh (CBR) and Self Refresh ?All inputs and outputs SSTL_2 compatible ?Serial Presence Detect with E 2PROM
?Standard form factor: 67.60mm ×31.75mm ×3.80 mm ?Standard reference layout Raw Cards A and C ?Gold plated contacts
?
RoHS Compliant Products 1)
1.2Description
The HYS64D32000HDL–[5/6]–C and HYS64D64020HDL–[5/6]–C are industry standard 200-Pin Small-Outline Dual-In-Line Memory Modules (SO-DIMMs) organized as 64M ×64. The memory array is designed with Double Data Rate Synchronous DRAMs (DDR SDRAM). A variety of de coupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E 2PROM device using the 2-pin I 2C protocol.The first 128bytes are programmed with configuration data and the second 128bytes are available to the customer.
1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Table 1
Performance
Part Number Speed Code –5–6Unit Speed Grade Component DDR400B DDR333B —Module PC3200–3033
PC2700–2533—max. Clock Frequency
@CL3f CK3200166MHz @CL2.5f CK2.5166166MHz @CL2
f CK2
133
133
MHz
Data Sheet 7
Rev.1.0, 2005-04
07122004-E7F5-5R65
HYS64D[32/64][000/020]HDL–[5/6]–C Small-Outline DDR SDRAM Modules
Overview
Table 2Ordering Information for Lead-Free(RoHS Compliant Products)
Product Type 1)1)
All product types end with a place code designating the silicon-die revision. Reference information available on request.
Example: HYS64D64020GDL–5–B, indicating Rev.B die are used for SDRAM components.
Compliance Code 2)2)The Compliance Code is printed on the module labels and describes the speed sort (for example “PC3200”), the latencies
(for example “30330” means CAS latency of 3.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Pre-charge latency of 3 clocks), JEDEC SPD code definition version 1, and the Raw Card used for this module.
Description
SDRAM Technology
PC3200 (CL=3.0)HYS64D32000HDL–5–C PC3200S-3033–1–C0One rank 256MB SO-DIMM 512MBit (×16)HYS64D64020HDL–5–C PC3200S-3033–1–A0Two ranks 512MB SO-DIMM 512MBit (×16)PC2700 (CL=2.5)HYS64D32000HDL–6–C PC2700S–2533–1–C0One rank 256MB SO-DIMM 512MBit (×16)HYS64D64020HDL–6–C
PC2700S-2533–1–A0
Two ranks 512MB SO-DIMM 512MBit (×16)
HYS64D[32/64][000/020]HDL–[5/6]–C Small-Outline DDR SDRAM Modules
Pin Configuration
Data Sheet 8
Rev.1.0, 2005-04
2Pin Configuration
The pin configuration of the Unbuffered Small Outline DDR SDRAM DIMM is listed by function in Table 3(200 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 4 and Table 5respectively. The pin numbering is depicted in Figure 1.Table 3Pin Configuration of SO-DIMM
Pin#
Name
Pin Type Buffer Type Function Clock Signals 35CK0I SSTL Clock Signal 160CK1I SSTL Clock Signal 89
CK2
I
SSTL
Clock Signal Note:ECC type
module
NC
NC –Note:non-ECC type
module 37CK0I SSTL Complement Clock 158CK1I SSTL Complement Clock 91
CK2
I
SSTL
Complement Clock Note:ECC type
module
NC
NC –Note:non-ECC type
module 96CKE0I SSTL Clock Enable Rank 095
CKE1I SSTL Clock Enable Rank 1Note:2-rank module NC
NC –Note:1-rank module
Control Signals
121S0I SSTL Chip Select Rank 0122
S1I SSTL Chip Select Rank 1Note:2-ranks module NC
NC –Note:1-rank module 118RAS I SSTL Row Address Strobe
120CAS I SSTL Column Address Strobe 119WE I SSTL Write Enable Address Signals
117BA0I SSTL Bank Address Bus 1:0
116
BA1
I
SSTL
112A0I SSTL Address Bus 11:0
111A1I SSTL 110A2I SSTL 109A3I SSTL 108A4I SSTL 107A5I SSTL 106A6I SSTL 105A7I SSTL 102A8I SSTL 101A9I SSTL 115A10I SSTL AP I SSTL 100A11I SSTL 99
A12
I
SSTL
Address Signal 12Note:Module based
on 256Mbit or larger dies
NC
NC –Note:128Mbit based
module 123
A13
I
SSTL
Address Signal 13Note:1Gbit based
module
NC
NC
–
Note:Module based
on 512Mbit or smaller dies Data Signals 5DQ0I/O SSTL Data Bus 63:07DQ1I/O SSTL 13DQ2I/O SSTL 17DQ3I/O SSTL 6DQ4I/O SSTL 8DQ5I/O SSTL 14DQ6I/O SSTL 18DQ7I/O SSTL 19DQ8I/O SSTL 23DQ9I/O SSTL 29DQ10I/O SSTL 31DQ11I/O SSTL 20DQ12I/O SSTL 24
DQ13
I/O
SSTL
Table 3Pin Configuration of SO-DIMM (cont’d)
Pin#Name Pin Type Buffer Type Function
Data Sheet 9
Rev.1.0, 2005-04
HYS64D[32/64][000/020]HDL–[5/6]–C Small-Outline DDR SDRAM Modules
Pin Configuration
30DQ14I/O SSTL Data Bus 63:0
32DQ15I/O SSTL 41DQ16I/O SSTL 43DQ17I/O SSTL 49DQ18I/O SSTL 53DQ19I/O SSTL 42DQ20I/O SSTL 44DQ21I/O SSTL 50DQ22I/O SSTL 54DQ23I/O SSTL 55DQ24I/O SSTL 59DQ25I/O SSTL 65DQ26I/O SSTL 67DQ27I/O SSTL 56DQ28I/O SSTL 60DQ29I/O SSTL 66DQ30I/O SSTL 68DQ31I/O SSTL 127DQ32I/O SSTL 129DQ33I/O SSTL 135DQ34I/O SSTL 139DQ35I/O SSTL 128DQ36I/O SSTL 130DQ37I/O SSTL 136DQ38I/O SSTL 140DQ39I/O SSTL 141DQ40I/O SSTL 145DQ41I/O SSTL 151DQ42I/O SSTL 153DQ43I/O SSTL 142DQ44I/O SSTL 146DQ45I/O SSTL 152DQ46I/O SSTL 154DQ47I/O SSTL 163DQ48I/O SSTL 165DQ49I/O SSTL 171DQ50I/O SSTL 175DQ51I/O SSTL 164DQ52I/O SSTL 166
DQ53
I/O
SSTL
Table 3Pin Configuration of SO-DIMM (cont’d)
Pin#Name Pin Type Buffer Type Function 172DQ54I/O SSTL Data Bus 63:0
176DQ55I/O SSTL 177DQ56I/O SSTL 181DQ57I/O SSTL 187DQ58I/O SSTL 189DQ59I/O SSTL 178DQ60I/O SSTL 182DQ61I/O SSTL 188DQ62I/O SSTL 190DQ63I/O SSTL 71
CB0
I/O
SSTL
Check Bit 0
Note:ECC type
module NC NC –Note:Non-ECC
module 73
CB1
I/O
SSTL
Check Bit 1
Note:ECC type
module NC
NC
–
Note:Non-ECC
module 79
CB2
I/O
SSTL
Check Bit 2
Note:ECC type
module NC NC –Note:Non-ECC
module 83
CB3
I/O
SSTL
Check Bit 3
Note:ECC type
module NC
NC
–
Note:Non-ECC
module 72
CB4
I/O
SSTL
Check Bit 4
Note:ECC type
module NC NC –Note:Non-ECC
module 74
CB5
I/O
SSTL
Check Bit 5
Note:ECC type
module NC
NC
–
Note:Non-ECC
module Table 3Pin Configuration of SO-DIMM (cont’d)
Pin#Name Pin Type Buffer Type Function
HYS64D[32/64][000/020]HDL–[5/6]–C Small-Outline DDR SDRAM Modules
Pin Configuration
Data Sheet 10
Rev.1.0, 2005-04
80
CB6
I/O
SSTL
Check Bit 6
Note:ECC type
module
NC
NC –Note:Non-ECC
module 84
CB7
I/O
SSTL
Check Bit 7
Note:ECC type
module
NC
NC –Note:Non-ECC
module 11DQS0I/O SSTL Data Strobes 7:0Note:See block
diagram for corresponding DQ signals
25DQS1I/O SSTL 47DQS2I/O SSTL 61DQS3I/O SSTL 133DQS4I/O SSTL 147DQS5I/O SSTL 169DQS6I/O SSTL 183DQS7I/O SSTL 77
DQS8
I/O
SSTL
Data Strobe 8Note:ECC type
module
NC
NC –Note:Non-ECC
module 12DM0I SSTL Data Mask 7:026DM1I SSTL 48DM2I SSTL 62DM3I SSTL 134DM4I SSTL 148DM5I SSTL 170DM6I SSTL 184DM7I SSTL 78
DM8
I
SSTL
Data Mask 8Note:ECC type
module
NC
NC
–
Note:Non-ECC
module EEPROM 195SCL I CMOS Serial Bus Clock 193SDA I/O OD
Serial Bus Data
194SA0I CMOS Slave Address Select Bus 2:0196SA1I CMOS 198
SA2
I
CMOS
Table 3Pin Configuration of SO-DIMM (cont’d)
Pin#Name Pin Type Buffer Type Function Power Supplies 1,2V REF
AI
–
I/O Reference Voltage
197V DDSPD PWR –EEPROM Power Supply 9,10,21,22,33,34,36,45,46,57,58,69,70,81,82,92,93,94,113,114,131,132,143,144,155,156,157,167,168,179,180,191,192
V DD
PWR –
Power Supply
Table 3Pin Configuration of SO-DIMM (cont’d)
Pin#
Name
Pin Type Buffer Type Function
Data Sheet 11Rev.1.0, 2005-04
HYS64D[32/64][000/020]HDL–[5/6]–C Small-Outline DDR SDRAM Modules
Pin Configuration
3,4,15,16,27,28,38, 39, 40,51,52,63,64,75,76,87,88, 90, 103,104,125,126,137,138,149,150,159,161,162,173,174,185,186V SS
GND –
Ground Plane
Other Pins
199
V DDID
O OD
V DD Identification
Note:Pin in tristate,
indicating V DD and V DDQ nets connected on PCB
Table 3Pin Configuration of SO-DIMM (cont’d)
Pin#Name Pin Type Buffer Type Function 85,86, 97, 98, 124,200
NC
NC
–
Not connected Note:Pins not
connected on Infineon SO DIMMs
Table 4Abbreviations for Pin Type
Abbreviation Description
I Standard input-only pin. Digital levels.O Output. Digital levels.
I/O I/O is a bidirectional input/output signal.AI Input. Analog levels.PWR Power GND Ground NC
Not Connected
Table 5Abbreviations for Buffer Type Abbreviation Description
SSTL Serial Stub Terminated Logic (SSTL2)LV-CMOS
Low Voltage CMOS CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
Table 3Pin Configuration of SO-DIMM (cont’d)
Pin#Name Pin Type Buffer Type Function
Table6Address Format
Density Organization Memory
Ranks SDRAMs# of
SDRAMs
# of row/bank/
columns bits
Refresh Period Interval
256MB32M×64132M×16413/2/108K64ms7.8μs 512MB64M×64232M×16813/2/108K64ms7.8μs
Data Sheet12Rev.1.0, 2005-04
Notes
1.V DD = V DDQ, therefore V DDID strap open
2.DQ, DQS, DM resistors are 22?±5%
Data Sheet13Rev.1.0, 2005-04
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Pin Configuration
Note:
1.V DD = V DDQ, therefore V DDID strap open
2.DQ, DQS, DM resistors are 22? ±5%
Data Sheet14Rev.1.0, 2005-04
HYS64D[32/64][000/020]HDL–[5/6]–C Small-Outline DDR SDRAM Modules
Electrical Characteristics
Data Sheet 15
Rev.1.0, 2005-04
07122004-E7F5-5R65
3
Electrical Characteristics
3.1
Operating Conditions
Attention:Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit.Absolute Maximum Ratings Parameter
Symbol
Values
Unit Note/ Test Condition
min.typ.max.
Voltage on I/O pins relative to V SS
V IN , V OUT
–0.5–V DDQ +0.5V
–Voltage on inputs relative to V SS V IN –1–+3.6V –Voltage on V DD supply relative to V SS V DD –1–+3.6V –Voltage on V DDQ supply relative to V SS V DDQ –1–+3.6V –Operating temperature (ambient)T A 0–+70°C –Storage temperature (plastic)T STG -55–+150°C –Power dissipation (per SDRAM component)P D –1–W –Short circuit output current I OUT
–
50–
mA
–
Electrical Characteristics and DC Operating Conditions Parameter
Symbol
Values Unit Note/Test Condition 1)
Min.Typ.Max.Device Supply Voltage
V DD
2.3 2.5 2.7V f CK ≤166MHz Device Supply Voltage V DD 2.5 2.6 2.7V f CK >166MHz 2)Output Supply Voltage V DDQ 2.3 2.5 2.7V f CK ≤166MHz 3)Output Supply Voltage V DDQ 2.5 2.6 2.7V f CK >166MHz 2)3)
EEPROM supply voltage V DDSPD 2.3 2.5
3.6V —Supply Voltage, I/O Supply Voltage V SS , V SSQ 00V —
Input Reference Voltage V REF
0.49 ×
V DDQ 0.5 × V DDQ 0.51 ×
V DDQ
V
4)I/O Termination Voltage (System)
V TT
V REF – 0.04V REF + 0.04V 5)Input High (Logic1) Voltage V IH(DC)V REF + 0.15
V DDQ + 0.3V 6)Input Low (Logic0) Voltage V IL(DC)–0.3V REF – 0.15V 6)Input Voltage Level, CK and CK Inputs V IN(DC)–0.3V DDQ + 0.3V 6)Input Differential Voltage, CK and CK Inputs V ID(DC)
0.36V DDQ + 0.6V
6)7)VI-Matching Pull-up Current to Pull-down Current
VI Ratio
0.71
1.4
—
8)
HYS64D[32/64][000/020]HDL–[5/6]–C Small-Outline DDR SDRAM Modules
Electrical Characteristics
Data Sheet 16
Rev.1.0, 2005-04
07122004-E7F5-5R65
Input Leakage Current
I I –2
2
μA
Any input 0V ≤V IN ≤V DD ; All other pins not under test =0V 9)
Output Leakage Current I OZ –55μA DQs are disabled; 0V ≤ V OUT ≤ V DDQ 9)
Output High Current, Normal Strength Driver I OH —–16.2mA V OUT = 1.95 V Output Low
Current,Normal Strength Driver
I OL
16.2
—
mA
V OUT = 0.35 V
1)0°C ≤ T A ≤ 70 °C; V DDQ = 2.5 V ± 0.2 V, V DD = +2.5 V ± 0.2 V; V DDQ = 2.6 V ± 0.1 V, V DD = +2.6 V ±0.1 V (DDR400); 2)DDR400 conditions apply for all clock frequencies above 166MHz
3)Under all conditions, V DDQ must be less than or equal to V DD .
4)Peak to peak AC noise on V REF may not exceed ±2% V REF (DC). V REF is also expected to track noise variations in V DDQ .5)V TT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal
to V REF , and must track variations in the DC level of V REF .6)Inputs are not recognized as valid until V REF stabilizes.
7)V ID is the magnitude of the difference between the input level on CK and the input level on CK.
8)The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation.9)Values are shown per pin.
Electrical Characteristics and DC Operating Conditions (cont’d)Parameter
Symbol
Values Unit Note/Test Condition 1)
Min.
Typ.
Max.
HYS64D[32/64][000/020]HDL–[5/6]–C Small-Outline DDR SDRAM Modules
Electrical Characteristics
Data Sheet 17
Rev.1.0, 2005-04
07122004-E7F5-5R65
3.2
Current Specification and Conditions
Table 7I DD Conditions
Parameter
Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles.
I DD0
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.I DD1Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ V IL,MAX
I DD2P Precharge Floating Standby Current
CS ≥ V IH,,MIN , all banks idle; CKE ≥ V IH,MIN ;
address and other control inputs changing once per clock cycle; V IN = V REF for DQ, DQS and DM.I DD2F
Precharge Quiet Standby Current
CS ≥ V IHMIN , all banks idle; CKE ≥V IH,MIN ; V IN = V REF for DQ, DQS and DM; address and other control inputs stable at ≥ V IH,MIN or ≤ V IL,MAX .
I DD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ V ILMAX ; V IN = V REF for DQ, DQS and DM.I DD3P Active Standby Current
one bank active; CS ≥ V IH,MIN ; CKE ≥ V IH,MIN ; t RC =t RAS,MAX ; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle.
I DD3N
Operating Current Read
one bank active; Burst Length =2; reads; continuous burst; address and control inputs changing once per clock cycle;50% of data outputs changing on every clock edge;
CL =2 for DDR266(A), CL =3 for DDR333 and DDR400B; I OUT =0mA I DD4R
Operating Current Write
one bank active; Burst Length =2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge;
CL =2 for DDR266(A), CL =3 for DDR333 and DDR400B I DD4W
Auto-Refresh Current t RC = t RFCMIN , burst refresh I DD5Self-Refresh Current
CKE ≤ 0.2 V; external clock on
I DD6Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
I DD7
HYS64D[32/64][000/020]HDL–[5/6]–C Small-Outline DDR SDRAM Modules
Electrical Characteristics
Data Sheet 18
Rev.1.0, 2005-04
07122004-E7F5-5R65
Table 8
I DD Specification for HYS64D[32/64]0x0HDL–5–C
Product Type HYS64D32000HDL–5–C HYS64D64020HDL–5–CC Unit
Note 1)2)
1)Module I DD values are calculated on the basis of component I DD and can be measured differently according to DQ loading
capacity.2)Test condition for maximum values: V DD =2.7V, T A =10°C
Organization
256MB 512MB ×64×641 Rank 2 Ranks –5
–5
Symbol Typ.Max.Typ.Max.I DD0300360450540mA 3)3)The module I DDx values are calculated from the I DDx values of the component data sheet as follows:
m ×I DDx [component]+n ×I DD3N [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules I DD1360440510620mA 3)4)4)DQ I/O (I DDQ ) currents are not included in the calculations (see note 1)
I DD2P 418937mA 5)5)The module I DDx values are calculated from the corrponent I DDx data sheet values as: (m + n ) × I DDx [component]
I DD2F 100120200240mA 5)I DD2Q 7090140180mA 5)I DD3P 5060100130mA 5)I DD3N 150180300360mA 5)I DD4R 440540590720mA 3)4)I DD4W 460540610720mA 3)I DD5580760730940mA 3)I DD6–12–24mA 5)I DD7
840
1000
990
1180
mA
3)4)
HYS64D[32/64][000/020]HDL–[5/6]–C Small-Outline DDR SDRAM Modules
Electrical Characteristics
Data Sheet 19
Rev.1.0, 2005-04
07122004-E7F5-5R65
Table 9
I DD Specification HYS64D[32/64]0x0HDL–6–C
Product Type HYS64D32000HDL–6–C HYS64D64020HDL–6–C Unit
Note 1)2)
1)Module I DD values are calculated on the basis of component I DD and can be measured differently according to DQ loading
capacity.2)Test condition for maximum values: V DD =2.7V, T A =10°C
Organization
256MB 512MB ×64×641 Rank 2 Ranks –6
–6
Symbol Typ.Max.Typ.Max.I DD0280340410500mA 3)3)The module I DDx values are calculated from the I DDx values of the component data sheet as follows:
m ×I DDx [component]+n ×I DD3N [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules I DD1320380450540mA 3)4)4)DQ I/O (I DDQ ) currents are not included in the calculations (see note 1)
I DD2P 418937mA 5)5)The module I DDx values are calculated from the corrponent I DDx data sheet values as: (m + n ) × I DDx [component]
I DD2F 80100170200mA 5)I DD2Q 6090120180mA 5)I DD3P 406090120mA 5)I DD3N 130160260320mA 5)I DD4R 380460510620mA 3)4)I DD4W 400480530640mA 3)I DD5520700650860mA 3)I DD6–12–24mA 5)I DD7
760
920
890
1080
mA
3)4)
HYS64D[32/64][000/020]HDL–[5/6]–C Small-Outline DDR SDRAM Modules
Electrical Characteristics
Data Sheet 20
Rev.1.0, 2005-04
07122004-E7F5-5R65
3.3AC Characteristics
AC Timing - Absolute Specifications for PC3200 and PC2700Parameter
Symbol –5
–6Unit
Note/ Test Condition 1)
DDR400B DDR333
Min.
Max.Min.Max.DQ output access time from CK/CK
t AC –0.7+0.5–0.7+0.7ns
2)3)4)5)CK high-level width t CH 0.450.550.450.55t CK
2)3)4)5)
Clock cycle time
t CK
58612ns CL = 3.0
2)3)4)5)612612ns CL = 2.5 2)3)4)5)7.5
127.512ns
CL = 2.0
2)3)4)5)
CK low-level width t CL
0.45
0.55
0.45
0.55
t CK 2)3)4)5)Auto precharge write recovery + precharge time
t DAL
(t WR /t CK ) + (t RP /t CK )t CK
2)3)4)5)6)DQ and DM input hold time t DH
0.4—0.45—ns 2)3)4)5)DQ and DM input pulse width (each input)
t DIPW
1.75— 1.75—ns 2)3)4)5)6)DQS output access time from CK/CK
t DQSCK –0.5+0.5–0.6+0.6ns
2)3)4)5)DQS input low (high) pulse width (write cycle)t DQSL,H 0.35—0.35—t CK
2)3)4)5)
DQS-DQ skew (DQS and associated DQ signals)t DQSQ —+0.40—+0.45ns
TSOPII
2)3)4)5)Write command to 1st DQS latching transition
t DQSS 0.72 1.250.75 1.25t CK
2)3)4)5)DQ and DM input setup time t DS 0.4—0.45—ns
2)3)4)5)DQS falling edge hold time from CK (write cycle)
t DSH
0.2—0.2—t CK 2)3)4)5)DQS falling edge to CK setup time (write cycle)
t DSS 0.2
—
0.2
—
t CK
2)3)4)5)Clock Half Period t HP
min. (t CL , t CH )—
min. (t CL , t CH )—ns 2)3)4)5)Data-out high-impedance time from CK/CK
t HZ
+0.7
–0.7+0.7ns 2)3)4)5)7)
Address and control input hold time
t IH 0.6—0.75—ns fast slew rate
3)4)5)6)8)
0.7
—
0.8
—
ns
slow slew rate
3)4)5)6)8)Control and Addr. input pulse width (each input)
t IPW 2.2— 2.2—ns
2)3)4)5)9)