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CXP83509中文资料

CMOS 8-bit Single Chip Microcomputer

Description

The CXP83508/83512/83516 and the CXP83509/83513/83517 are CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, sub timer/counter, LCD controller/driver and remote control reception circuit besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port.

The CXP83508/83512/83516 and the CXP83509/83513/83517 also provide a sleep/stop function that enables lower power consumption.

Features

?Wide-range instruction system (213 instructions) to cover various types of data.

— 16-bit arithmetic/multiplication and division/boolean bit operation instructions ?Minimum instruction cycle

400ns at 10MHz operation (4.5 to 5.5V)1μs at 4MHz operation (2.7 to 5.5V)122μs at 32kHz operation (2.7 to 5.5V)

?Incorporated ROM capacity

8K bytes (CXP83508, 83509)12K bytes (CXP83512, 83513)16K bytes (CXP83516, 83517)

?Incorporated RAM capacity

608bytes (includes LCD display data area and serial interface RAM)

?Peripheral functions — A/D converter 8-bit, 8-channel, successive approximation method

(Conversion time of 12.4μs/10MHz)

— Serial interface Incorporated buffer RAM

(Auto transfer for 1 to 32 bytes), 1 channel

8-bit clock synchronized type (MSB/LSB first selectable), 1 channel

— Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer,

Sub timer/counter

— LCD controller/driver Maximum 128 segment display possible (during 1/4 duty)

4 common output, 32 segment output Display method static, 1/2, 1/3, 1/4 duty Bias method 1/2, 1/3 bias

— Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO ?Interruption 14 factors, 14 vectors, multi-interruption possible ?Standby mode Sleep/stop ?Package 80-pin plastic QFP/LQFP ?Piggy/evaluation chip CXP83600 (CXP83508, 83512, 83516)

CXP83601 (CXP83509, 83513, 83517)Structure

Silicon gate CMOS IC

– 1–

E98133B96

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXP83508/83512/83516CXP83509/83513/83517

– 2–

X T A L

A N 0 t o A N 7

R M C S I 0S O 0S I 1S O 1E C C S 0S C K 0

S C K 1

N T 0N T 1N T 2N T 3T E X

T X

E X T A L

V D D V s s P C 0 t o P C 7

P H 0

P B 0 t o P B 7

P E 0 t o P E 4P E 5 t o P E 6

S E G 0 t o S E G 31C O M 0 t o C O M 3V L

V L C 1

V L C 2

P A 0 t o P A 7

P D 0 t o P D 7

P F 0 t o P F 7

V L C 3

A D J T O R S T

N T 4

P I 0 t o P I 1

B l o c k D i a g r a m

– 3–

PD6/SEG22PD5/SEG21PD4/SEG20PD3/SEG19PD2/SEG18PD1/SEG17PD0/SEG16SEG15SEG14SEG13SEG12SEG11SEG10SEG9SEG8SEG7SEG6SEG5SEG4SEG3SEG2SEG1SEG0COM3

P A 3/A N 3

P A 4/A N 4

P A 5/A N 5

P A 6/A N 6

P A 7/A N 7

R S T

E X T A L

X T A L

V S S

V L

V L C 3

V L C 2

V L C 1

C O M 0

C O M 1

C O M 2

P E 2/I N T 2

P E 1/I N T 1

P E 0/I N T 0/E C

P F 7/S E G 31

P F 6/S E G 30

N C

P I 1/T E X

P I 0/T X

V D D

P F 5/S E G 29

P F 4/S E G 28

P F 3/S E G 27

P F 2/S E G 26

P F 1/S E G 25

P F 0/S E G 24P D 7/S E G 23

Note) Do not make any connections to NC (Pin 75).

PE5/TO PE6/ADJ

PB0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7 PH0/INT4 PA0/AN0

PD4/SEG20

PD3/SEG19

PD2/SEG18

PD1/SEG17

PD0/SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

P

A

1

/

A

N

1

P

A

2

/

A

N

2

P

A

3

/

A

N

3

P

A

4

/

A

N

4

P

A

5

/

A

N

5

P

A

6

/

A

N

6

P

A

7

/

A

N

7

R

S

T

E

X

T

A

L

X

T

A

L

V

S

S

V

L

V

L

C

3

V

L

C

2

V

L

C

1

C

O

M

C

O

M

1

C

O

M

2

C

O

M

3

S

E

G

P

E

4

/

R

M

C

P

E

3

/

I

N

T

3

P

E

2

/

I

N

T

2

P

E

1

/

I

N

T

1

P

E

/

I

N

T

/

E

C

P

F

7

/

S

E

G

3

1

P

F

6

/

S

E

G

3

N

C

P

I

1

/

T

E

X

P

I

/

T

X

V

D

D

P

F

5

/

S

E

G

2

9

P

F

4

/

S

E

G

2

8

P

F

3

/

S

E

G

2

7

P

F

2

/

S

E

G

2

6

P

F

1

/

S

E

G

2

5

P

F

/

S

E

G

2

4

P

D

7

/

S

E

G

2

3

P

D

6

/

S

E

G

2

2

P

D

5

/

S

E

G

2

1

Note) Do not make any connections to NC (Pin 73).

– 4–

PE5/TO PE6/ADJ

PB0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7 PH0/INT4 PA0/AN0

PD4/SEG20

PD3/SEG19

PD2/SEG18

PD1/SEG17

PD0/SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

P

A

1

/

A

N

1

P

A

2

/

A

N

2

P

A

3

/

A

N

3

P

A

4

/

A

N

4

P

A

5

/

A

N

5

P

A

6

/

A

N

6

P

A

7

/

A

N

7

R

S

T

E

X

T

A

L

X

T

A

L

V

S

S

V

L

V

L

C

3

V

L

C

2

V

L

C

1

C

O

M

C

O

M

1

C

O

M

2

C

O

M

3

S

E

G

P

E

4

/

R

M

C

P

E

3

/

I

N

T

3

P

E

2

/

I

N

T

2

P

E

1

/

I

N

T

1

P

E

/

I

N

T

/

E

C

P

F

7

/

S

E

G

3

1

P

F

6

/

S

E

G

3

N

C

P

I

1

/

T

E

X

P

I

/

T

X

V

D

D

P

F

5

/

S

E

G

2

9

P

F

4

/

S

E

G

2

8

P

F

3

/

S

E

G

2

7

P

F

2

/

S

E

G

2

6

P

F

1

/

S

E

G

2

5

P

F

/

S

E

G

2

4

P

D

7

/

S

E

G

2

3

P

D

6

/

S

E

G

2

2

P

D

5

/

S

E

G

2

1

Note) Do not make any connections to NC (Pin 73).

– 5–

– 6–

Pin Description

Symbol

I/O

Functions

I/O/Analog input

PA0/AN0

to PA7/AN7

(Port A)

8-bit I/O port. I/O can be set in a bit unit.Standby release input can be set in a bit unit.Incorporation of pull-up resistor can be set through the program in a bit unit.(8 pins)

Analog inputs to A/D converter.(8 pins)

I/O

PC0 to PC7PE0/INT0/EC PE1/INT1PE2/INT2PE3/INT3PE4/RMC PE5/TO PE6/ADJ

PH0/INT4PI0/TX PI1/TEX

Input/Input/Input Input/Input Input/Input Input/Input Input/Input Output/Output Output/Output

I/O/Input

Input Input/Input

(Port C)

8-bit I/O port. I/O can be set in a bit unit. Capable of driving 12mA sink current. Incorporation of pull-up resistor can be set through the program in a bit unit.(8 pins)

(Port E)

7-bit port. Lower 5 bits are for inputs; upper 2bits are for outputs.(7 pins)

(Port H)

1-bit I/O port.

Incorporation of pull-up resistor can be set through the program.(1 pin)

(Port I)

2-bit input port. (2 pins)

External interruption request input.(1 pin)

Crystal connectors for sub timer/counter clock oscillation. For usage as event counter, input to TEX, and leave TX open.

External event inputs for 8-bit timer/counter.

External interruption request inputs.(4 pins)

Remote control reception circuit input.

Output for 8-bit timer/counter rectangular wave.Output for TEX oscillation frequency division.

I/O I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output

PB0PB1/CS0PB2/SCK0PB3/SI0PB4/SO0PB5/SCK1PB6/SI1PB7/SO1

(Port B)

8-bit I/O port. I/O can be set in a bit unit.

Incorporation of pull-up resistor can be set through the program in a bit unit. (8 pins)

Chip select input for serial interface (CH0).Serial clock I/O (CH0).Serial data input (CH0).Serial data output (CH0).Serial clock I/O (CH1).Serial data input (CH1).Serial data output (CH1).

– 7–

Symbol I/O Functions

Output/Output PF0/SEG24

to

PF7/SEG31(Port F)

8-bit output port.(8 pins)

Output/Output

PD0/SEG16

to

PD7/SEG23(Port D)

8-bit output port.(8 pins)Output SEG0 to SEG15LCD segment signal output. (16 pins)Input

Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL.EXTAL Output

COM0 to COM3LCD common signal output. (4 pins)V LC1to V LC3LCD bias power supply. (3 pins)

Output V L Control pin to cut off the current flowing to external LCD bias resistor during standby.

XTAL Input

Low-level active system reset.

NC. Do not make any connections to NC.Positive power supply.GND.

RST NC V DD V SS

LCD segment signal outputs.(16 pins)

I/O Circuit Format for Pins

– 8–

– 10–

– 11–

– 12–

– 13–

?1V IN and V OUT must not exceed V DD + 0.3V.

?2The high current drive transistor is the N-ch transistor of Port C (PC).

Note)Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.

Supply voltage LCD bias voltage Input voltage Output voltage

High level output current

High level total output current Low level output current Low level total output current Operating temperature Storage temperature

Allowable power dissipation V DD

V LC1, V LC2,

V LC3

V IN V OUT I OH

ΣI OH I OL I OLC ΣI OL Topr Tstg

P D –0.3 to +7.0

–0.3 to +7.0?1

–0.3 to +7.0?1–0.3 to +7.0?1

–5–501520100–20 to +75–55 to +150

600

380380

V V V V mA mA mA mA mA °C °C mW mW mW

Output per pin Total for all output pins

Value per pin, excluding high current

output pins

Value per pin for high current output pins ?2Total for all output pins

QFP-80P-L01LQFP-80P-L01QFP-80P-L03Item

Symbol Rating Unit Remarks

Absolute Maximum Ratings

(Vss = 0V)

– 14–

LCD bias voltage

High level input voltage

Low level input voltage

Operating temperature Supply voltage

5.55.55.5

V DD

V DD V DD

V DD + 0.3

0.3V DD 0.2V DD 0.4+75

V

V V V V V V °C

V Item

Symbol

Min.Max.Unit

Remarks

2.72.72.5

Vss

0.7V DD 0.8V DD

V DD – 0.400–0.3–20

V LC1

V LC2V LC3V IH

V IHS V IHEX V IL

V ILS V ILEX Topr

Guaranteed operation range during 1/16 frequency dividing mode or sleep mode Guaranteed operation range with TEX clock Guaranteed data hold range during stop

LCD power supply range ?4

?1

Hysteresis input ?2EXTAL ?3, TEX ?5?1

Hysteresis input ?2EXTAL ?3, TEX ?5

V DD

?1Value for each pin of normal input ports (PA, PB0, PB4, PB7, PC and PI).

?2Value of the following pins; RST, CS0, SI0, SI1, SCK0, SCK1, EC/INT0, INT1, INT2, INT3, INT4 and RMC.?3Specifies only during external clock input.?4Optimal values are determined by LCD used.?5

Specifies only during external event count input.

Recommended Operating Conditions

(Vss = 0V)

Guaranteed operation range

during 1/2 and 1/4 frequency

dividing mode

fc = 10MHz or less fc = 4MHz or less 4.52.7

5.55.5

– 15–

V DD = 4.5V, I OH = –1.0mA V DD = 4.5V, I OH = –2.4mA V DD = 4.5V, I OH = –0.5mA V DD = 4.5V, I OH = –1.2mA V DD = 4.5V, I OL = 1.8mA V DD = 4.5V, I OL = 3.6mA V DD = 4.5V, I OL = 12.0mA V DD = 5.5V, V IH = 5.5V V DD = 5.5V, V IL = 0.4V V DD = 5.5V, V IH = 5.5V

V DD = 5.5V V IL = 0.4V

V DD = 4.5V, V IH = 4.0V V DD = 5.5V

V I = 0, 5.5V V DD = 5V V LC1= 3.75V V LC2= 2.5V V LC3= 1.25V

High level

output voltage

I/O leakage current Supply current ?5

4.03.54.03.5

0.5–0.50.1–0.1

–1.5

–2.78

V V V V V V V V μA μA μA μA μA μA μA

k ?

k ?

PC

SCK0?1, SO0?1SCK1?1, SO1?1PA, PB, PC,PD ?2, PE5,PE6,

PF ?2, PH0,V L (V OL only)EXTAL

TEX RST ?3

Item

Symbol

Pins

Conditions

Min.PA to PC ?4,

PE0 to PE4,PH ?4, PI,

RST ?3

V DD

I IZ

Common output

impedance R COM Segment output

impedance

R SEG COM0 to

COM3SEG0 to SEG15,SEG16 to SEG31?2

I DD1

High-speed mode operation (1/2 frequency dividing clock)

I DDS1I DDS3

V OL

I IHE I ILE I IHT

I ILT I ILR I IL I IH

Low level

output voltage

Input current

3

5Typ.

0.40.61.5

40–4010–10–400–45

±10

515Max.

Unit DC Characteristics (V DD = 4.5 to 5.5V)

Electrical Characteristics

(Ta = –20 to +75°C, Vss = 0V)V DD = 5.5V, 10MHz crystal oscillation (C 1= C 2= 15pF)

Sleep mode

Stop mode

V DD = 5.5V, 10MHz crystal oscillation (C 1= C 2= 15pF)1240mA

2.68mA

V DD = 5.5V, 10MHz and termination of TEX oscillation

10μA

V OH

– 16–

?1Specifies when Port B output buffer capability switching register (BUFB: 01F4h) selects the buffer capability to high.

?2Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24 to PF7/SEG31, PD and PF is the case when the common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output.?3RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected.

?4Pins PA to PC, and PH0 specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. ?5When all output pins are left open.

Clock 1MHz 0V for all pins excluding measured pins

Input capacity 10

20

pF

PA to PC,

PE0 to PE4, PH,PI, EXTAL, RST Item Symbol Pins Conditions Min.C IN

Typ.Max.Unit

– 17–

V DD = 2.7V, I OH = –0.12mA V DD = 2.7V, I OH = –0.45mA V DD = 2.7V, I OL = 1.0mA V DD = 2.7V, I OL = 1.4mA V DD = 2.7V, I OL = 4.5mA V DD = 3.3V, V IH = 3.3V V DD = 3.3V, V IL = 0.3V V DD = 3.3V, V IH = 3.3V V DD = 3.3V V IL = 0.3V

V DD = 2.7V, V IH = 2.4V V DD = 3.3V

V I = 0, 3.3V V DD = 3V V LC1= 2.25V V LC2= 1.5V V LC3= 0.75V

High level

output voltage

I/O leakage current Supply current ?5

2.52.1

0.3–0.30.1–0.1–0.9

0.9

V V V V V V μA μA μA μA μA μA μA

k ?

k ?

PC

PA, PB, PC,PD ?2, PE5,PE6,

PF ?2, PH0,V L (V OL only)EXTAL

TEX RST ?3

Item

Symbol

Pins

Conditions

Min.PA to PC ?4,

PE0 to PE4,PH ?4, PI,

RST ?3

V DD

I IZ

Common output

impedance R COM Segment output

impedance

R SEG COM0 to

COM3SEG0 to SEG15,SEG16 to SEG31?2

I DD1

High-speed mode operation (1/2 frequency dividing clock)

I DDS1I DDS3

V OH

V OL

I IHE I ILE I IHT

I ILT I ILR I IL I IH

Low level

output voltage

Input current

4.5

10Typ.

0.250.40.920–2010–10–200–20

±10

7.530Max.

Unit I DD2

DC Characteristics (V DD = 2.7 to 3.3V)

Electrical Characteristics

(Ta = –20 to +75°C, Vss = 0V)V DD = 3.3V, 4MHz crystal oscillation (C 1= C 2= 15pF)

V DD = 3.3V, TEX ?6crystal oscillation (C 1= C 2= 47pF)

Sleep mode

Stop mode

V DD = 3.3V, 4MHz crystal oscillation (C 1= C 2= 15pF)

2.58mA

30100μA

0.62mA

I DDS2V DD = 3.3V, TEX ?6crystal oscillation (C 1= C 2= 47pF)V DD = 3.3V, 4MHz and termination of TEX oscillation

1630μA

10μA

SCK0?1, SO0?1SCK1?1, SO1?1V DD = 2.7V, I OH = –0.24mA V DD = 2.7V, I OH = –0.90mA 2.5V 2.1V

– 18–

Clock 1MHz

0V for all pins excluding

measured pins

Input capacity 1020pF

PA to PC,

PE0 to PE4,

PH, PI, EXTAL,

TEX, RST

Item Symbol Pins Conditions Min.C IN

Typ.Max.Unit

?1Specifies when Port B output buffer capability switching register (BUFB: 01F4h) selects the buffer capability to high.

?2Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24 to PF7/SEG31, PD and PF is the case when the common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output.?3RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected.

?4Pins PA to PC, and PH0 specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. ?5When all output pins are left open.

?6The value when 32.768kHz oscillator is connected to TEX.

– 19–

?1t sys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (CLC: 00FEh).

t

sys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”).

EXTAL

Crystal oscillation Ceramic oscillation

External clock

TEX clock applied condition Crystal oscillation

TEX EC

t TH

t TL

t TF

t TR

AC Characteristics (1) Clock timing

System clock frequency System clock input pulse width

System clock input rise and fall time

Event count input clock pulse width Event count input clock rise and fall time System clock frequency Event count input clock input pulse width

Event count input clock rise and fall time

f C

t XL , t XH t CR , t CF

t EH , t EL t ER , t EF

f C

t TL , t TH t TR , t TF

XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX

MHz

ns

ns ns

ms

kHz

μs ms

Item

Symbol Pin Conditions

Min.Unit Fig. 1, Fig. 2

Fig. 1, Fig. 2external clock drive Fig. 1, Fig. 2

external clock drive Fig. 3Fig. 3

V DD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition)Fig. 3Fig. 3

1137.577.5

t sys + 50?1

10

Typ.

32.768

Max.105

200

20

20

(Ta = –20 to +75°C, V DD = 2.7 to 5.5V, Vss = 0V)Fig. 2. Clock applied conditions

Fig. 1. Clock timing

Fig. 3. Event count clock timing

V DD = 4.5 to 5.5V

V DD = 4.5 to 5.5V

– 20–

Chip select transfer mode (SCK = output mode)Chip select transfer mode (SCK = output mode)Chip select transfer mode Chip select transfer mode Chip select transfer mode Note 1)t sys indicates the three values below according to the upper two bits (CPU clock selection) of the

clock control register (CLC: 00FEh).

t sys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)

Note 2)CS, SCK, SI and SO indicates CS0, SCK0, SI0 and SO0, respectively.

Note 3)The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL.

Note 4)The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer

capability to normal.

Item

CS ↓ →SCK delay time CS ↑ →SCK float delay time CS ↓ →SO delay time CS ↓ →SO float delay time CS high level width SCK cycle time SCK high and low level widths SI input setup time (for SCK ↑)SI input hold time (for SCK ↑)SCK ↓ → SO delay time

t DCSK t DCSKF t DCSO

t DCSOF t WHCS t KCY t KH t KL t SIK t KSI t KSO

SCK0SCK0SO0

SO0CS0SCK0

SCK0

SI0

SI0

SO0

Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode

ns ns ns ns ns Symbol

Pin Min.

t sys + 200t sys + 200t sys + 200t sys + 200

t sys + 2002t sys + 200

16000/fc

t sys + 100

8000/fc – 100–t sys + 100

2002t sys + 100

100

ns ns ns ns ns ns ns ns

ns ns

2t sys + 200

100

Max.

Unit Conditions

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