HD74HC595
8-bit Shift Register/Latch (with 3-state outputs)
REJ03D0634-0200
(Previous ADE-205-514)
Rev.2.00
Mar 30, 2006 Description
This device each contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading.
Both the shift register and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register state will always be one clock pulse ahead of the storage register.
Features
? High Speed Operation: t pd (RCK to Q) = 17 ns typ (C L = 50 pF)
? High Output Current: Fanout of 15 LSTTL Loads (Q A to Q H outputs)
? Wide Operating Voltage: V CC = 2 to 6 V
? Low Input Current: 1 μA max
? Low Quiescent Supply Current: I CC (static) = 4 μA max (Ta = 25°C)
? Ordering Information
Part Name Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74HC595P DILP-16
pin PRDP0016AE-B
(DP-16FV)
P —
HD74HC595FPEL SOP-16 pin (JEITA) PRSP0016DH-B
(FP-16DAV)
FP EL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability. Function Table
Pin Arrangement
Logic Diagram
Absolute Maximum Ratings
Item Symbol Ratings Unit
Supply voltage range V CC –0.5 to 7.0 V Input / Output voltage V IN , V OUT –0.5 to V CC +0.5
V
Input / Output diode current I IK , I OK ±20 mA
Output current I OUT
±35 mA
V CC , GND current I CC or I GND ±75 mA
Power dissipation
P T 500 mW
Storage temperature Tstg –65 to +150 °C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Recommended Operating Conditions
Item Symbol Ratings Unit Conditions
Supply voltage V CC 2 to 6 V Input / Output voltage V IN , V OUT 0 to V CC V Operating temperature Ta –40 to 85 °C 0 to 1000 V CC = 2.0 V 0 to 500
V CC = 4.5 V Input rise / fall time *1
t r , t f
0 to 400
ns
V CC = 6.0 V
Note: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Ta = 25°C
Ta = –40 to+85°C
Item Symbol V CC (V) Min Typ Max Min Max Unit
Test Conditions
2.0 1.5 — — 1.5 — 4.5
3.15 — — 3.15 —
V IH 6.0 4.2 — — 4.2 —
V
2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35
Input voltage V IL
6.0 — — 1.8 — 1.8 V 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — I OH = –20 μA
4.5 4.18 — — 4.13 —
I OH = –6 mA V OH
6.0 5.68 — — 5.63 —
V Q A to Q H Vin = V IH or V IL I OH = –7.8 mA
2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1
I OL = 20 μA
4.5 — — 0.26 — 0.33
I OL = 6 mA
Output voltage V OL
6.0 — — 0.26 — 0.33 V Q A to Q H Vin = V IH or V IL I OL =
7.8 mA 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — I OH = –20 μA
4.5 4.18 — — 4.13 —
I OH = –4 mA V OH
6.0 5.68 — — 5.63 —
V Q’H Vin = V IH or V IL I OH = –5.2 mA
2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1
I OL = 20 μA
4.5 — — 0.26 — 0.33
I OL = 4 mA
Output voltage V OL
6.0 — — 0.26 — 0.33 V Q’H Vin = V IH or V IL I OL = 5.2 mA
Off-state output
current
I OZ 6.0 — — ±0.5 — ±5.0 μA Vin = V IH or V IL ,
Vout = V CC or GND Input current
Iin 6.0 — — ±0.1 — ±1.0 μA Vin = V CC or GND Quiescent supply current I CC 6.0 — — 4.0 — 40 μA Vin = V CC or GND, Iout = 0 μA
Switching Characteristics (C L = 50 pF, Input t r = t f = 6 ns)
Ta = 25°C
Ta = –40 to +85°C
Item Symbol V CC (V) Min Typ Max Min Max Unit
Test Conditions
2.0 — — 5 — 4 4.5 — — 27 — 21
Maximum clock frequency f max 6.0 — — 31 — 24 MHz 2.0 — — 115 — 145 4.5 — 12 23 — 29 t PLH t PHL 6.0 — — 20 — 25 ns SCK to Q H ’ 2.0 — — 150 — 190 4.5 — 17 30 — 38
t PLH t PHL 6.0 — — 26 —
33
ns RCK to Q 2.0 — — 175 — 220 4.5 — 20 35 — 44 Propagation delay
time
t PLH
6.0 — — 30 — 37 ns SCLR to Q H ’ 2.0 — — 150 — 190 4.5 — 13 30 — 38
Output enable time
t ZL t ZH 6.0 — — 26 —
33
ns 2.0 — — 150 — 190 4.5 — 15 30 — 38 Output disable time t LZ t HZ 6.0 — — 26 — 33
ns 2.0 100 — — 125 — 4.5 20 1 — 25 — 6.0 17 — — 21 —
ns SER to SCK 2.0 200 — — 250 — 4.5 40 8 — 50
—
Setup time
t su
6.0 34 — — 43 —
ns SCK to RCK 2.0 80 — — 100 — 4.5 16 8 — 20 — Pulse width t w
6.0 14 — — 17
— ns 2.0 100 — — 125 — 4.5 20 — — 25 — Removal time t rem
6.0 17 — — 21 —
ns 2.0 5 — — 5 — 4.5 5 1 — 5 — Hold time t h
6.0 5 — — 5
—
ns 2.0 — — 75 — 95 4.5 — 5 15 — 19
6.0 — — 13 — 16
ns Q H ’ 2.0 — — 60 — 75 4.5 — 4 12 — 15 Output rise/fall
time t TLH t THL 6.0 — — 10 —
13 ns Q Input capacitance
Cin — — 5 10 —
5
pF
Test Circuit
Waveforms
Package Dimensions
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