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A photonic front-end processor in a WDM ATM multicast switch

A photonic front-end processor in a WDM ATM multicast switch
A photonic front-end processor in a WDM ATM multicast switch

JOURNAL OF LIGHTW A VE TECHNOLOGY ,VOL.18,NO.3,MARCH 2000

273

A Photonic Front-End Processor in a WDM ATM

Multicast Switch

H.J.Chao ,Senior Member,IEEE ,L.Wu ,Member,IEEE ,Z.Zhang,S.H.Yang,L.M.Wang,Y .Chai,J.Y .Fan,

and F.S.Choa

Abstract—Dense wavelength-division multiplexing (DWDM)technology has provided tremendous transmission capacity in optical fiber communications.However,switching and routing capacity is still far behind transmission capacity.This is because most of today's packet switches and routers are implemented using electronic technologies.Optical packet switches are the potential candidate to boost switching capacity to be comparable with transmission capacity.In this paper,we present a photonic asynchronous transfer mode (ATM)front-end processor that has been implemented and is to be used in an optically transparent WDM ATM Multicast (3M)switch.We have successfully demon-strate the front-end processor in two different experiments.One performs cell delineation based on ITU standards and overwrites VCI/VPI optically at 2.5Gb/s.The other performs cell synchro-nization,where cells from different input ports running at 2.5Gb/s are phase-aligned in the optical domain before they are routed in the switch fabric.The resolution of alignment is achieved to the extent of 100ps (or 1/4bit).An integrated 1

neering,U Publish

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Fig.1.Architecture of the WDM ATM multicast (3M)

Switch.

Fig.2.Cell format adopted in the system.

also been proposed to identify packet boundaries for IP over WDM [9].Once cell boundaries are identified,the VPI/VCI and header error control (HEC)fields are replaced optically with the new values by the VCI-overwrite unit.These two units have been implemented and demonstrated at the data rate of 2.5Gb/s.

The cell synchronization unit is used to align the phases of in-coming ATM cells in the optical domain.The synchronization issue is also addressed in [19].Zucchelli and Burzio have imple-mented a two-stage cell synchronizer [10],[11],coarse and fine synchronizer,at the rate of 622Mb/s.The former uses a few

slow

thermooptic

switches to control the cells through different fiber delay lines.The latter uses a tunable wavelength converter to convert the wavelength of the cells to finely adjust the delay along a highly dispersive fiber.In our design,we adjust the phases of optical cells at 2.5Gb/s to a reference cell clock with the adjustment range from 1to 511bits and with a precision of 1/4bit (or 100ps).We have adopted a novel sampling method to achieve 100-ps precision without using a 10-GHz clock.In this paper,Section II presents an overview of the enhanced 3M switch and the optical random access memory.Section III describes the architecture of the photonic ATM front-end pro-cessor.Section IV shows the implementation and testing results.Section V presents the conclusions.

II.A N O VERVIEW OF THE 3M S WITCH

Fig.1shows the architecture of an

enhanced 3M switch,where incoming cells running at 2.5Gb/s are optically split into two paths.Cells on the top path remain in the op-tical domain and are routed through the optical switch

plane.

Fig.3.An optical random access memory.

Cells on the bottom path are converted to the electronic domain,where their headers are extracted for processing (e.g.,finding the output ports for which the cells are destined and finding new VPI/VCI values to replace the old VPI/VCI values).An electronic central controller,as shown in Fig.1,performs cell delineation,VCI-overwrite,cell synchronization,and routing.The first three functions are implemented in the photonic ATM front-end processor,while the last one is handled by a route con-troller that routes cells to proper output ports.

As shown in Fig.2,the cell format adopted in our system has 64bytes with 5bytes of header,48bytes of payload,and 2guard time fields (with all ones),which are 6and 5bytes

CHAO et al.:A PHOTONIC FRONT-END PROCESSOR IN A WDM ATM MULTICAST SWITCH275

Fig.4.An optical shared memory controlled by a route controller.

long,respectively.The guard times are used to accommodate

the slow switching of optical devices,such as optical tunable

filters.The lengths of the guard times between the cells,and

between the cell header and the payload were arbitrarily chosen

to demonstrate the feasibility of the technology.

The incoming optical cells are first delayed by fiber lines,

processed for their headers,and synchronized in the front-end

processor before they are sent to the switch fabric.In the

switch fabric,cells are converted to different wavelengths by

wavelength converters(WC’s)that are controlled by the route

controller,which keeps track of the available wavelengths in

the WDM optical shared memory.It is a fiber loop memory,

as shown in Fig.3,and is used to store optical cells until they

are ready to be transmitted to the next https://www.doczj.com/doc/a316049275.html,ing a3-dB

directional coupler,cells are coupled into the optical memory

and coexist with the existing cells.Accessing cells in the

optical memory is done by controlling the space switches

(SW’s),e.g.,semiconductor optical amplifier(SOA)gate.The

maximum number of cells(i.e.,wavelengths)simultaneously

stored in this memory is

output ports by a splitter and selected by the

destined output port(or ports,if multicast)through tunable

filters that are tuned by the route controller at a per-cell basis.

The final wavelength converter stage converts cells to their

predetermined wavelengths.Other optical loop memory can be

found in[20]–[22].

Fig.4shows how the shared memory is controlled by a

route controller.

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Fig.6.Block diagram of the cell delineation

unit.

Fig.7.Block diagram of the VCI-overwrite unit.

The write controller and read controller generate proper signals to coordinate all functional blocks.

The jitter from the high-speed control circuits (2.5GHz)has been minimized by taking some careful steps,such as opti-mizing circuits design at 2.5GHz,using high-speed ECL and GaAs chips,Getek PCB material.

III.T HE A RCHITECTURE OF THE P HOTONIC ATM F RONT -E ND

P ROCESSOR The header of an ATM cell carries all necessary routing in-formation.The photonic ATM front-end processor is designed to extract cell headers and perform cell delineation,VCI-over-

CHAO et al.:A PHOTONIC FRONT-END PROCESSOR IN A WDM ATM MULTICAST SWITCH

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Fig.8.Block diagram of the cell synchronization unit.

write,and cell synchronization.The front-end processor pre-sented in the paper is used for an OC-48line.The optical devices in the system need to have flat gain over wide bandwidth to ac-commodate WDM applications.The gain of the optical switches used in the system is kept just enough to overcome the insertion loss while input power is sufficiently high to suppress the ASE noise.

A.Cell Delineation Unit

As shown in Fig.1,an optical cell stream is tapped from each input line,converted to electronic format,and sent to the cell delineation unit.Cell delineation is a process used to identify cell boundaries so that the incoming cell stream can be further processed at the cell level by the following units,such as VCI-overwrite.

We adopted the standardized HEC checking mechanism to find cell boundaries.It takes advantage of the inherent Cyclic Redundancy Check(CRC)coding correlation between the cell header to be protected(the first4bytes)and HEC byte(the fifth byte of the cell header).Fig.5shows the state diagram of cell delineation.Initially,a cell boundary is arbitrarily assumed and checked by performing a polynomial division bit-by-bit in the HUNT state(Fig.5).If the remainder(i.e.,syndrome)for a com-plete calculation is zero,then this boundary is assumed to be correct.Otherwise,shift a bit from the data stream and repeat the operation until the syndrome is zero.Once a cell boundary is determined,it has to be confirmed cell-by-cell for eight con-secutive times in the PRESYNC state before the cell boundary is claimed to be found.It then goes to the SYNC state.Once in the SYNC state,the cell boundary is claimed to be lost when seven consecutive mismatches occur.As a result,the above procedure for cell delineation will start over again(from the HUNT

state).Fig.9.Block diagram of the timing signal generator.

As shown in Fig.6,to reduce the high-speed circuit require-ment,the serial bit stream at2.5Gb/s is first converted to16-bit parallel words(155Mb/s)through a serial to parallel converter. A16-bit parallel format of the CRC circuit is used to perform polynomial division and the syndrome is checked every three word clock cycles.An HPS(HUNT,PRESYNC,and SYNC)fi-nite state machine performs the state transition between HUNT, PRESYNC,and SYNC states in Fig.5.If a syndrome equals zero,then the finite state machine goes to the PRESYNC state from the HUNT state and disables a set of control and shift cir-cuits by a signal Y.Otherwise,the finite state machine informs the control and shift circuits to inhibit a bit or a byte every three cell clock cycles.Once the cell boundary is confirmed,the state machine goes to the SYNC state and sends a signal X to create a cell clock,which indicates the location of the cell boundary.The cell clock and signal X are passed to the VCI-overwrite unit to-gether with the old VPI/VCI and the word clock.In our design, the cell boundary can be identified within72cell time slots from a random bit stream.

Identifying cell boundaries for a back-to-back cell stream at 2.5Gb/s without using SONET frames is much more difficult than the case where cells are carried over SONET frames.In our design,when an error HEC is detected in the HUNT state,

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Fig.10.Sample timing of the fine adjustment circuit (1=4

bit).

Fig.11.Fine delay comparator.

the system clock (2.5GHz)is shifted by one bit to restart the HEC hunting process as opposed to shifting one byte in the case where cells are carried over SONET frames.This is achieved by masking a clock pulse at 2.5GHz (or 200ps),which is very challenging.

B.VCI-Overwrite Unit

Once cell boundaries are recognized and confirmed by the cell delineation unit,the state machine moves to the SYNC state

and enables the VCI-overwrite unit with the cell clock and signal X,as shown in Fig.7.The main function of this unit is to over-write the VPI/VCI field of the incoming cell header in the op-tical domain.The VCI-overwrite unit performs table lookups in the electronic domain,converts the new VPI/VCI to an op-tical signal,and replaces the old VPI/VCI by using

a op-tical switch.The routing table (i.e.,VCI/VPI translation table)is pre-programmed manually for permanent virtual connections (PVC’s)and not by UNI and PNNI signaling protocols that are used for switched virtual connections (SVC’s).The challenge is how to handle the high-speed overwriting at the bit rate of 2.5Gb/s with each bit only 400ps.We resolve it by (a)replacing the whole cell header instead of just the VPI/VCI fields,and (b)using electronic variable delay lines (programmable delay)to compensate for the time difference between the old header and the new header.

As shown in Fig.7,the new header obtained from the table lookup is converted to a serial format by a parallel to serial con-verter.It is then used to control a laser driver to drive a DFB laser diode that generates the cell header in the optical domain.

The new header replaces the old one using

a

optical switch that is controlled by a 6-byte wide pulse in every cell time slot.

CHAO et al.:A PHOTONIC FRONT-END PROCESSOR IN A WDM ATM MULTICAST SWITCH 279

TABLE I

C ONVERSION T ABLE B ETWEEN [D0,D1,

D2,D3]AND [C10,

C11]

Fig.12.The PCB’s of the cell delineation and VCI-overwrite

units.

Fig.13.A portion of the PCB of the cell synchronization unit.

TABLE II

S UMMARY OF THE P RINTED C IRCUIT B

OARDS

The successfully overwritten cells are sent to fiber delay lines in the cell synchronization unit.

The switching speed of

the optical switch is 1GHz,which is sufficiently fast for our application.The time delay of the VCI-overwrite Unit is mainly caused by the VPI/VCI table lookup and is negligible as compared to the propagation delay between switch nodes.C.Cell Synchronization Unit

In the 3M switch,synchronization is done at two levels.The cell contention resolution,VCI/VPI overwrite and cell read/write from/to the loop memory are executed at the cell level while the interaction between electronic and optical signals is at the bit level.For instance,cell header overwrite optically is done at the bit level.Furthermore,synchronization among the incoming optical cells is achieved at 1/4bit.

The cell synchronization unit in Fig.8is used to optically align cells from different inputs to the extent

of

(where

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Fig.14.A fabricated122SOA gates switch.

Fig.15.Switching characteristics of an SOA switch(200ps/div.).

Fig.16.Testing setup of the cell delineation and the VCI-overwrite units.

100ps,the phase adjustment error is limited to100ps.Table I

shows the mapping of the fine sampled value(D0–D3)to the

last two bits of the delay line control(C10,C11).

With different combinations of C1to C11,the optical delay

elements are tuned to insert the desired delay needed to align the

phase of incoming cells.For example,with[C1,C2,

[1,0,1,0,0,0,0,0,0,0,1],a total delay of

(the last term is

CHAO et al.:A PHOTONIC FRONT-END PROCESSOR IN A WDM ATM MULTICAST SWITCH 281

bit stream to 16-bit parallel words at 155Mb/s,reducing the number of high-speed components and implementation costs.A number of EPROM chips are used for VCI translation in the VCI-overwrite PCB.A 16-bit multiplexer performs parallel-to-serial conversion for the cell headers and overwrites the old VCI optically.In the cell synchronization PCB,several programmable delay chips are used to adjust the phase of some signals in the coarse and fine adjustment circuits.The delay adjustment range varies from 1390to 3630ps with approximate 20-ps delay step resolution.

Fig.12is a photograph of the cell delineation and VCI-over-write PCB’s.Fig.13shows a portion of the cell synchroniza-tion PCB.Table II summarizes the characteristics of these three PCB’s.

B.

SOA Switches

We have developed the

integrated

Y-junction SOA switches that are used in optical delay elements of the cell syn-chronization unit and the WDM optical shared memory.

Fig.14shows our

integrated

Y-junction SOA photonic switch that

is

mm.It can be fabricated on an InP sub-strate by wet etching and regrowth processing.The Y-junction passive waveguide,with a stripe width of

3.75

m.The

total length of the passive waveguide is

1200

m.They are made of InGaAs–InGaAsP

multiple quantum well around 1550nm.After the antireflec-tion coating,the ripple in the spontaneous emission spectrum is smaller than 0.2dB at the working bias current.

Fig.15shows the switching characteristics of the fabricated SOA switches.An optical “dc”signal is switched on and off by the SOA gates controlled by external electrical signals.Both the rising and falling times are around 600ps,which is par-tially limited by the driving electronics.Further improvement of the speed by reducing the area of the electrical contact 5to 10times is possible.However,since guard times between cells are employed,the subnanosecond switching speed of the de-vice is good enough for our applications.By using the fabri-

cated

SOA switch,we have demonstrated the data-block switching operation.

C.Testing of the Cell Delineation and VCI-Overwrite Units Testing is divided into two parts,one demonstrating cell de-lineation and VCI-overwrite,and the other demonstrating cell synchronization.

We integrate two PCB’s (cell delineation and VCI-overwrite units)with the necessary optical devices as shown in Fig.16.A data generator generates the 2.5-GHz Bit_clk and a series of 2.5-Gb/s back-to-back cells.To simplify the test,the gener-ated cells with the format shown in Fig.2have a random pay-load but an identical cell header pattern,which is {00001010,11001100,11101110,11110000,10100000}.We assume that only the third byte (representing VCI)and the fifth byte (HEC byte)are updated in the VCI-overwrite

unit.

Fig.17.Testing result of the cell delineation and VCI-overwrite units (3.6

ns/div).

Fig.18.Coarse delays adjustment.

Since inputs and outputs of two PCB’s have standard ECL

voltage levels,

with

V ,which is different from that of the laser driver

(

V),an amplifier is needed.

The optical switch is accomplished by two modulators and drivers that are controlled by the VCI-overwrite unit.A high-speed os-cilloscope is used to examine the overwritten cell stream,which is converted from optical format to electronic format by an O/E converter.

When the system is powered on,the data generator provides a cell stream and a Bit_clk to the system.Depending on the position of the first cell boundary selected by the cell delineation unit,the correct updated cells can be obtained and monitored in the oscilloscope.

Fig.17shows the testing results of the cell delineation and VCI-overwrite units.The new header becomes {00001010,11001100,00010001,11110000,01110111},which meets our expectation.

D.Testing of the Cell Synchronization Unit

The cell synchronizer PCB controls the 11stages of optical delay elements through C1to C11signals that turn on or off

the

Y-junction SOA switches.The fiber delay length varies

from

to is the number of delay stages.Fig.18illustrates

the

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Fig.19.Testing setup of the cell synchronization unit.

Fig.20.Fine delay adjustments(200ps/div).

The testing setup shown in Fig.19generates three cell

streams at2.5Gb/s through Routes1,2,and3.To simplify

the testing,instead of using the Cell_clk derived from the cell

delineation unit,we use the Cell_clk from the data generator

with a frequency of of the bit clock(2.5GHz).Since the

most challenging part of the experiment is to adjust the phase

of the incoming cells to the neighborhood of one bit,we only

control the last three stages of the delay elements,while the

first eight stages are replaced by a fiber line(Delay2)with a

delay of510bits.In our setup,we let the Ref_clk synchronize

with the Cell_clk.By varying the length of fiber delay line

(Delay1),the phase of the cell stream is set to

1010(64bytes),has

been shown to delay by511

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Fig.22.X-axis:time,2ns/div;Y-axis:relevant voltage.A partial PRBS pattern of a cell operating at 2.5Gb/s and circulating up to 23loops with the wavelength of 1556.5

nm.

Fig.23.X-axis:wavelength;Y-axis:relevant power.The optical spectrum of the two WDM cells operating at 2.5Gb/s.

and the number of circulations of the ATM cell in the loop memory.

The testing setup is shown in Fig.21.Four bit streams are generated from the Pattern Generator and carried by four different wavelengths.At the rate of 2.5Gb/s,each consists of a 64-byte cell followed by a string of zero bits.The cell is generated according to pseudorandom binary sequence (PRBS)and its duration (t2)is 205ns.These four wave-lengths are multiplexed by a 4-to-1multiplexer.Through a coupler,50%of the power is fed to the loop memory and the other 50%is used for monitoring.The waveguide grating router (WGR)splits the multiplexed wavelengths into four separate paths,each passing a polarization controller (PC),optical switch (SW),and attenuator.The erbium-doped fiber amplifier (EDFA)is used to compensate for the power loss due to multiple circulations in the loop memory.The four optical switches are controlled by the FPGA chip with S1–S4signals according to the operation modes,e.g.,writing cells

into the loop memory,reading cells from the loop memory,and circulating cells in the loop memory.Fig.21(b)shows one of the input bit streams,D1.Two cells carried

by

generated from the Pattern Generator.CLOCK is an external clock signal to the FPGA controller,which is independent from

the bit streams

.The duration of the S1signal (t4and t5)corresponds to the write and read cycles,respectively,as does t6and t7in the S2signal.The duration can be adjusted flexibly by the FPGA chip and the adjustment precision is 9ns.The guard time,t3,is 13%–20%of t2.

Fig.22shows a partial PRBS pattern of a cell operating at 2.5Gb/s and circulating up to 23loops with the wavelength of 1556.5nm.Fig.23shows the optical spectrum of two WDM cells operating at 2.5Gb/s,and their corresponding wavelengths

(

Y-junction

SOA switch has been developed and used as the space switch in the cell synchronizer and the WDM loop memory.

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The WDM loop memory has been demonstrated to be able to store two WDM cells and circulate them up to23turns at2.5 Gb/s.A dynamic refresh controller for multiple WDM channels in the loop memory is being designed with FPGA chips.

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H.J.Chao(S’82–M’85–SM’95)received the

B.S.E.E.and M.S.E.E.degrees from the National

Chiao-Tung University,Taiwan,R.O.C.,in1977

and1980,respectively.He received the Ph.D.

degree in electrical engineering from The Ohio State

University,Columbus,in1985.

He is Professor of the Department of Electrical

Engineering at Polytechnic University,Brooklyn,

NY,which he joined in January1992.His research

interests include terabit IP routers,optical packet

switches,and quality of service control in IP/ATM networks.From1985to1991,he was a Member of Technical Staff at Bellcore, NJ,where he conducted research in the area of SONET/ATM broad-band networks.He was involved in architecture designs and ASIC implementations, such as the first SONET-like Framer chip,ATM Layer chip,and Sequencer chip(the first chip handling packet scheduling).

Dr.Chao received the Bellcore Excellence Award in1987.He served as Guest Editor for the IEEE J OURNAL ON S ELECTED A REAS IN C OMMUNICATIONS (JSAC)with special topics on“Advances in ATM Switching Systems for B-ISDN”(June1997)and“Next Generation IP Switches and Routers”(June 1999).He is currently serving as an Editor for the IEEE/ACM T RANSACTIONS ON N ETWORKING

.

L.Wu(M’97)received the B.S.,M.S.,and Ph.D.de-

grees in electronic engineering from Tsinghua Uni-

versity,Beijing,China,in1988,1991,and1997,re-

spectively.

He was a Senior Lecturer in the Department

of Electronic Engineering,Tsinghua University

from1994to early1997.After his research and

development work on multimedia DSP chips in

1997,he joined the Center for Advanced Technology

in Telecommunications,the Department of Electrical

Engineering,Polytechnic University,Brooklyn,NY, as a Postdoctoral Fellow,working on design and implementation of high-speed digital control circuits and systems utilized in WDM ATM Multicast optical switching systems.He is also working on ASIC design of the ATM switch chips.His current interest is on high-speed digital circuits and systems utilized in optical fiber communications and ASIC design of ATM switch chips and DSP chips.

Dr.Wu received the Tsinghua University Excellence Graduate Award and Medal in

1988.

Z.Zhang was born in Liaoning,China,in1967.He

received the B.Sc.degree in electronic engineering

and the Ph.D.degree in opto-electronics from

Tsinghua University,China,in1989and1996,

respectively.

During1996,he was with the Department of

Electronic Engineering at Tsinghua University,

working on optical time-division and wavelength-di-

vision multiplexed ATM switching system.From

late1996to1998,he was a postdoctoral Fellow

with the Department of Electrical Engineering at the Polytechnic University,Brooklyn,NY,working on photonic ATM front-end processor and3M(WDM,A TM,Multicast)optical switching system.Since early1999,he has been a Hardware Design Engineer at Fujitsu Network Communications,Inc.,Pearl River,NY,working on ATM switching systems. His research interests are in ATM network,photonic packet switching and optical WDM

network.

S.H.Yang received the B.S.degree in physics from

Soochow University,Taiwan,R.O.C.,in1987,the

M.S.degree in electro/optical engineering from the

National Chiao-Tung University,Taiwan,in1989,

and the Ph.D.degree in electrical engineering from

Polytechnic University,Brooklyn,NY,in1999.

In1999,he joined the Transcomm Technology

System,Inc.,Fremont,CA,where he works in the

area of access networks.His research interests are

in the area of ATM switches,IP routers,and access

network systems.

CHAO et al.:A PHOTONIC FRONT-END PROCESSOR IN A WDM ATM MULTICAST SWITCH 285

L.M.Wang received the B.S.degree in physics and the M.S.degree in Optics from the University of Electronic Science and Technology of China,Chengdu,Sichuan,China,in 1985and 1991,respectively.He received a second M.S.de-gree in physics from Indiana University–Purdue University at Indianapolis,IN,in 1996.He received the Ph.D.degree in electrical engineering from the Uni-versity of Maryland Baltimore County (UMBC),Baltimore,MD,in May 1999.From July 1996to May 1999,he worked on the opto-electronic devices and their applications in optical access networks and all-optical packet switches.He joined Corning,Inc.,Corning,NY ,in May 1999,as Senior Scientist in fiber communications.His current interests are dispersion-managed fibers and soliton

transmissions.Y.Chai received the B.S.,M.S.,and Ph.D.degrees in electrical engineering from Tsinghua University,Beijing,China,in 1986,1988,and 1992,respectively.He was a Lecturer and an Associate Professor in the Department of Electronic Engineering,Tsinghua University,Beijing,China,from 1992to 1996.He joined the faculty of the Department of Computer Science and Electrical Engineering,University of Maryland Baltimore County (UMBC),Baltimore,MD,as a Research Associate from 1996to 1999.He is now with Tyco Submarine

Systems,Ltd.,Eatontown,NJ.He worked on tunable semiconductor lasers,laser frequency stabilization,optical FDM transmission,high-speed WDM transmission system,and optical packet switching networks.He has more than 60publications and presentations,and holds two patents.His current interest is on undersea optical WDM transmission systems and gain-flattened broad-band

EDFA.

J.Y.Fan received the B.S.degree in physics from the National Tsinghua University,Taiwan,R.O.C.,in 1988,the M.S.degree in electro-optical engineering from the National Chiao-Tung University,Taiwan,in 1990and the Ph.D.degree in electrical engineering from the University of Maryland Baltimore County (UMBC),Baltimore,MD,in 1999.His Ph.D.work concentrated on the design,fabrication,and implementation of high-speed photonic switching in a photonic IP/ATM system and demultiplexing/mul-tiplexing for TDM system,and wavelength converts

for WDM system.

He is now with Nanovation Technologies,Inc.,Evanston,IL,where he is doing research work in thin-film photonic devices for optical communications.

F.S.Choa received the B.S.degree from the National Taiwan University,Taiwan,R.O.C.,and the M.S.and Ph.D.degrees from the State University of New York (SUNY)at Buffalo,NY .

After his Ph.D.research work on femtosecond infrared lasers and detectors in 1988,he joined AT&T Bell Laboratories,in Holmdel and Murray Hill,NJ,where he worked in the area of photonic integrated circuits and chemical beam epitaxy.Since joining the University of Maryland Baltimore County (UMBC),Baltimore,MD,he has been working in the areas of III–V compound semi-conductor material growth and processing,RF-photonic devices and systems,photonic IP/ATM switching,ultrahigh capacity WDM communications and net-works,and fiber-optic sensors for biomedical sensing.He has authored and coauthored more than 130refereed journal and conference publications.

Dr.Choa is a Topical Editor for Optics Letters and Associate Editor of the Journal of High-Speed Networks .

高中英语每日一题第3周playapartin含解析新人教版必修120171011143

play a part (in) 重要程度:★☆☆☆☆难易程度:★★☆☆☆ Have you realized the part computers have ___________ in the daily life? A. made B. given C. caused D. played 【参考答案】D 【拓展延伸】 1. play a part (in) 在……中扮演一个角色;参与;在……中起作用 2. play the role of 扮演……的角色 play an important role / part in...在……中起重要作用 play the leading role / part主演;起带头作用 3. take part in 参加 for the most part多半;在很大程度上 for one’s part就某人而言,对某人来说 1. Colors play an important ___________ in the way you look. A. part B. form C. effect D. pride 2. Mr. Huang will ___________ in the movement. A. play a leading part B. take parts C. play leading part D. take a part 3. __________ part that women ___________ in society is great. A. The; plays B. A; takes C. A; plays

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aesb.dosth.helpsb.ithsth.帮助某人做某事 trytodosth.尽力做某事 It’s+ad+forsb.todosth.对某人来说,做某事……的。 语法讲解 Boosillonlybeonputers,notonpaper.书将只在电脑里,而不是在纸上。 Thereillbeorepollution.将会有更多的污染。 ).Thereillbe+n=Thereis/aregoingtobe+n将会有…ThereisgoingtobeafootballatchthisFriday. ).pollution:污染;公害pollute:污染;弄脏polluted:受污染的 Everyoneshouldplayapartinsavingtheearth.每个人应该参与挽救地球。 Todaytherearealreadyrobotsoringinfactories.现在已经有机器人在工厂里工作了。 Therebesb.doingsth.有某人正在做…Thereisabirdsinginginthetree. Theyagreeitaytaehundredsofyears.他们同意这可能花费几百年的时间。 Ittaes+时间+todosth.某人花费时间区做某事。 Ittooehalfanhourtofinishyhoeor. agreetodosth.eagreetoeetuplaterandtalthingsover

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