General Description
The MAX5590–MAX5595 octal, 12/10/8-bit, voltage-out-put digital-to-analog converters (DACs) offer buffered outputs and a 3μs maximum settling time at the 12-bit level. The DACs operate from a +2.7V to +5.25V analog supply and a separate +1.8V to +5.25V digital supply.The 20MHz 3-wire serial interface is compatible with SPI?, QSPI?, MICROWIRE?, and digital signal processor (DSP) protocol applications. Multiple devices can share a common serial interface in direct-access or daisy-chained configuration. The MAX5590–MAX5595provide two multifunction, user-programmable, digital I/O ports. The externally selectable power-up states of the DAC outputs are either zero scale, midscale, or full scale. Software-selectable FAST and SLOW settling modes decrease settling time in FAST mode, or reduce supply current in SLOW mode.
The MAX5590/MAX5591 are 12-bit DACs, the MAX5592/MAX5593 are 10-bit DACs, and the MAX5594/MAX5595 are 8-bit DACs. The MAX5590/MAX5592/MAX5594 provide unity-gain-configured output buffers,while the MAX5591/MAX5593/MAX5595 provide force-sense-configured output buffers. The MAX5590–MAX5595 are specified over the extended -40°C to +85°C temperature range, and are available in space-saving 24-pin and 28-pin TSSOP packages.
Applications
Portable Instrumentation
Automatic Test Equipment (ATE)Digital Offset and Gain Adjustment Automatic Tuning
Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Controls
Motion Control
Microprocessor (μP)-Controlled Systems Power Amplifier Control
Fast Parallel-DAC to Serial-DAC Upgrades
Features
?Octal, 12/10/8-Bit Serial DACs in TSSOP Packages ? 3μs (max) 12-Bit Settling Time to 1/2 LSB
?Integral Nonlinearity:
1 LSB (max) MAX5590/MAX5591 A-Grade (12-Bit)1 LSB (max) MAX5592/MAX5593 (10-Bit)1/
2 LSB (max) MAX5594/MAX5595 (8-Bit)?Guaranteed Monotonic, ±1 LSB (max) DNL ?Two User-Programmable Digital I/O Ports ?Single +2.7V to +5.25V Analog Supply ?+1.8V to AV DD Digital Supply
?20MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-/DSP-Compatible Serial Interface ?Glitch-Free Outputs Power Up to Zero Scale,Midscale, or Full Scale Controlled by PU Pin ?Unity-Gain or Force-Sense-Configured Output Buffers
MAX5590–MAX5595
Voltage-Output DACs
________________________________________________________________Maxim Integrated Products
1
Ordering Information
For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at https://www.doczj.com/doc/9b6646645.html,.
*Future product—contact factory for availability. Specifications are preliminary.
Selector Guide and Pin Configurations appear at end of data sheet.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
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M A X 5590–M A X 5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,Voltage-Output DACs 2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AV DD = 2.7V to 5.25V, DV DD = 1.8V to AV DD , AGND = 0, DGND = 0, V REF = 2.5V (for AV DD = 2.7V to 5.25V), V REF = 4.096V (for
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AV DD to DV DD ........................................................................±6V AGND to DGND..................................................................±0.3V AV DD to AGND, DGND.............................................-0.3V to +6V DV DD to AGND, DGND............................................-0.3V to +6V FB_, OUT_,
REF to AGND........-0.3V to the lower of (AV DD + 0.3V) or +6V SCLK, DIN, CS , PU,
DSP to DGND.......-0.3V to the lower of (DV DD + 0.3V) or +6V UPIO1, UPIO2
to DGND...............-0.3V to the lower of (DV DD + 0.3V) or +6V
Maximum Current into Any Pin.........................................±50mA Continuous Power Dissipation (T A = +70°C)
24-Pin TSSOP (derate 12.2mW/°C above +70°C).......976mW 28-Pin TSSOP (derate 12.8mW/°C above +70°C).....1026mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range.............................-65°C to +150°C Maximum Junction Temperature.....................................+150°C Lead Temperature (soldering, 10s).................................+300°C
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MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________3
ELECTRICAL CHARACTERISTICS (continued)
(AV DD = 2.7V to 5.25V, DV DD = 1.8V to AV DD , AGND = 0, DGND = 0, V REF = 2.5V (for AV DD = 2.7V to 5.25V), V REF = 4.096V (for
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M A X 5590–M A X 5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,Voltage-Output DACs 4_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV DD = 2.7V to 5.25V, DV DD = 1.8V to AV DD , AGND = 0, DGND = 0, V REF = 2.5V (for AV DD = 2.7V to 5.25V), V REF = 4.096V (for
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MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________5
ELECTRICAL CHARACTERISTICS (continued)
(AV DD = 2.7V to 5.25V, DV DD = 1.8V to AV DD , AGND = 0, DGND = 0, V REF = 2.5V (for AV DD = 2.7V to 5.25V), V REF = 4.096V (for AV DD = 4.5V to 5.25V), R L = 10k ?, C L = 100pF, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.) (Note 1)
Note 1:For the force-sense versions, FB_ is connected to its respective OUT_. V OUT (max) = V REF / 2, unless otherwise noted.
Note 2:Linearity guaranteed from decimal code 40 to code 4095 for the MAX5590B/MAX5591B (12-bit, B-grade), code 10 to code
1023 for the MAX5592/MAX5593 (10-bit), and code 3 to code 255 for the MAX5594/MAX5595 (8-bit).
Note 3:Represents the functional range. The linearity is guaranteed at V REF = 2.5V (for AV DD from 2.7V to 5.25V), and V REF =
4.096V (for AV DD = 4.5V to
5.25V). See the Typical Operating Characteristics section for linearity at other voltages.
Note 4:DC crosstalk is measured as follows: outputs of DACA–DACH are set to full scale and the output of DACH is measured.
While keeping DACH unchanged, the outputs of DACA–DACG are transitioned to zero scale and the ?V OUT of DACH is measured.
Note 5:Guaranteed by design.
Note 6:The reference -3dB bandwidth is measured with a 0.1V P-P sine wave on V REF and with full-scale input code.
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M A X 5590–M A X 5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,Voltage-Output DACs 6_______________________________________________________________________________________
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1)
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MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________7
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)
(DV DD = 1.8V to 5.25V, GND = 0, T A = T MIN to T MAX , unless otherwise noted.)
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M A X 5590–M A X 5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,Voltage-Output DACs 8_______________________________________________________________________________________
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2)
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MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________9
TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2)
Note 7:In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol-lowing edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns (2.7V) or 50ns (1.8V).
Note 8:The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low
and CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of operation.
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M A X 5590–M A X 5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,Voltage-Output DACs 10______________________________________________________________________________________
-4-2-3
-101
2340
1024
2048
3072
4095
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (12-BIT)
DIGITAL INPUT CODE I N L (L S B )
-1.00
-0.50-0.75
-0.2500.250.500.751.0002565127681023
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (10-BIT)
M A X 5590-95 t o c 02
DIGITAL INPUT CODE I N L (L S B )
-0.50
-0.25
0.250.50
064128192255
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (8-BIT)
M A X 5590-95 t o c 03
DIGITAL INPUT CODE
I N L (L S B )
-0.50
-0.2500.250.500
1024
2048
3072
4095
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (12-BIT)
DIGITAL INPUT CODE D N L (L S B )
-0.2
-0.100.10.20
256
512
768
1023
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (10-BIT)
M A X 5590-95 t o c 05
DIGITAL INPUT CODE
D N L (L S B )
-0.050
-0.025
0.0250.050
64
128
192
255
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (8-BIT)
M A X 5590-95 t o
c 06
DIGITAL INPUT CODE
D N L (L S B )
-4
-2-30-112341.0
2.0
2.5
1.5
3.0 3.5
4.0
4.5
5.0
INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE (12-BIT)
V REF (V)
I N L (L S B )
-0.5
-0.3
-0.4-0.1-0.20.100.20.40.30.5
1.0
20
2.5
1.5
3.0 3.5
4.0
4.5
5.0
DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE (12-BIT)
V REF (V)
D N L (L S B )
-4
0-2
-3-124
31-40
10
-15
35
60
85
INTEGRAL NONLINEARITY vs. TEMPERATURE (12-BIT)
TEMPERATURE (°C)
I N L (L S B )
Typical Operating Characteristics
(AV DD = DV DD = 5V, V REF = 4.096V, R L = 10k ?, C L = 100pF, speed mode = FAST, PU = floating, T A = +25°C, unless otherwise noted.)
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MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________11
-0.2
-0.1
0.10.2-40
10
-15
35
60
85
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE (12-BIT)
TEMPERATURE (°C)
D N L (L S B )
1
23
4501024
2048
3072
4095
SUPPLY CURRENT
vs. DIGITAL INPUT CODE (FORCE-SENSE)
DIGITAL INPUT CODE
S U P P L Y C U R R E N T (m A )
01
2
3
1024
2048
3072
4095
SUPPLY CURRENT
vs. DIGITAL INPUT CODE (UNITY GAIN)
DIGITAL INPUT CODE
S U P P L Y C U R R E N T (m A )
1
2
3
4
2.70
3.40
4.10
4.80
5.25
SUPPLY CURRENT
vs. SUPPLY VOLTAGE (FORCE-SENSE)
SUPPLY VOLTAGE (V)S U P P L Y C U R R E N T (m A )
0.51.01.52.02.53.02.70
3.40
4.10
4.80
5.25
SUPPLY CURRENT
vs. SUPPLY VOLTAGE (UNITY GAIN)
SUPPLY VOLTAGE (V)S U P P L Y C U R R E N T (m A )
2010
3050
40602.70 4.103.40 4.80 5.25
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
S H U T D O W N S U P P L Y C U R R E N T (n A )
0124
5367-40
10
-15
35
60
85
OFFSET ERROR vs. TEMPERATURE
TEMPERATURE (°C)
O F F S E T E R R O R (L S B )
-10-8
-4
-6
-20-40
10
-15
35
60
85
GAIN ERROR vs. TEMPERATURE
TEMPERATURE (°C)
G A I N E R R O R (L S B )
0.5
1.5
1.0
2.02.5
-15
-5
-10
05
10
15
OUTPUT VOLTAGE
vs. OUTPUT SOURCE/SINK CURRENT
I OUT (mA)
O U T P U T V O L T A G E (V )
Typical Operating Characteristics (continued)
(AV DD = DV DD = 5V, V REF = 4.096V, R L = 10k ?, C L = 100pF, speed mode = FAST, PU = floating, T A = +25°C, unless otherwise noted.)
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M A X 5590–M A X 5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,Voltage-Output DACs 12______________________________________________________________________________________
MAJOR-CARRY TRANSITION GLITCH
MAX5590-95 toc19
250ns/div
OUT_2mV/div
CS 5V/div
SETTLING TIME POSITIVE
MAX5590-95 toc20
400ns/div
OUT_2V/div
CS 5V/div
FULL-SCALE TRANSITION
SETTLING TIME NEGATIVE
MAX5590-95 toc21
400ns/div
OUT_2V/div
CS 5V/div
FULL-SCALE TRANSITION
5-25
1
1001000
10
10,000
REFERENCE INPUT BANDWIDTH
FREQUENCY (kHz)
G A I N (d B )
-20-15-10-50REFERENCE FEEDTHROUGH AT 1kHz
M A X 5590-95 t o c 23
FREQUENCY (kHz)
S I G N A L A M P L I T U D E (d B )
5.04.5 3.5 4.01.5 2.0 2.5 3.01.0-130-120-110-100-90-80-70-60-50-40-30-22-142
0.5 5.5
200μs/div
DAC-TO-DAC CROSSTALK
OUTH 1mV/div
OUTA–OUTG 2V/div
MAX5590-95 toc24
Typical Operating Characteristics (continued)
(AV DD = DV DD = 5V, V REF = 4.096V, R L = 10k ?, C L = 100pF, speed mode = FAST, PU = floating, T A = +25°C, unless otherwise noted.)
1μs/div
DIGITAL FEEDTHROUGH
OUT_
(AC-COUPLED)2mV/div
SCLK 2V/div MAX5590-95 toc25
400μs/div
POWER-UP GLITCH
OUT_2V/div
AV DD 2V/div
PU = DV DD
10μs/div
EXITING SHUTDOWN TO MIDSCALE
OUT_2V/div
2V/div
MAX5590-95 toc27
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MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________13
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M A X 5590–M A X 5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,Voltage-Output DACs
Functional Diagrams
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MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
Functional Diagrams (continued)
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M A X 5590–M A X 5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,Voltage-Output DACs 16______________________________________________________________________________________
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MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________
17
Table 1. Serial Write Data Format
Figure 1. Serial-Interface Timing Diagram (DSP Mode Disabled)
Figure 2. Serial-Interface Timing Diagram (DSP Mode Enabled)
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M A X 5590–M A X 5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,Voltage-Output DACs 18
______________________________________________________________________________________
Figure 3. MICROWIRE and SPI Single DAC Writes (CPOL = 0, CPHA = 0 or CPOL = 1, CPHA = 1)
Figure 4. DSP and SPI Single DAC Writes (CPOL = 0, CPHA = 1 or CPOL = 1, CPHA = 0)Serial-Interface Programming Commands
Tables 2a, 2b, and 2c provide all of the serial-interface programming commands for the MAX5590–MAX5595.Table 2a shows the basic DAC programming com-mands, Table 2b gives the advanced-feature program-ming commands, and Table 2c provides the 24-bit read commands. Figures 3 and 4 provide the serial-interface diagrams for read and write operations.
Loading Input and DAC Registers
The MAX5590–MAX5595 contain a 16-bit shift register that is followed by a 12-bit input register and a 12-bit DAC register for each channel (see the Functional Diagrams ). Tables 3, 4, and 5 highlight a few of the commands that handle the loading of the input and DAC registers. See Table 2a for all DAC programming commands.
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MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
19
*F o r t h e M A X 5592/M A X 5593 (10-b i t v e r s i o n ), D 11–D 2 a r e t h e s i g n i f i c a n t b i t s a n d D 1 a n d D 0 a r e s u b -b i t s . F o r t h e M A X 5594/M A X 5595 (8-b i t v e r s i o n ),D 11–D 4 a r e t h e s i g n i f i c a n t b i t s a n d D 3–D 0 a r e s u b -b i t s . S e t a l l s u b -b i t s t o z e r o d u r i n g t h e w r i t e c o m m a n d s .
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M A X 5590–M A X 5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,Voltage-Output DACs
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