Memory
1 Megabit (128K x 8-Bit) EEPROM
28C011T
F EATURES :
?128k x 8-bit EEPROM
?R AD -P AK ? radiation-hardened against natural space radia-tion
?Total dose hardness:
- > 100 krad (Si), depending upon space mission ?Excellent Single Event Effects:- No Latchup > 120 MeV/mg/cm 2 - SEU > 90 MeV/mg/cm 2 read mode ?Package:
- 32-pin R AD -P AK ? flat package - 32-pin Rad-Tolerant flat package - JEDEC-approved byte-wide pinout ?High speed:
- 120, 150, and 200 ns maximum access times available ?High endurance:
- 10,000 erase/write (in Page Mode), - 10 year data retention ?Page write mode:- 1 to 128 bytes
?Low power dissipation
- 20 mW/MHz active (typical)- 110 μW standby (maximum)
D ESCRIPTION :
Maxwell Technologies’ 28C011T high-density 1 Megabit (128K x 8-Bit) EEPROM microcircuit features a greater than 100krad (Si) total dose tolerance, depending upon space mission.The 28C011T is capable of in-system electrical byte and page programmability. It has a 128-byte page programming function to make its erase and write operations faster. It also features data polling and a Ready/Busy signal to indicate the comple-tion of erase and programming operations. In the 28C010T,hardware data protection is provided with the RES pin, in addi-tion to noise protection on the WE signal and write inhibit on power on and off. Software data protection is implemented using the JEDEC optional standard algorithm.
Maxwell Technologies' patented R AD -P AK ? packaging technol-ogy incorporates radiation shielding in the microcircuit pack-age. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, R AD -P AK ? provides greater than 100krad (Si) radiation dose tolerance. This product is available with screening up to Class S.
Logic Diagram
28C011T
Memory
T ABLE 1. 28C011T P INOUT D ESCRIPTION
P IN
S YMBOL D ESCRIPTION 12-5, 27, 26, 23, 25, 4, 28, 3, 31, 2
A0-A16Address 24OE Output Enable 22CE Chip Enable 29WE Write Enable 32V CC Power Supply 16V SS Ground 1RDY/BUSY Ready/Busy 30
RES
Reset
T ABLE 2. 28C011T A BSOLUTE M AXIMUM R ATINGS
P ARAMETER
SYMBOL
MIN
MAX
UNITS
Supply Voltage (Relative to V SS )V CC -0.6+7.0V Input Voltage (Relative to V SS )V IN -0.5 11.V IN min = -3.0V for pulse width < 50ns.
+7.0V
Operating Temperature Range T OPR -55+125°C Storage Temperature Range
T STG
-65
+150
°C
T ABLE 3. D ELTA L IMITS
P ARAMETER V ARIATION I CC 1±10%I CC 2±10%I CC 3A ±10%I CC 3B
±10%
T ABLE 4. 28C011T R ECOMMENDED O PERATING C ONDITIONS
P ARAMETER S YMBOL M IN M AX U NITS Supply Voltage V CC 4.5 5.5V Input Voltage
RES_PIN
V IL -0.311.V IL min = -1.0V for pulse width < 50 ns
0.8V
V IH
2.2V CC +0.3V H V CC -0.5V CC +1Operating Temperature Range T OPR
-55
+125
°C
Memory
T ABLE 5. 28C011T C APACITANCE
(T A = 25 °C, f = 1 MHZ)
P ARAMETER
S YMBOL M IN M AX U NITS Input Capacitance: V IN = 0V 1C IN --6pF Output Capacitance: V OUT = 0V 1C OUT
--
12
pF
1.Guaranteed by design.
T ABLE 6. 28C011T DC E LECTRICAL C HARACTERISTICS
(V CC = 5V ± 10%, T A = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED )
P ARAMETER
T EST C ONDITION
S UBGROUPS S YMBOL M IN M AX U NITS Input Leakage Current V CC = 5.5V, V IN = 5.5V 1, 2, 3I IL -- 2 1μA Output Leakage Current V CC = 5.5V, V OUT = 5.5V/0.4V 1, 2, 3I LO --2μA Standby V CC Current
CE = V CC 1, 2, 3
I CC1--20μA CE = V IH
I CC2--1mA Operating V CC Current
I OUT = 0mA, Duty = 100%, Cycle = 1μs at V CC = 5.5V
1, 2, 3I CC3A --15mA
I OUT = 0mA, Duty = 100%, Cycle = 150ns at V CC = 5.5V
1, 2, 3I CC3B --50Input Voltage
RES_PIN
1, 2, 3V IL --0.8V V IH 2.2--V H V CC -0.5--Output Voltage
I OL = 2.1 mA 1, 2, 3V OL --0.4V I OH = -0.4 mA
V OH
2.4
--1.I LI on RES = 100 uA max.
T ABLE 7. 28C011T AC E LECTRICAL C HARACTERISTICS FOR R EAD O PERATION 1
(V CC = 5V + 10%, T A = -55 TO +125 °C)
P ARAMETER
S YMBOL S UBGROUPS M IN
M AX
U NITS Address Access Time CE = OE = V IL , WE = V IH -120-150-200
t ACC
9, 10, 11
------120150200
ns
Chip Enable Access Time OE = V IL , WE = V IH -120-150-200
t CE
9, 10, 11
------120150200ns
Memory
Output Enable Access Time CE = V IL , WE = V IH -120-150-200
t OE
9, 10, 11
000
7575100
ns
Output Hold to Address Change CE = OE = V IL , WE = V IH -120-150-200
t OH
9, 10, 11
000
------ns
Output Disable to High-Z 2CE = V IL , WE = V IH -120-150-200
CE = OE = V IL , WE = V IH -120-150-200
t DF
t DFR
9, 10, 11
000000
505060
300350450
ns
RES to Output Delay 3CE = OE = V IL , WE = V IH -120-150-200
t RR
9, 10, 11
------400450650
ns
1.Test conditions: Input pulse levels - 0.4V to
2.4V; input rise and fall times < 20ns; output load - 1 TTL gate + 100pF (including scope and jig); reference levels for measuring timing - 0.8V/1.8V.2.t DF and t DFR are defined as the time at which the output becomes an open circuit and data is no longer driven.
3.Guaranteed by design.
T ABLE 8. 28C011T AC E LECTRICAL C HARACTERISTICS FOR P AGE /B YTE E RASE AND B YTE W RITE
O PERATIONS
(V CC = 5V + 10%, T A = -55 TO +125 °C)
P ARAMETER
S YMBOL S UBGROUPS M IN 1
M AX
U NITS Address Setup Time -120-150-200
t AS
9, 10, 11
000
------ns
Chip Enable to Write Setup Time (WE controlled)-120-150-200
t CS
9, 10, 11
000
------ns
T ABLE 7. 28C011T AC E LECTRICAL C HARACTERISTICS FOR R EAD O PERATION 1
(V CC = 5V + 10%, T A = -55 TO +125 °C)
P ARAMETER
S YMBOL S UBGROUPS M IN
M AX
U NITS
Memory
Write Pulse Width CE controlled -120-150-200
WE controlled -120-150-200
t CW
t WP
9, 10, 11
200250350200250350
------------ns
Address Hold Time -120-150-200t AH
9, 10, 11
150150200
------ns
Data Setup Time -120-150-200t DS
9, 10, 11
75100150
------ns
Data Hold Time -120-150-200
t DH
9, 10, 11
101010
------ns
Chip Enable Hold Time (WE controlled)-120-150-2000
t CH
9, 10, 11
000
------ns
Write Enable to Write Setup Time (CE controlled)-120-150-200
t WS
9, 10, 11
000
------ns
Write Enable Hold Time (CE controlled)-120-150-200
t WH
9, 10, 11
000
------ns
Output Enable to Write Setup Time -120-150-200
t OES
9, 10, 11
000
------ns
Output Enable Hold Time -120-150-200
t OEH
9, 10, 11
000
------ns
O PERATIONS
(V CC = 5V + 10%, T A = -55 TO +125 °C)
P ARAMETER S YMBOL S UBGROUPS M IN 1
M AX
U NITS
Memory
Write Cycle Time 2-120-150-200t WC
9, 10, 11
------101010
ms
Data Latch Time -120-150-200
t DL
9, 10, 11
250300400
------ns
Byte Load Window -120-150-200t BL
9, 10, 11
100100200
------μs
Byte Load Cycle -120-150-200
t BLC
9, 10, 11
0.550.550.95
303030
μs
Time to Device Busy -120-150-200t DB
9, 10, 11
100120170
------ns
Write Start Time 3-120-150-200
t DW
9, 10, 11
150150250
------ns
RES to Write Setup Time -120-150-200
t RP
9, 10, 11
100100200
------μs
V CC to RES Setup Time 4-120-150-200
t RES
9, 10, 11
113
------μs
https://www.doczj.com/doc/9f6203829.html,e this device in a longer cycle than this value.
2.t WC must be longer than this value unless polling techniques or RDY/BUSY are used. This device automatically completes the internal write operation within this value.
3.Next read or write operation can be initiated after t DW if polling techniques or RDY/BUSY are used.
4.Gauranteed by design.
O PERATIONS
(V CC = 5V + 10%, T A = -55 TO +125 °C)
P ARAMETER
S YMBOL S UBGROUPS M IN 1
M AX
U NITS
Memory
F IGURE 1. R EAD T IMIN
G W AVEFORM
T ABLE 9. 28C011T M ODE S ELECTION 1
1.X = Don’t care.
P ARAMETER CE
OE WE I/O RES RDY/BUSY Read V IL V IL V IH D OUT V H High-Z Standby V IH X X High-Z X High-Z Write V IL V IH V IL D IN V H High-Z --> V OL
Deselect V IL V IH V IH High-Z V H High-Z Write Inhibit X X V IH --X --X V IL X --X --Data Polling V IL V IL V IH Data Out (I/O7)
V H V OL Program X
X
X
High-Z
V IL
High-Z
Memory
Memory
Memory
F IGURE 6. D ATA P OLLIN
G T IMING W AVEFORM
Memory
F IGURE 7. S OFTWARE D ATA P ROTECTION T IMIN
G W AVEFORM (1) (IN PROTECTION MODE )
F IGURE 8. S OFTWARE D ATA P ROTECTION T IMIN
G W AVEFORM (2) (IN NON -PROTECTION MODE )
EEPROM A PPLICATION N OTES
This application note describes the programming procedures for the EEPROM modules and with details of various techniques to preserve data protection.
Automatic Page Write
Page-mode write feature allows 1 to 128 bytes of data to be written into the EEPROM in a single write cycle, and allows the undefined data within 128 bytes to be written corresponding to the undefined address (A0 to A6). Loading the first byte of data, the data load window opens 30μs for the second byte. In the same manner each additional byte of data can be loaded within 30μs. In case CE and WE are kept high for 100 μs after data input, EEPROM enters
erase and write mode automatically and only the input data are written into the EEPROM.
Memory
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of WE or CE.
Data Polling
Data Polling function allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data to be loaded outputs from I/O 7 to indicate that the EEPROM is per-forming a write operation.
RDY/Busy Signal
RDY/Busy signal also allows a comparison operation to determine the status of the EEPROM. The RDY/Busy signal has high impedance except in write cycle and is lowered to V OL after the first write signal. At the-end of a write cycle,the RDY/Busy signal changes state to high impedance.
RES Signal
When RES is LOW, the EEPROM cannot be read and programmed. Therefore, data can be protected by keeping RES low when V CC is switched. RES should be high during read and programming because it doesn’t provide a latch function.
Data Protection
To protect the data during operation and power on/off, the EEPROM has the internal functions described below.
1.
Data Protection against Noise of Control Pins (CE, OE, WE) during Operation.
Memory
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mis-take. To prevent this phenomenon, the EEPROM has a noise cancellation function that cuts noise if its width is 20ns or less in programming mode. Be careful not to allow noise of a width of more than 20ns on the control pins.
2. Data Protection at V CC on/off
When V CC is turned on or off, noise on the control pins generated by external circuits, such as CPUs, may turn the EEPROM to programming mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in unprogrammable state during V CC on/off by using a CPU reset signal to RES pin.
RES should be kept at V SS level when V CC is turned on or off. The EEPROM breaks off programming operation when RES become low, programming operation doesn’t finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms after the last data input.
3.
Software Data Protection
Memory
The software data protection function is to prevent unintentional programming caused by noise generated by external circuits. In software data protection mode, 3 bytes of data must be input before write data as follows. These bytes can switch the non-protection mode to the protection mode.
Software data protection mode can be canceled by inputting the following 6 bytes. Then, the EEPROM turns to the non-protec-
tion mode and can write data normally. However, when the data is input in the canceling cycle, the data cannot be written.
Memory
32-P IN R
AD -P AK ? F LAT P ACKAGE
Note: All dimensions in inches
S YMBOL D IMENSION
M IN N OM M AX A 0.1170.1300.143b 0.0150.0170.022c 0.0040.0050.009D --0.8200.830E 0.4040.4100.416E1----0.440
e 0.050BSC L 0.3500.3700.390Q 0.0210.0330.036S10.005
0.027--N
32
Memory
Note: All dimensions in inches.
28C011T 32-P IN R AD -T OLERANT F LAT P ACKAGE
S YMBOL D IMENSION
M IN N OM M AX A 0.0780.0870.096b 0.0150.0170.022c 0.0040.0050.009D --0.8200.830E 0.4040.4100.416E1----0.426
e 0.050BSC L 0.3900.4000.410S10.005
0.027--N
32
Important Notice:
These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.
The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information.
Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.
Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech-
nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
Memory
Memory
Product Ordering Options
Model Number
Feature Option Details
28C011T
XX
F
X
-XX
Access Time
Screening Flow
Package
Radiation Feature
Base Product Nomenclature
12 = 120 ns 15 = 150 ns 20 = 200 ns
Monolithic
S = Maxwell Class S B = Maxwell Class B
I = Industrial (testing @ -55°C, +25°C, +125°C)
E = Engineering (testing @ +25°C)
F = Flat Pack
RP = R AD -P AK ? package RT = No Radiation Guarentee CLass E and I Only
RT1 = Guaranteed to 10 krad at die level
RT2 = Guaranteed to 25 krad at die level
RT4 = Guaranteed to 40 krad at 1 Megabit (128k x 8-bit) EEPROM