DDR2 Registered SDRAM MODULE
240pin Registered Module based on 1Gb C-die
72-bit ECC
60FBGA & 63FBGA with Pb-Free
(RoHS compliant)
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TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Table of Contents
1.0 DDR2 Registered DIMM Ordering Information (4)
2.0 Features (4)
3.0 Address Configuration (4)
4.0 Pin Configurations (Front side/Back side) (5)
5.0Pin Description (5)
6.0 Input/Output Function Description (6)
7.0 Functional Block Diagram (7)
7.1 2GB, 256Mx72 Module - M393T5663CZ3/M393T5663CZA (7)
7.2 2GB, 256Mx72 Module - M393T5660CZ3/M393T5660CZA (8)
7.3 4GB, 512MBx72 Module - M393T5160CZ3/M393T5160CZA (9)
7.4 4GB, 512MBx72 Module - M392T5160CJ (10)
7.5 8GB, 1GBx72 Module - M393T1G60CJA (11)
8.0 Absolute Maximum DC Ratings (12)
9.0 AC & DC Operating Conditions (12)
9.1 Recommended DC Operating Conditions (SSTL - 1.8) (12)
9.2 Operating Temperature Condition (13)
9.3 Input DC Logic Level (13)
9.4 Input AC Logic Level (13)
9.5 AC Input Test Conditions (13)
10.0 IDD Specification Parameters Definition (14)
11.0 Operating Current Table (15)
11.1 M393T5663CZ3 / M393T5663CZA : 2GB(128Mx8 *18) Module (15)
11.2 M393T5663CZ3 / M393T5663CZA : 2GB(128Mx8 *18) Module (15)
11.3 M393T5660CZ3 / M393T5660CZA : 2GB(256Mx4 *18) Module (16)
11.4 M393T5660CZ3 / M393T5660CZA : 2GB(256Mx4 *18) Module (16)
11.5 M393T5160CZ3 / M393T5160CZA / M392T5160CJA : 4GB(256Mx4 *36 / 512Mx4 *18) Module (17)
11.6 M393T5160CZ3 / M393T5160CZA / M392T5160CJA : 4GB(256Mx4 *36 / 512Mx4 *18) Module (17)
11.7 M393T1G60CJA : 8GB(512Mx4 *36) Module (18)
11.8 M393T1G60CJA : 8GB(512Mx4 *36) Module (18)
12.0 Input/Output Capacitance (19)
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 (19)
13.1 Refresh Parameters by Device Density (19)
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin (19)
13.3 Timing Parameters by Speed Grade (20)
14.0 Physical Dimensions : (22)
14.1 128Mbx8/256Mbx4 based 256Mx72 Module (2/1 Ranks) (22)
14.2 256Mbx4 based 512Mx72 Module (2 Ranks) (23)
14.3 DDP 512Mbx4 based 512Mx72 Module (2 Ranks) (24)
14.4 DDP 512Mbx4 based 1Gx72 Module (4 Ranks) (25)
15.0 240 Pin DDR2 Registered DIMM Clock Topology (26)
Revision History
Revision Month Year History
1.0March2007 - Initial Release
1.1April2007 - Add the 2GB Registered DIMM Product
1.2June2007 - Added IDD values for DDR2-800 - Corrected Typo
1.3July2007 - Corrected Typo
1.4November2007 - Changed ordering information
1.0 DDR2 Registered DIMM Ordering Information
Part Number Density Organization Component Composition Number of Rank Parity Register Height
M393T5663CZ3-CD5/CC2GB256Mx72128Mx8(K4T1G084QC)*18EA2X30.00mm M393T5663CZA-CF7/E62GB256Mx72128Mx8(K4T1G084QC)*18EA2O30.00mm M393T5660CZ3-CD5/CC2GB256Mx72256Mx4(K4T1G044QC)*18EA1X30.00mm M393T5660CZA-CF7/E62GB256Mx72256Mx4(K4T1G044QC)*18EA1O30.00mm M393T5160CZ3-CD5/CC4GB512Mx72256Mx4(K4T1G044QC)*36EA2X30.00mm M393T5160CZA-CF7/E64GB512Mx72256Mx4(K4T1G044QC)*36EA2O30.00mm M392T5160CJA-CF7/E64GB512Mx72DDP512Mx4(K4T2G044QC)*18EA2O18.30mm M393T1G60CJA-CE6/D58GB1Gx72DDP512Mx4(K4T1G044QC)*36EA4O30.00mm Note :
1. “Z” of Part number(11th digit) stand for Lead-free products. and "J" of Part number(11th digit) stand for dual-die package products.
2. “3” of Part number(12th digit) stand for Non-parity Register products. and "A" of Part number(12th digit) stand for Parity Register products.
3. "92" of Part number(3~4th digit) stand for VLP(Very Low Profile) Register products.
2.0 Features
?Performance range
F7(DDR2-800)E6(DDR2-667)D5(DDR2-533)CC(DDR2-400)Unit Speed@CL3-400400400Mbps Speed@CL4533533533400Mbps Speed@CL5667667--Mbps Speed@CL6800---Mbps CL-tRCD-tRP6-6-65-5-54-4-43-3-3CK ?JEDEC standard 1.8V ± 0.1V Power Supply
?V DDQ = 1.8V ± 0.1V
?200 MHz f CK for 400Mb/sec/pin, 267MHz f CK for 533Mb/sec/pin, 333MHz f CK for 667Mb/sec/pin, 400MHz f CK for 800Mb/sec/pin
?8Banks
?Posted CAS
?Programmable CAS Latency: 3, 4, 5, 6
?Programmable Additive Latency: 0, 1 , 2 , 3, 4 and 5
?Write Latency(WL) = Read Latency(RL) -1
?Burst Length: 4 , 8(Interleave/nibble sequential)
?Programmable Sequential / Interleave Burst Mode
?Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
?Off-Chip Driver(OCD) Impedance Adjustment
?On Die Termination with selectable values(50/75/150 ohms or disable)
?PASR(Partial Array Self Refresh)
?Average Refresh Period 7.8us at lower than a T CASE 85°C, 3.9us at 85°C < T CASE < 95 °C - support High Temperature Self-Refresh rate enable feature
?Serial presence detect with EEPROM
?DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8
?All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
3.0 Address Configuration
Organization Row Address Column Address Bank Address Auto Precharge 256Mx4(1Gb) based Module A0-A13A0-A9, A11BA0-BA2A10
128Mx8(1Gb) based Module A0-A13A0-A9BA0-BA2A10
NC = No Connect, RFU = Reserved for Future Use
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1V REF 121V SS 31DQ19151V SS 61A4181V DDQ 91V SS 211DM5/DQS142V SS 122DQ432V SS 152DQ2862V DDQ 182A392DQS5212NC/DQS14
3DQ0123DQ533DQ24153DQ2963A2183A193DQS5213V SS 4DQ1124V SS 34DQ25154V SS 64
V DD
184V DD
94V SS 214DQ465V SS 125DM0/DQS935V SS 155DM3/DQS12KEY
95DQ42215DQ476DQS0126NC/DQS936DQS3156NC/DQS12
65V SS 185CK096DQ43216V SS 7DQS0127V SS 37DQS3157V SS 66V SS 186CK097V SS 217DQ528V SS 128DQ638V SS 158DQ3067V DD 187V DD 98DQ48218DQ539DQ2129DQ739DQ26159DQ3168NC/Par_In 188A099DQ49219V SS 10DQ3130V SS 40DQ27160V SS 69V DD 189V DD 100V SS 220S211V SS 131DQ1241V SS 161CB470A10/AP 190BA1101SA2221S312DQ8132DQ1342CB0162CB571BA0191V DDQ 102NC(TEST)222V SS 13DQ9133V SS 43CB1163V SS 72V DDQ 192RAS 103V SS 223DM6/DQS1514V SS 134DM1/DQS1044V SS 164DM8/DQS1773WE 193S0104DQS6224NC/DQS15
15DQS1135NC/DQS10
45DQS8165NC/DQS17
74CAS 194V DDQ 105DQS6225V SS 16DQS1136V SS 46DQS8166V SS 75V DDQ 195ODT0106V SS 226DQ5417V SS 137RFU 47V SS 167CB676S1196A13107DQ50227DQ5518RESET 138RFU 48CB2168CB777ODT1197V DD 108DQ51228V SS 19NC 139V SS 49CB3169V SS 78V DDQ 198V SS 109V SS 229DQ6020V SS 140DQ1450V SS 170V DDQ 79V SS 199DQ36110DQ56230DQ6121DQ10141DQ1551V DDQ 171CKE180DQ32200DQ37111DQ57231V SS 22DQ11142V SS 52CKE0172V DD 81DQ33201V SS 112V SS 232DM7/DQS1623V SS 143DQ2053V DD 173NC 82V SS 202DM4/DQS13113DQS7233NC/DQS16
24DQ16144DQ2154BA2174NC 83DQS4203NC/DQS13
114DQS7234V SS 25DQ17145V SS 55NC/Err_Out 175V DDQ 84DQS4204V SS 115V SS 235DQ6226V SS 146DM2/DQS1156V DDQ 176A1285V SS 205DQ38116DQ58236DQ6327DQS2147NC/DQS11
57A11177A986DQ34206DQ39117DQ59237V SS 28DQS2148V SS 58A7178V DD 87DQ35207V SS 118V SS 238VDDSPD 29V SS 149DQ2259V DD 179A888V SS 208DQ44119SDA 239SA030
DQ18
150
DQ23
60
A5
180
A6
89DQ40209DQ45120
SCL
240
SA1
90
DQ41
210
V SS * The VDD and VDDQ pins are tied to the single power-plane on PCB.
Pin Name Description
Pin Name Description CK0Clock Inputs, positive line ODT0~ODT1On die termination CK0Clock inputs, negative line DQ0~DQ63Data Input/Output
CKE0, CKE1Clock Enables CB0~CB7Data check bits Input/Output RAS Row Address Strobe DQS0~DQS8Data strobes
CAS Column Address Strobe DQS0~DQS8Data strobes, negative line WE Write Enable DM(0~8), DQS(9~17)Data Masks / Data strobes (Read)
S0~ S3
Chip
Selects DQS9~DQS17Data strobes (Read), negative line A0~A9, A11~A13Address Inputs
RFU Reserved for Future Use A10/AP Address Input/Autoprecharge NC No Connect
BA0~BA2DDR2 SDRAM Bank Address
TEST Memory bus test tool
(Not Connect and Not Useable on DIMMs)SCL Serial Presence Detect (SPD) Clock Input V DD Core Power SDA SPD Data Input/Output V DDQ I/O Power SA0~SA2SPD address
V SS Ground
Par_In Parity bit for the Address and Control bus V REF Input/Output Reference Err_Out Parity error found in the Address and Control bus V DDSPD
SPD Power
RESET
Register and PLL control pin
5.0Pin Description
4.0 Pin Configurations (Front side/Back side)
Symbol Type Description
CK0Input Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CK0Input Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.
CKE0~CKE1Input Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
S0~S3Input Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is dis-abled, new commands are ignored but previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high.
ODT0~ODT1Input I/O bus impedance control signals.
RAS, CAS, WE Input When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM.
V REF Supply Reference voltage for SSTL_18 inputs
V DDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity BA0~BA2Input Selects which SDRAM bank of eight is activated.
A0~A9,A10/AP
A11~A13Input During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge com-mand cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are used to define which bank to precharge.
DQ0~63,
CB0~CB7
In/Out Data and Check Bit Input/Output pins
DM0~DM8Input Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once the write command is registered into the SDRAM.
V DD, V SS Supply Power and ground for the DDR SDRAM input buffers and core logic
DQS0~DQS17In/Out Positive line of the differential data strobe for input and output data.
DQS0~DQS17In/Out Negative line of the differential data strobe for input and output data.
SA0~SA2Input These signals are tied at the system planar to either V SS or V DDSPD to configure the serial SPD EEPROM address range.
SDA In/Out This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DDSPD to act as a pullup.
SCL Input This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DDSPD to act as a pullup.
V DDSPD Supply Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6 Volt operation).
RESET Input The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-nized with the input clock )
Par_In Input Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even) Err_Out Output Parity error found in the Address and Control bus
TEST In/Out Used by memory bus analysis tools (unused on memory DIMMs) 6.0 Input/Output Function Description
RS0DQS0DQS0
DM0/DQS9NC/DQS9
DM/RDQS NU/RDQS
CS DQS DQS
DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D0
DQS1DQS1
DM1/DQS10NC/DQS10
DM/RDQS NU/RDQS
CS DQS DQS
DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D1
DQS2DQS2
DM2/DQS11NC/DQS11
DM/RDQS NU/RDQS
CS DQS DQS
DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D2
DQS3DQS3
DM3/DQS12NC/DQS12
DM/RDQS NU/RDQS
CS DQS DQS
DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D3
DQS8DQS8
DM8/DQS17NC/DQS17
DM/RDQS NU/RDQS
CS DQS DQS
CB0CB1CB2CB3CB4CB5CB6CB7I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D8
DQS4DQS4
DM4/DQS13NC/DQS13
DM/RDQS NU/RDQS
CS DQS DQS
DQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D4
DQS5DQS5
DM5/DQS14NC/DQS14
DM/RDQS NU/RDQS
CS DQS DQS
DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D5
DQS6DQS6
DM6/DQS15NC/DQS15
DM/RDQS NU/RDQS
CS DQS DQS
DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D6
DQS7DQS7
DM7/DQS16NC/DQS16
DM/RDQS NU/RDQS
CS DQS DQS
DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D7
DM/RDQS NU/RDQS
CS DQS DQS
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D9
DM/RDQS NU/RDQS
CS DQS DQS
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D10
DM/RDQS NU/RDQS
CS DQS DQS
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D11
DM/RDQS NU/RDQS
CS DQS DQS
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D12
DM/RDQS NU/RDQS
CS DQS DQS
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D17
DM/RDQS NU/RDQS
CS DQS DQS
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D13
DM/RDQS NU/RDQS
CS DQS DQS
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D14
DM/RDQS NU/RDQS
CS DQS DQS
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
D15
DM/RDQS NU/RDQS
CS DQS DQS
I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D16
RS1A0
Serial PD
A1
A2
SA0SA1SA2
SCL
SDA
V SS
D0 - D17
V DD /V DDQ D0 - D17D0 - D17VREF V DDSPD
Serial PD WP Note :
1. DQ-to-I/O wiring may be changed per nibble.
2. Unless otherwise noted, resister values are 22 Ohms
3. RS0 and RS1 alternate between the back and front sides of the DIMM
1:2R E G I S T E R
RST
S1*
BA0-BA2A0-A13RAS CAS WE CKE0CKE1RESET**
PCK7**
PCK7**
RS1-> CS : DDR2 SDRAMs D9-D17
RBA0-RBA2 -> BA0-BA2: DDR2 SDRAMs D0-D17RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17RRAS -> RAS : DDR2 SDRAMs D0-D17RCAS -> CAS : DDR2 SDRAMs D0-D17RWE -> WE : DDR2 SDRAMs D0-D17RCKE0 -> CKE : DDR2 SDRAMs D0-D8RCKE1 -> CKE : DDR2 SDRAMs D9-D17P L L
OE
CK0CK0RESET
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17PCK7 -> CK : Register PCK7 -> CK : Register
ODT0ODT1RODT0 -> ODT0 : DDR2 SDRAMs D0-D8RODT1 -> ODT1 : DDR2 SDRAMs D9-D17
S0*RSO-> CS : DDR2 SDRAMs D0-D8(populated as 2 rank of x8 DDR2 SDRAMs)
7.1 2GB, 256Mx72 Module - M393T5663CZ3/M393T5663CZA * S0 connects to DCS and S1 connects to CSR on a Register,
S1 connects to DCS and S0 connects to CSR on another Register.** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.
Signals for Address and Command Parity Function (M393T5663CZA)V SS V DD
PAR_IN C0C1
PPO QERR
Register A
PAR_IN 100K ohms
The resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register Options for Unused Address inputs"
V DD V DD
C0C1
PPO QERR
Err_Out
Register B
PAR_IN
7.0 Functional Block Diagram
VSS
RS0
DQS0
DQS0
DM CS DQS DQS
DQ0 DQ1 DQ2 DQ3I/O 0
I/O 1
I/O 2
I/O 3
D0
DM0/DQS9
NC/DQS9
DM CS DQS DQS
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
D9
DQS1
DQS1
DM CS DQS DQS
DQ8 DQ9 DQ10 DQ11I/O 0
I/O 1
I/O 2
I/O 3
D1
DM1/DQS10
NC/DQS10
DM CS DQS DQS
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
D10
DQS2
DQS2
DM CS DQS DQS
DQ16 DQ17 DQ18 DQ19I/O 0
I/O 1
I/O 2
I/O 3
D2
DM2/DQS11
NC/DQS11
DM CS DQS DQS
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
D11
DQS3
DQS3
DM CS DQS DQS
DQ24 DQ25 DQ26 DQ27I/O 0
I/O 1
I/O 2
I/O 3
D3
DM3/DQS12
NC/DQS12
DM CS DQS DQS
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
D12
DQS5
DQS5
DM CS DQS DQS
DQ40 DQ41 DQ42 DQ43I/O 0
I/O 1
I/O 2
I/O 3
D5
DM5/DQS14
NC/DQS14
DM CS DQS DQS
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
D14
DQS4
DQS4
DM CS DQS DQS
DQ32 DQ33 DQ34 DQ35I/O 0
I/O 1
I/O 2
I/O 3
D4
DM4/DQS13
NC/DQS13
DM CS DQS DQS
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
D13
DQS6
DQS6
DM CS DQS DQS
DQ48 DQ49 DQ50 DQ51I/O 0
I/O 1
I/O 2
I/O 3
D6
DM6/DQS15
NC/DQS15
DM CS DQS DQS
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
D15
DQS8
DQS8
DM CS DQS DQS
CB0 CB1 CB2 CB3I/O 0
I/O 1
I/O 2
I/O 3
D8
DM8/DQS17
NC/DQS17
DM CS DQS DQS
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
D17
DQS7
DQS7
DM CS DQS DQS
DQ56 DQ57 DQ58 DQ59
I/O 0
I/O 1
I/O 2
I/O 3
D7
DM7DQS16
NC/DQS16
DM CS DQS DQS
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
D16
A0
Serial PD
A1A2
SA0SA1SA2
SCL SDA
V SS D0 - D17
V DD/V DDQ D0 - D17
D0 - D17
VREF
V DDSPD Serial PD
WP
Note :
1. DQ-to-I/O wiring may be changed per nibble.
2. Unless otherwise noted, resister values are 22 Ohms 1:2
R
E
G
I
S
T
E
R
RST
S0*
BA0-BA2
A0-A13
RAS
CAS
WE
CKE0
ODT0
RESET**
PCK7** PCK7**RSO-> CS : DDR2 SDRAMs D0-D17
RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D17
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17
RRAS -> RAS : DDR2 SDRAMs D0-D17
RCAS -> CAS : DDR2 SDRAMs D0-D17
RWE -> WE : DDR2 SDRAMs D0-D17
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
P
L
L
OE
CK0
CK0
RESET
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK7 -> CK : Register
PCK7 -> CK : Register
* S0 connects to DCS of Register1 and CSR of Register2. CSR of reg-ister 1 and DCS of register 2 connects to VDD.
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers. S1, CKE1 and ODT1 are NC.
Signals for Address and Command Parity Function (M393T5660CZA)
V SS
V DD
PAR_IN
C0
C1
PPO
QERR
Register A
PAR_IN
100K ohms
The resistors on Par_In, A13, A14, A15, BA2 and the
signal line of Err_Out refer to the section: "Register
Options for Unused Address inputs"
V DD
V DD
C0
C1
PPO
QERR Err_Out
Register B
PAR_IN
A0
Serial PD
A1
A2
SA0SA1SA2
SCL
SDA
V SS
D0 - D35
V DD /V DDQ D0 - D35D0 - D35VREF V DDSPD Serial PD WP P L L
OE
CK0RESET
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35PCK7 -> CK : Register PCK7 -> CK : Register
1:2R E G I S T E R
RST
S1*
BA0-BA1A0-A13RAS CAS WE CKE0CKE1RESET**
PCK7**
PCK7**
RS1-> CS : DDR2 SDRAMs D18-D35
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35RRAS -> RAS : DDR2 SDRAMs D0-D35RCAS -> CAS : DDR2 SDRAMs D0-D35RWE -> WE : DDR2 SDRAMs D0-D35RCKE0 -> CKE : DDR2 SDRAMs D0-D17RCKE1 -> CKE : DDR2 SDRAMs D18-D35ODT0ODT1RODT0 -> ODT0 : DDR2 SDRAMs D0-D17RODT1 -> ODT1 : DDR2 SDRAMs D18-D35
S0*RSO-> CS : DDR2 SDRAMs D0-D17
VSS RS0
DQS0DQS0
DM
CS
DQS DQS
DQ0DQ1DQ2DQ3I/O 0I/O 1I/O 2I/O 3D0DM0/DQS9NC/DQS9
DM
CS
DQS DQS
DQ4DQ5DQ6DQ7
I/O 0I/O 1I/O 2I/O 3D9DQS1DQS1
DM CS DQS DQS DQ8DQ9DQ10DQ11I/O 0I/O 1I/O 2I/O 3D1DM1/DQS10NC/DQS10
DM CS DQS DQS DQ12DQ13DQ14DQ15
I/O 0
I/O 1I/O 2I/O 3D10DQS2DQS2
DM CS DQS DQS DQ16DQ17DQ18DQ19I/O 0I/O 1I/O 2I/O 3D2DM2/DQS11NC/DQS11
DM CS DQS DQS DQ20DQ21DQ22DQ23
I/O 0
I/O 1I/O 2I/O 3D11DQS3DQS3
DM CS DQS DQS DQ24DQ25DQ26DQ27I/O 0I/O 1I/O 2I/O 3D3DM3/DQS12NC/DQS12
DM CS DQS DQS DQ28DQ29DQ30DQ31
I/O 0
I/O 1I/O 2I/O 3D12DQS5DQS5
DM CS DQS DQS DQ40DQ41DQ42DQ43I/O 0I/O 1I/O 2I/O 3D5DM5/DQS14NC/DQS14
DM CS DQS DQS DQ44DQ45DQ46DQ47
I/O 0
I/O 1I/O 2I/O 3D14DQS4DQS4
DM CS DQS DQS DQ32DQ33DQ34DQ35I/O 0I/O 1I/O 2I/O 3D4DM4/DQS13NC/DQS13
DM CS DQS DQS DQ36DQ37DQ38DQ39
I/O 0
I/O 1I/O 2I/O 3D13DQS6DQS6
DM CS DQS DQS DQ48DQ49DQ50DQ51I/O 0I/O 1I/O 2I/O 3D6DM6/DQS15NC/DQS15
DM CS DQS DQS DQ52DQ53DQ54DQ55
I/O 0
I/O 1I/O 2I/O 3D15DQS8DQS8
DM CS DQS DQS CB0CB1CB2CB3I/O 0I/O 1I/O 2I/O 3D8DM8/DQS17NC/DQS17
DM CS DQS DQS CB4CB5CB6CB7I/O 0
I/O 1I/O 2I/O 3D17DQS7DQS7
DM CS DQS DQS DQ56DQ57DQ58DQ59I/O 0I/O 1I/O 2I/O 3D7DM7DQS16NC/DQS16
DM CS DQS DQS DQ60DQ61DQ62DQ63
I/O 0
I/O 1I/O 2I/O 3D16DM/
CS
DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D18DM/CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D19DM/CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D20DM CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D21DM CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D23DM CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D22DM CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D24DM CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D26DM CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D25DM
CS
DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D27DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D28DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D29DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D30DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D32DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D31DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D33DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D35DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D34RS1* S0 connects to DCS and S1 connects to CSR on a pair of Registers,
Other signals connect to one pair of four Registers.
Signals for Address and Command Parity Function (M393T5160CZA)V SS V DD
PAR_IN C0C1
PPO QERR
Register A
PAR_IN 100K ohms
The resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register Options for Unused Address inputs"
V DD V DD
C0C1
PPO QERR
Err_Out
Register B
PAR_IN
A0
Serial PD
A1
A2
SA0SA1SA2
SCL
SDA
V SS
D0 - D35
V DD /V DDQ D0 - D35D0 - D35VREF V DDSPD Serial PD WP P L L
OE
CK0RESET
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35PCK7 -> CK : Register PCK7 -> CK : Register
1:2R E G I S T E R
RST
S1*
BA0-BA1A0-A13RAS CAS WE CKE0CKE1RESET**
PCK7**
PCK7**
RS1-> CS : DDR2 SDRAMs D18-D35
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35RRAS -> RAS : DDR2 SDRAMs D0-D35RCAS -> CAS : DDR2 SDRAMs D0-D35RWE -> WE : DDR2 SDRAMs D0-D35RCKE0 -> CKE : DDR2 SDRAMs D0-D17RCKE1 -> CKE : DDR2 SDRAMs D18-D35ODT0ODT1RODT0 -> ODT0 : DDR2 SDRAMs D0-D17RODT1 -> ODT1 : DDR2 SDRAMs D18-D35
S0*RSO-> CS : DDR2 SDRAMs D0-D17
VSS RS0
DQS0DQS0
DM
CS
DQS DQS
DQ0DQ1DQ2DQ3I/O 0I/O 1I/O 2I/O 3D0DM0/DQS9NC/DQS9
DM
CS
DQS DQS
DQ4DQ5DQ6DQ7
I/O 0I/O 1I/O 2I/O 3D9DQS1DQS1
DM CS DQS DQS DQ8DQ9DQ10DQ11I/O 0I/O 1I/O 2I/O 3D1DM1/DQS10NC/DQS10
DM CS DQS DQS DQ12DQ13DQ14DQ15
I/O 0
I/O 1I/O 2I/O 3D10DQS2DQS2
DM CS DQS DQS DQ16DQ17DQ18DQ19I/O 0I/O 1I/O 2I/O 3D2DM2/DQS11NC/DQS11
DM CS DQS DQS DQ20DQ21DQ22DQ23
I/O 0
I/O 1I/O 2I/O 3D11DQS3DQS3
DM CS DQS DQS DQ24DQ25DQ26DQ27I/O 0I/O 1I/O 2I/O 3D3DM3/DQS12NC/DQS12
DM CS DQS DQS DQ28DQ29DQ30DQ31
I/O 0
I/O 1I/O 2I/O 3D12DQS5DQS5
DM CS DQS DQS DQ40DQ41DQ42DQ43I/O 0I/O 1I/O 2I/O 3D5DM5/DQS14NC/DQS14
DM CS DQS DQS DQ44DQ45DQ46DQ47
I/O 0
I/O 1I/O 2I/O 3D14DQS4DQS4
DM CS DQS DQS DQ32DQ33DQ34DQ35I/O 0I/O 1I/O 2I/O 3D4DM4/DQS13NC/DQS13
DM CS DQS DQS DQ36DQ37DQ38DQ39
I/O 0
I/O 1I/O 2I/O 3D13DQS6DQS6
DM CS DQS DQS DQ48DQ49DQ50DQ51I/O 0I/O 1I/O 2I/O 3D6DM6/DQS15NC/DQS15
DM CS DQS DQS DQ52DQ53DQ54DQ55
I/O 0
I/O 1I/O 2I/O 3D15DQS8DQS8
DM CS DQS DQS CB0CB1CB2CB3I/O 0I/O 1I/O 2I/O 3D8DM8/DQS17NC/DQS17
DM CS DQS DQS CB4CB5CB6CB7I/O 0
I/O 1I/O 2I/O 3D17DQS7DQS7
DM CS DQS DQS DQ56DQ57DQ58DQ59I/O 0I/O 1I/O 2I/O 3D7DM7DQS16NC/DQS16
DM CS DQS DQS DQ60DQ61DQ62DQ63
I/O 0
I/O 1I/O 2I/O 3D16DM/
CS
DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D18DM/CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D19DM/CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D20DM CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D21DM CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D23DM CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D22DM CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D24DM CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D26DM CS DQS DQS I/O 0
I/O 1I/O 2I/O 3D25DM
CS
DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D27DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D28DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D29DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D30DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D32DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D31DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D33DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D35DM CS DQS DQS
I/O 0
I/O 1I/O 2I/O 3
D34RS1* S0 connects to DCS and S1 connects to CSR on a pair of Registers,
Other signals connect to one pair of four Registers.
Signals for Address and Command Parity Function
V SS V SS
PAR_IN C1C2
PPO1QERR
Register A
PAR_IN1100K ohms
The resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register Options for Unused Address inputs"
V DD V DD
C1C2
PPO1QERR
Err_Out
Register B
PAR_IN1PPO2PAR_IN2
PPO2PAR_IN2
RODT0RS122 ?
DQS DQS DQ3~0DM D0RCKE0RS0C S 0C S 1C K E 0C K E 1O D T 0O D T 0
DQS0DQS0DQ3~0
DQS DQS DQ3~0DM D18C S 0C S 1C K E 0C K E 1O D T 0O D T 0
RODT1RS3RCKE1RS2
DQS DQS DQ3~0DM D1C S 0C S 1C K E 0C K E 1O D T 0O D T 0
DQS1DQS1DQ11~8
DQS DQS DQ3~0DM D19
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS DQS DQ3~0DM D3C S 0C S 1C K E 0C K E 1O D T 0O D T 0
DQS3DQS3DQ27~24
DQS DQS DQ3~0DM D21
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS DQS DQ3~0DM D2C S 0C S 1C K E 0C K E 1O D T 0O D T 0
DQS2DQS2DQ19~16
DQS DQS DQ3~0DM D20
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS DQS DQ3~0DM
D8C S 0C S 1C K E 0C K E 1O D T 0O D T 0
DQS8DQS8CB3~0
DQS DQS DQ3~0DM D26
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS DQS DQ3~0DM D4C S 0C S 1C K E 0C K E 1O D T 0O D T 0
DQS4DQS4DQ35~32
DQS DQS DQ3~0DM D22C S 0C S 1C K E 0C K E 1O D T 0O D T 0
DQS DQS DQ3~0DM D5C S 0C S 1C K E 0C K E 1O D T 0O D T 0
DQS5DQS5DQ43~40
DQS DQS DQ3~0DM D23
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS DQS DQ3~0DM
D7C S 0C S 1C K E 0C K E 1O D T 0O D T 0
DQS7DQS7DQ59~56
DQS DQS DQ3~0DM
D25
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS DQS DQ3~0DM D6C S 0C S 1C K E 0C K E 1O D T 0O D T 0
DQS6DQS6DQ51~48
DQS DQS DQ3~0DM D24
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
RODT0RS1RCKE0RS0RODT1RS3RCKE1RS2
RODT0RS10 ?
DQS DQS DQ3~0DM D9
RCKE0RS0
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS9DQS9DQ7~4
DQS DQS DQ3~0DM D27
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
RODT1RS3RCKE1RS2
DQS DQS DQ3~0DM D10
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS10DQS10DQ15~12
DQS DQS DQ3~0DM D28
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0DQS DQS DQ3~0DM D12
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS12DQS12DQ31~28
DQS DQS DQ3~0DM D30
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0DQS DQS DQ3~0DM D11
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS11DQS11DQ23~20
DQS DQS DQ3~0DM D29
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0DQS DQS DQ3~0DM
D17
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS17DQS17CB7~4
DQS DQS DQ3~0DM D35
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0DQS DQS DQ3~0DM D13
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS13DQS13DQ39~36
DQS DQS DQ3~0DM D31
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0DQS DQS DQ3~0DM D14
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS14DQS14DQ47~44
DQS DQS DQ3~0DM D32
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0DQS DQS DQ3~0DM
D16
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS16DQS16DQ63~60
DQS DQS DQ3~0DM
D34
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0DQS DQS DQ3~0DM D15
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0
DQS15DQS15DQ55~52
DQS DQS DQ3~0DM D33
C S 0C S 1C K E 0C K E 1O
D T 0O D T 0RODT0RS1RCKE0RS0RODT1RS3RCKE1RS2
P L
L
OE
CK0CK0RESET PCK7-> CK : Register PCK7-> CK : Register
PCK0-PCK6, PCK8, PCK9-> CK : DDR2 SDRAMs D0-D35
1:2R E G I S T E R
RST
S1,3**BA0-BA2A0-A15RAS CAS WE CKE0CKE1RESET**
PCK7**
PCK7**
RS1-> CS1 : DDR2 SDRAMs D0-D17, RS3-> CS1 : DDR2 SDRAMs D18-D35RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35RRAS -> RAS : DDR2 SDRAMs D0-D35RCAS -> CAS : DDR2 SDRAMs D0-D35
RWE -> WE : DDR2 SDRAMs D0-D35RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RCKE1 -> CKE : DDR2 SDRAMs D18-D35ODT0ODT1RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
RODT1 -> ODT1 : DDR2 SDRAMs D18-D35S0,2*RS0-> CS0 : DDR2 SDRAMs D0-D17, RS2-> CS0 : DDR2 SDRAMs D18-D35* S0 connects to DCS0, S1 to DCS1 on the first register, S2 connects DCS0, S3 connects DCS1, on the secon register
**A13-15, BA2 have optional pull down resistors (100K ohms), not indicated here.
A0Serial PD
A1A2
SA0SA1SA2
SCL SDA WP Register
PAR_IN
PARIN
PTYERR Register
PARIN
PTYERR
10 K ?
ERR_OUT
0 ?
PCK0-PCK6, PCK8, PCK9-> CK : DDR2 SDRAMs D0-D35
Note : There is no specific device V DD supply voltage requirement for SSTL-1.8 compliance. However under all conditions V DDQ must be less than or equal
to V DD .
1. The value of V REF may be selected by the user to provide optimum noise margin in the system. Typically the value of V REF is expected to be about 0.5 x V DDQ of the transmitting device and V REF is expected to track variations in V DDQ .
2. Peak to peak AC noise on V REF may not exceed +/-2% V REF (DC).
3. V TT of transmitting device must track V REF of receiving device.
4. AC parameters are measured with V DD , V DDQ and V DDL tied together.
Symbol Parameter
Rating
Units Notes
Min.Typ. Max.V DD Supply Voltage 1.7 1.8 1.9V V DDL Supply Voltage for DLL 1.7 1.8 1.9V 4V DDQ Supply Voltage for Output 1.7 1.8 1.9V 4V REF Input Reference Voltage 0.49*V DDQ 0.50*V DDQ
0.51*V DDQ mV 1,2V TT
Termination Voltage
V REF -0.04
V REF
V REF +0.04
V
3 Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2standard.
Symbol Parameter
Rating Units Notes V DD Voltage on V DD pin relative to V SS - 1.0 V ~ 2.3 V V 1V DDQ Voltage on V DDQ pin relative to V SS - 0.5 V ~ 2.3 V V 1V DDL Voltage on V DDL pin relative to V SS - 0.5 V ~ 2.3 V V 1V IN, V OUT Voltage on any pin relative to V SS - 0.5 V ~ 2.3 V V
1
T STG
Storage Temperature
-55 to +100
°C 1, 2
9.0 AC & DC Operating Conditions
9.1 Recommended DC Operating Conditions (SSTL - 1.8)
8.0 Absolute Maximum DC Ratings
Note:
1. Input waveform timing is referenced to the input signal crossing through the V IH/IL (AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from V REF to V IH (AC) min for rising edges and the range from V REF to V IL (AC)max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from V IL (AC) to V IH (AC) on the positive transitions and V IH (AC) to V IL (AC) on the negative transitions.
Symbol Condition
Value Units Notes V REF Input reference voltage
0.5 * V DDQ
V 1V SWING(MAX)
Input signal maximum peak to peak swing 1.0V 1SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
V DDQ V IH (AC) min
V IH (DC) min V REF
V IL (DC) max V IL (AC) max
V SS
< AC Input Test Signal Waveform >
V SWING(MAX)
delta TR
delta TF
V REF - V IL (AC) max
delta TF
Falling Slew =
Rising Slew =
V IH (AC) min - V REF
delta TR
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=
3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Symbol Parameter Rating Units Notes TOPER
Operating Temperature
0 to 95
°C
1, 2, 3
9.3 Input DC Logic Level
Symbol Parameter Min.Max.Units Notes
V IH (DC)DC input logic high V REF + 0.125
V DDQ + 0.3V V IL (DC)
DC input logic low
- 0.3
V REF - 0.125
V
9.4 Input AC Logic Level
Symbol Parameter DDR2-400, DDR2-533DDR2-667, DDR2-800Units Min.Max.Min.Max.V IH (AC)AC input logic high V REF + 0.250
-V REF + 0.200
-V V IL (AC)
AC input logic low
-V REF - 0.250
-V REF - 0.200
V
9.5 AC Input Test Conditions
9.2 Operating Temperature Condition
(IDD values are for full operating range of Voltage and Temperature)
Symbol Proposed Conditions Units Note
IDD0Operating one bank active-precharge current;
t CK = t CK(IDD), t RC = t RC(IDD), t RAS = t RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD1Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; t CK = t CK(IDD), t RC = t RC (IDD), t RAS = t RASmin(IDD), t RCD =
t RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern
is same as IDD4W
mA
IDD2P Precharge power-down current;
All banks idle; t CK = t CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
mA
IDD2Q Precharge quiet standby current;
All banks idle; t CK = t CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
mA
IDD2N Precharge standby current;
All banks idle; t CK = t CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
mA
IDD3P Active power-down current;
All banks open; t CK = t CK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0mA mA
Slow PDN Exit MRS(12) = 1mA mA
IDD3N Active standby current;
All banks open; t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP = t RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD4W Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP
= t RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
mA
IDD4R Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; t CK = t CK(IDD), t RAS = t RAS-
max(IDD), t RP = t RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
mA
IDD5B Burst auto refresh current;
t CK = t CK(IDD); Refresh command at every t RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD6Self refresh current;
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Normal mA
Low Power mA
IDD7Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = t RCD(IDD)-1*t CK(IDD); t CK = t CK(IDD), t RC =
t RC(IDD), t RRD = t RRD(IDD), t FAW = t FAW(IDD), t RCD = 1*t CK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol-
lowing page for detailed timing conditions
mA
10.0 IDD Specification Parameters Definition
(T A =0o C, VDD= 1.9V)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol F7(800@CL=6)
E6(667@CL=5)
D5(533@CL=4)
CC(400@CL=3)
Unit Notes
IDD01260117011251080mA IDD11350126012151170mA IDD2P 270270270270mA IDD2Q 810810810720mA IDD2N 900810810720mA IDD3P-F 810720630630mA IDD3P-S 324324324324mA IDD3N 1035945945855mA IDD4W 2025180016651440mA IDD4R 2115180015751395mA IDD5B 2115202519801890mA IDD6*270270270270mA IDD7
3150
2925
2745
2520
mA
(T A =0o C, VDD= 1.9V)
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol F7(800@CL=6)
E6(667@CL=5)
D5(533@CL=4)
CC(400@CL=3)
Unit Notes
IDD01950176016151470mA IDD12120192017651610mA IDD2P 910850790730mA IDD2Q 1520143013401160mA IDD2N 1470131012401080mA IDD3P-F 1540135011601060mA IDD3P-S 1054954854754mA IDD3N 1595143513651205mA IDD4W 2675236021351820mA IDD4R 2905248021451855mA IDD5B 2945270525102270mA IDD6*270270270270mA IDD7
4180
3795
3455
3070
mA
11.2 M393T5663CZ3 / M393T5663CZA : 2GB(128Mx8 *18) Module
- considering Register and PLL current value
11.1 M393T5663CZ3 / M393T5663CZA : 2GB(128Mx8 *18) Module
11.0 Operating Current Table
(T A =0o C, VDD= 1.9V)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol F7(800@CL=6)
E6(667@CL=5)
D5(533@CL=4)
CC(400@CL=3)
Unit Notes
IDD01620153014401440mA IDD11800171016201620mA IDD2P 270270270270mA IDD2Q 810810810720mA IDD2N 900810810720mA IDD3P-F 810720630630mA IDD3P-S 324324324324mA IDD3N 117010801080990mA IDD4W 2880243021602070mA IDD4R 2880243021601890mA IDD5B 3330324031503060mA IDD6*270270270270mA IDD7
5400
5040
4680
4320
mA
(T A =0o C, VDD= 1.9V)
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol F7(800@CL=6)
E6(667@CL=5)
D5(533@CL=4)
CC(400@CL=3)
Unit Notes
IDD02310212019301830mA IDD12570237021702060mA IDD2P 910850790730mA IDD2Q 1520143013401160mA IDD2N 1470131012401080mA IDD3P-F 1540135011601060mA IDD3P-S 1054954854754mA IDD3N 1730157015001340mA IDD4W 3530299026302450mA IDD4R 3670311027302350mA IDD5B 4160392036803440mA IDD6*270270270270mA IDD7
6430
5910
5390
4870
mA
11.4 M393T5660CZ3 / M393T5660CZA : 2GB(256Mx4 *18) Module
- considering Register and PLL current value 11.3 M393T5660CZ3 / M393T5660CZA : 2GB(256Mx4 *18) Module
(T A =0o C, VDD= 1.9V)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol F7(800@CL=6)
E6(667@CL=5)
D5(533@CL=4)
CC(400@CL=3)
Unit Notes
IDD02520234022502160mA IDD12700252024302340mA IDD2P 540540540540mA IDD2Q 1620162016201440mA IDD2N 1800162016201440mA IDD3P-F 1620144012601260mA IDD3P-S 648648648648mA IDD3N 2070189018901710mA IDD4W 3780324029702790mA IDD4R 3780324029702610mA IDD5B 4230405039603780mA IDD6*540540540540mA IDD7
6300
5850
5490
5040
mA
(T A =0o C, VDD= 1.9V)* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol F7(800@CL=6)
E6(667@CL=5)
D5(533@CL=4)
CC(400@CL=3)
Unit Notes
IDD03540321029702730mA IDD13860352032703020mA IDD2P 1490140013101220mA IDD2Q 2680254024002080mA IDD2N 2600232022201940mA IDD3P-F 2710238020501900mA IDD3P-S 1738158814381288mA IDD3N 2860258024802200mA IDD4W 4770409036803360mA IDD4R 4870418037603250mA IDD5B 5450505047404340mA IDD6*540540540540mA IDD7
8010
7300
6680
5970
mA
11.6 M393T5160CZ3 / M393T5160CZA / M392T5160CJA : 4GB(256Mx4 *36 / 512Mx4 *18) Module
- considering Register and PLL current value
11.5 M393T5160CZ3 / M393T5160CZA / M392T5160CJA : 4GB(256Mx4 *36 / 512Mx4 *18) Module
(T A =0o C, VDD= 1.9V)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol E6(667@CL=5)
D5(533@CL=4)
CC(400@CL=3)
Unit Notes
IDD0396038703600mA IDD1414040503780mA IDD2P 108010801080mA IDD2Q 324032402880mA IDD2N 324032402880mA IDD3P-F 288025202520mA IDD3P-S 129612961296mA IDD3N 351035103150mA IDD4W 486045904230mA IDD4R 486045904050mA IDD5B 567055805220mA IDD6*108010801080mA IDD7
7470
7110
6480
mA
(T A =0o C, VDD= 1.9V)* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol E6(667@CL=5)
D5(533@CL=4)
CC(400@CL=3)
Unit Notes
IDD0483045904170mA IDD1514048904460mA IDD2P 194018501760mA IDD2Q 416040203520mA IDD2N 394038403380mA IDD3P-F 382033103160mA IDD3P-S 223620861936mA IDD3N 420041003640mA IDD4W 571053004800mA IDD4R 580053804690mA IDD5B 667063605780mA IDD6*108010801080mA IDD7
8920
8300
7410
mA
11.8 M393T1G60CJA : 8GB(512Mx4 *36) Module
- considering Register and PLL current value
11.7 M393T1G60CJA : 8GB(512Mx4 *36) Module
(V DD =1.8V, V DDQ =1.8V, T A =25o C)
* DM is internally loaded to match DQ and DQS identically.
Parameter Sym.
Min
Max
Min
Max
Min
Max
Min
Max
Units
Part-Number
M393T5663CZ3M393T5663CZA M393T5660CZ3M393T5660CZA M393T5160CZ3M393T5160CZA M392T5160CJA M393T1G60CJA Input capacitance, CK and CK CCK -11-11-11-11pF
Input capacitance, CKE and CS CI1-12-12-12-12Input capacitance, Addr,RAS,CAS,WE CI2-12-12-12-12Input/output capacitance, DQ, DM, DQS, DQS
CIO
-10
-10
-10
-10
Parameter
Symbol 256Mb 512Mb 1Gb 2Gb 4Gb Units Refresh to active/Refresh command time tRFC
75105127.5195327.5ns Average periodic refresh interval
tREFI
0 °C ≤ T CASE ≤ 85°C 7.87.87.87.87.8μs 85 °C < T CASE ≤ 95°C
3.9
3.9
3.9
3.9
3.9
μs
Speed DDR2-800(F7)
DDR2-667(E6)
DDR2-533(D5)
DDR2-400(CC)
Units
Bin (CL - tRCD - tRP)
6 - 6 - 6
5 - 5 - 5
4 - 4 - 4
3 - 3 - 3
Parameter min max min max min max min max tCK, CL=3--585858ns tCK, CL=4 3.758 3.758 3.75858ns tCK, CL=53838 3.758--ns tCK, CL=6 2.58------ns tRCD 15-15-15-15-ns tRP 15-15-15-15-ns tRC 60-60-60-55-ns tRAS
45
70000
45
70000
45
70000
40
70000
ns 13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400
(0 °C < T OPER < 95 °C; V DDQ = 1.8V + 0.1V; V DD = 1.8V + 0.1V)
13.1 Refresh Parameters by Device Density
13.2 Speed Bins and CL, tRCD, tRP , tRC and tRAS for Corresponding Bin 12.0 Input/Output Capacitance
Parameter Symbol
DDR2-800DDR2-667DDR2-533DDR2-400
Units Notes min max min max min max min max
DQ output access time from CK/CK tAC- 400400-450+450-500+500-600+600ps DQS output access time from CK/CK tDQSCK- 350350-400+400-450+450-500+500ps CK high-level width tCH0.450.550.450.550.450.550.450.55tCK CK low-level width tCL0.450.550.450.550.450.550.450.55tCK
CK half period tHP min(tCL,t
CH)
x
min(tCL,
tCH)
x
min(tCL,
tCH)
x
min(tCL,
tCH)
x ps
Clock cycle time, CL=x tCK25008000300080003750800050008000ps DQ and DM input hold time tDH(base)125x175x225x275x ps DQ and DM input setup time tDS(base)50x100x100x150x ps Control & Address input pulse width for
each input
tIPW0.6x0.6x0.6x0.6x tCK DQ and DM input pulse width for each input tDIPW0.35x0.35x0.35x0.35x tCK Data-out high-impedance time from CK/CK tHZ x tAC max x tAC max x tAC max x tAC max ps DQS low-impedance time from CK/CK tLZ(DQS)tAC min tAC max tAC min tAC max tAC min tAC max tAC min tAC max ps
DQ low-impedance time from CK/CK tLZ(DQ)2*tAC
min
tAC max
2*tAC
min
tAC max2*tACmin tAC max2*tACmin tAC max ps
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ x200x240x300x350ps DQ hold skew factor tQHS x300x340x400x450ps
DQ/DQS output hold time from DQS tQH tHP -
tQHS
x
tHP -
tQHS
x
tHP -
tQHS
x
tHP -
tQHS
x ps
First DQS latching transition to associated
clock edge
tDQSS- 0.250.25-0.250.25-0.250.25-0.250.25tCK
DQS input high pulse width tDQSH0.35x0.35x0.35x0.35x tCK
DQS input low pulse width tDQSL0.35x0.35x0.35x0.35x tCK DQS falling edge to CK setup time tDSS0.2x0.2x0.2x0.2x tCK DQS falling edge hold time from CK tDSH0.2x0.2x0.2x0.2x tCK Mode register set command cycle time tMRD2x2x2x2x tCK Write postamble tWPST0.40.60.40.60.40.60.40.6tCK Write preamble tWPRE0.35x0.35x0.35x0.35x tCK Address and control input hold time tIH(base)250x275x375x475x ps Address and control input setup time tIS(base)175x200x250x350x ps Read preamble tRPRE0.9 1.10.9 1.10.9 1.10.9 1.1tCK Read postamble tRPST0.40.60.40.60.40.60.40.6tCK Active to active command period for 1KB
page size products
tRRD7.5x7.5x7.5x7.5x ns
Active to active command period for 2KB
page size products
tRRD10x10x10x10x ns
Four Activate Window for 1KB page size
products
tFAW3537.537.537.5ns
Four Activate Window for 2KB page size
products
tFAW45505050ns CAS to CAS command delay tCCD2x222tCK Write recovery time tWR15x15x15x15x ns Auto precharge write recovery + precharge
time
tDAL WR+tRP x WR+tRP x WR+tRP x WR+tRP x tCK Internal write to read command delay tWTR7.57.5x7.5x10x ns Internal read to precharge command delay tRTP7.57.57.57.5ns Exit self refresh to a non-read command tXSNR tRFC + 10tRFC + 10tRFC + 10tRFC + 10ns Exit self refresh to a read command tXSRD200x200200200tCK
Exit precharge power down to any non-read command tXP2x2x2x2x tCK
13.3 Timing Parameters by Speed Grade