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AFE5804ZCFT中文资料

FEATURES DESCRIPTION

APPLICATIONS

8 Channels

SPI

IN1

IN8

..CH1

LVDS

OUT

CH8

AFE5804

https://www.doczj.com/doc/8c18987208.html,................................................................................................................................................SBOS442A–JUNE2008–REVISED SEPTEMBER2008 FULLY-INTEGRATED,8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND

0.89nV/√12-Bit,40MSPS,101mW/Channel

?8-Channel Complete Analog Front-End:The AFE5804is a complete analog front-end device

specifically designed for ultrasound systems that –LNA,VCA,PGA,LPF,and ADC

require low power and small size.

?Mode Control for Power/Noise Optimization:

The AFE5804consists of eight channels,including a –Low Noise(Full-Channel):

low-noise amplifier(LNA),voltage-controlled

0.89nV/√Hz(TGC Mode I)

attenuator(VCA),programmable gain amplifier

1.23nV/√Hz(TGC Mode II)

(PGA),low-pass filter(LPF),and a12-bit

1.03nV/√Hz(PW Mode)

analog-to-digital converter(ADC)with low voltage –Ultra-Low Power:differential signaling(LVDS)data outputs.

101mW/Channel(TGC Mode II)

The LNA gain is set for20dB gain and has excellent 65mW/Channel(CW Mode)

noise and signal handling capabilities,including fast ?Low-Noise Pre-Amp(LNA):overload recovery.VCA gain can vary over a46dB –0.75nV/√Hz range with a0V to1.2V control voltage common to all

channels of the AFE5804.

–20dB Fixed Gain

The PGA can be programmed for gains of20dB,–280mV PP Linear Input Range

25dB,27dB,and30dB.The internal low-pass filter ?Variable-Gain Amplifier:

can also be programmed to12.5MHz or17MHz.

–Gain Control Range:46dB

The LVDS outputs of the ADC reduce the number of ?PGA Gain Settings:20dB,25dB,27dB,30dB

interface lines to an ASIC or FPGA,thereby enabling ?Low-Pass Filter:the high system integration densities desired for

portable systems.The ADC can either be operated –Selectable BW:12.5MHz,17MHz

with internal or external references.The ADC also –2nd-Order,Bessel

features a signal-to-noise ratio(SNR)enhancement ?Gain Error:±0.5dB mode that can be useful at high gains.

?Channel Matching:±0.25dB

The AFE5804is available in a15mm×9mm,?Clamping135-ball BGA package that is Pb-free

(RoHS-compliant)and green.It is specified for ?Fast Overload Recovery:Two Clock Cycles

operation from0°C to+85°C.

?12-Bit Analog-to-Digital Converter:

–10MSPS to50MSPS

–69dB SNR at10MHz

–Serial LVDS Interface

?Integrated CW Switch Matrix

?15mm×9mm,135-BGA Package:

–Pb-Free(RoHS-Compliant)and Green

?Medical Imaging,Ultrasound

–Portable Systems

–Battery-Powered Systems

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Infineon is a registered trademark of Infineon Technologies.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.Copyright?2008,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas

Instruments standard warranty.Production processing does not

necessarily include testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS (1)

AFE5804

SBOS442A–JUNE 2008–REVISED SEPTEMBER https://www.doczj.com/doc/8c18987208.html,

This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGING/ORDERING INFORMATION (1)(2)

OPERATING PACKAGE TEMPERATURE

ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR

RANGE NUMBER MEDIA,QUANTITY ECO STATUS

AFE5804ZCFR Tape and Reel,1000AFE5804

μFBGA-135

ZCF

0°C to +85°C

AFE5804ZCFT Tape and Reel,250

Pb-Free,Green AFE5804ZCF

Tray,160

(1)For the most current package and ordering information see the Package Option Addendum at the end of this document,or see the TI web site at https://www.doczj.com/doc/8c18987208.html, .

(2)

These packages conform to Lead (Pb)-free and green manufacturing specifications.Additional details including specific material content can be accessed at https://www.doczj.com/doc/8c18987208.html, /leadfree.

GREEN:TI defines Green to mean Lead (Pb)-Free and in addition,uses less package materials that do not contain halogens,including bromine (Br),or antimony (Sb)above 0.1%of total product weight.N/A:Not yet available Lead (Pb)-Free;for estimated conversion dates,go to https://www.doczj.com/doc/8c18987208.html,/leadfree .Pb-FREE:TI defines Lead (Pb)-Free to mean RoHS compatible,including a lead concentration that does not weight,and,if designed to be soldered,suitable for use in specified lead-free soldering processes.

Over operating free-air temperature range,unless otherwise noted.

AFE5804

UNIT Supply voltage range,AVDD1–0.3to +3.9V Supply voltage range,AVDD2–0.3to +3.9V Supply voltage range,AVDD_5V –0.3to +6V Supply voltage range,DVDD –0.3to +3.9V Supply voltage range,LVDD –0.3to +2.2V Voltage between AVSS1and LVSS –0.3to +0.3

V Voltage at analog inputs

–0.3to minimum [3.6,(AVDD2+0.3)]

V External voltage applied to REFT-pin –0.3to +3V External voltage applied to REFB-pin –0.3to +2

V Voltage at digital inputs –0.3to minimum [3.9,(AVDD2+0.3)]

V Peak solder temperature (2)

+260°C Maximum junction temperature,T J +125°C Storage temperature range –55to +150°C Operating temperature range

0to +85°C HBM

2000V ESD ratings

CDM 750V MM

150

(1)Stresses above these ratings may cause permanent damage.Exposure to absolute maximum conditions for extended periods may degrade device reliability.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those specified is not supported.(2)

Device complies with JSTD-020D.

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ELECTRICAL CHARACTERISTICS AFE5804

https://www.doczj.com/doc/8c18987208.html,................................................................................................................................................SBOS442A–JUNE2008–REVISED SEPTEMBER2008 At AVDD_5V=5.0V,AVDD1=AVDD2=DVDD=3.3V,LVDD=1.8V,TGC mode I,single-ended input into LNA,ac-coupled

(1.0μF),V CNTL=1.0V,f IN=5MHz,Clock=40MSPS,50%duty cycle,LPF=12.5MHz,internal reference mode,ISET=56k?,

LVDS buffer setting=3.5mA,and ambient temperature T A=+25°C,unless otherwise noted.

AFE5804

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PREAMPLIFIER(LNA)

Gain A SE-input to differential output20dB

Input voltage(TGC,PW modes)V IN Linear operation(HD2≤40dB)280mV PP (CW mode)Linear operation220mV PP

Maximum input voltage Limited by internal diodes600mV PP Input voltage noise(TGC)e n(RTI)R S=0?,f=2MHz0.75nV/√Hz

TGC mode I3pA/√Hz Input current noise I n(RTI)

TGC mode II 1.7pA/√Hz Common-mode voltage,input V CMI Internally generated 2.4V

Bandwidth BW Small-signal,–3dB55MHz

Input resistance R IN At2.5MHz8k?

Includes internal ESD and clamping

Input capacitance C IN16pF

diodes

FULL-SIGNAL CHANNEL(LNA+VCA+LPF+ADC)

Input voltage noise

e n R S=0?,f=2MHz,PGA=30dB0.89nV/√Hz

(TGC mode I)

Input voltage noise(TGC mode II)R S=0?,f=2MHz,PGA=30dB 1.23nV/√Hz

Input voltage noise(PW mode)R S=0?,f=2MHz,PGA=30dB 1.03nV/√Hz

Noise figure NF R S=200?,f=2MHz 1.1dB

Low-pass filter bandwidth LPF At–3dB,selectable through SPI12.5,17MHz

Bandwidth tolerance±10%

High-pass filter HPF(First-order,due to internal ac-coupling)200kHz

Group delay variation1MHz to10MHz±3ns

≤6dB overload to within3%,

Overload recovery2Clock Cycles

V CNTL=0V to1.2V

ACCURACY

Gain(PGA)Selectable through SPI20,25,27,30dB

Total gain,max(1)LNA+PGA gain,V CNTL=1.2V47.54950.5dB

V CNTL=0V to1.2V46dB Gain range

V CNTL=0.1V to1.0V40dB

1.0V

Gain matching Channel-to-channel–0.5±0.25+0.5dB

Offset error V CNTL=1.2V,PGA=30dB–39+39LSB

Offset error drift(tempco)±5ppm/°C

Clamp level Level internally fixed before LPF 2.3V PP

GAIN CONTROL(VCA)

Input voltage range V CNTL Gain range=46dB0to1.2V

Gain slope V CNTL=0.1V to1.0V44.4dB/V

Input resistance25k?

Response time V CNTL=0V to1.2V step;to90%signal0.5μs

(1)Excludes digital gain within ADC.

(2)Excludes error of internal reference.

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AFE5804

SBOS442A–JUNE2008–REVISED https://www.doczj.com/doc/8c18987208.html, ELECTRICAL CHARACTERISTICS(continued)

At AVDD_5V=5.0V,AVDD1=AVDD2=DVDD=3.3V,LVDD=1.8V,TGC mode I,single-ended input into LNA,ac-coupled

(1.0μF),V CNTL=1.0V,f IN=5MHz,Clock=40MSPS,50%duty cycle,LPF=12.5MHz,internal reference mode,ISET=56k?,

LVDS buffer setting=3.5mA,and ambient temperature T A=+25°C,unless otherwise noted.

AFE5804

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE

f IN=2MHz;–1dBFS

59.7dBFS

(V CNTL=1.0V,PGA=30dB)

Signal-to-noise ratio SNR

f IN=5MHz;–1dBFS59.5dBFS

f IN=10MHz;–1dBFS59.1dBFS

f IN=5MHz;–1dBFS

–45dBFS

(V CNTL=0.35V,PGA=30dB)

f IN=5MHz;–1dBFS

Second-harmonic distortion HD2–50–70dBFS

(V CNTL=1V,PGA=30dB)

f IN=5MHz;–6dBFS

–61–70dBFS

(V CNTL=1V,PGA=20dB)

f IN=5MHz;–1dBFS

–43dBFS

(V CNTL=0.35V,PGA=30dB)

f IN=5MHz;–1dBFS

Third-harmonic distortion HD3–43–50dBFS

(V CNTL=1V,PGA=30dB)

f IN=5MHz;–6dBFS

–61–70dBFS

(V CNTL=1V,PGA=20dB)

f1=4.99MHz at–6dBFS,

Intermodulation distortion IMD358dBc

f2=5.01MHz at–32dBFS

Crosstalk f IN≤5MHz,V CNTL=0.6V,–6dBFS–67dBc

CW—SIGNAL CHANNELS

Input voltage noise(CW)e n R S=0?,f=2MHz 1.1nV/√Hz

Output noise correlation factor Summing of eight channels0.6%

At V IN=100mV PP13.8mA/V Output transconductance(V/I)

At V IN=270mV PP12.2mA/V Dynamic CW output current,max I OUTAC 2.9mA PP

Static CW output current(sink)I OUTDC0.9mA

Output common-mode voltage(3)VCM 2.5V

Output impedance50k?

Output capacitance10pF

INTERNAL REFERENCE VOLTAGES(ADC)

Reference top VREFT0.5V

Reference bottom VREFB 2.5V

VREFT–VREFB 1.952 2.05V

Common-mode voltage(internal)VCM 1.425 1.5 1.575V

VCM output current±2mA

(3)CW outputs require an externally applied bias voltage of+2.5V.

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AFE5804

At AVDD_5V=5.0V,AVDD1=AVDD2=DVDD=3.3V,LVDD=1.8V,TGC mode I,single-ended input into LNA,ac-coupled

(1.0μF),V CNTL=1.0V,f IN=5MHz,Clock=40MSPS,50%duty cycle,LPF=12.5MHz,internal reference mode,ISET=56k?,

LVDS buffer setting=3.5mA,and ambient temperature T A=+25°C,unless otherwise noted.

AFE5804

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EXTERNAL REFERENCE VOLTAGES(ADC)

Reference top VREFT 2.4 2.5 2.6V

Reference bottom VREFB0.40.50.6V

VREFT–VREFB 1.9 2.1V

Switching current(4) 2.5mA

POWER SUPPLY

SUPPLY VOLTAGES At40MSPS

AVDD1,AVDD2,DVDD Operating 3.15 3.3 3.47V

AVDD_5V Operating 4.755 5.25V

LVDD 1.7 1.8 1.9V

SUPPLY CURRENTS

IAVDD1(ADC)99110mA

TGC mode I123136mA IAVDD2(VCA)

CW mode6375mA

TGC mode I710mA IAVDD_5V(VCA)

CW mode5461mA IDVDD(VCA) 1.5 3.0mA

ILVDD(ADC)6880mA

All channels,TGC mode I,no signal896985mW

All channels,TGC mode II,no signal808898mW Power dissipation,total(5)All channels,PW mode,no signal840925mW

All channels,CW mode,no signal(6)525575mW

No clock applied,no signal528mW POWER-DOWN MODES

Power-down dissipation,total Complete power-down mode5268mW

Power-down response time 1.0μs

Power-up response time PD to valid output(90%level)50μs

Power-down dissipation(7)Partial power-down mode95mW

THERMAL CHARACTERISTICS

Temperature range085°C

Thermal resistance,T JA32°C/W

Thermal resistance,T JC 4.2°C/W

(4)Current drawn by the eight ADC channels from the external reference voltages;sourcing for VREFT,sinking for VREFB.

(5)Programmable power affects on the front-end;ADC power consumption remains constant at about57mW/channel for40MSPS.

(6)ADC powered-down during CW mode.

(7)At VCA_PD pin pulled high;see also Power-Down Timing diagram.

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DIGITAL CHARACTERISTICS

AFE5804

SBOS442A–JUNE 2008–REVISED SEPTEMBER https://www.doczj.com/doc/8c18987208.html,

DC specifications refer to the condition where the digital outputs are not switching,but are permanently at a valid logic level

'0'or '1'.At C LOAD =5pF (1),I OUT =3.5mA (2),R LOAD =100?(2),and no internal termination,unless otherwise noted.

AFE5804

PARAMETER

TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 1.4 3.3V Low-level input voltage 0

0.3

V High-level input current 10μA Low-level input current (3)

–10μA Input capacitance 3

LVDS OUTPUTS High-level output voltage 1375mV Low-level output voltage 1025mV Output differential voltage,|V OD |350mV V OS output offset voltage (2)Common-mode voltage of OUTP and OUTM 1200mV Output capacitance inside the device,from either

Output capacitance 2pF output to ground

1x (clock FCLKP and FCLKM 1050MHz rate)6x (clock LCLKP and LCLKM 60

300

MHz

rate)

CLOCK Clock input rate 10

MSPS Clock duty cycle

50%Clock input amplitude,differential Sine-wave,ac-coupled 3V PP (VCLKP –VCLKM)

LVPECL,ac-coupled 1.6V PP LVDS,ac-coupled

0.7

V PP

Clock input amplitude,single-ended (VCLKP)

High-level input voltage,V IH CMOS 2.2

V Low-level input voltage,V IL

CMOS

0.6

(1)C LOAD is the effective external single-ended load capacitance between each output pin and ground.

(2)I OUT refers to the LVDS buffer current setting;R LOAD is the differential load resistance between the LVDS output pair.(3)Except pin J3which has an internal pull-up resistor (52k ?)to 3.3V.

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FUNCTIONAL BLOCK DIAGRAM

IN1

OUT1P

OUT1M

LCLKP

LCLKM

FCLKP

FCLKM

CW[0:9]

OUT8P

OUT8M

(

)

(

)

(

)

(

)

(

)

IN8 VCNTL

?Channels

2 to 7

(

)

AFE5804

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PIN CONFIGURATION

Columns

35246

879

R o w s

AFE5804

SBOS442A–JUNE 2008–REVISED SEPTEMBER https://www.doczj.com/doc/8c18987208.html,

ZCF PACKAGE

135-BGA BOTTOM VIEW

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Legend:AVDD1

+3.3V; Analog AVDD2+3.3V; Analog +3.3V; Analog +1.8V; Digital +5V; Analog DVDD LVDD AVDD_5V

Analog Ground Analog Ground Digital Ground

AVSS1AVSS2LVSS

AFE5804

ZCF PACKAGE

135-BGA

CONFIGURATION MAP (TOP VIEW)

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AFE5804

SBOS442A–JUNE2008–REVISED https://www.doczj.com/doc/8c18987208.html,

Table1.TERMINAL FUNCTIONS

PIN NO.PIN NAME FUNCTION DESCRIPTION

H7CS Input Chip select for serial interface;active low

H1ADS_PD Input Power-down pin for ADS;active high

H9ADS_RESET Input RESET input for ADS;active low

H6SCLK Input Serial clock input for serial interface

H8SDATA Input Serial data input for serial interface

J2,L2,K7,J7,

AVDD1POWER 3.3V analog supply for ADS

K3,L8,K5,K6

L3,M3,L4,M4,

L5,M5,L6,M6,AVSS1GND Analog ground for ADS

L7,M7,J1

P5,N6,N7LVDD POWER 1.8V digital supply for ADS

N3,N4,N5,R5LVSS GND Digital ground for ADS

C5,D5DVDD POWER 3.3V digital supply for the VCA;connect to the3.3V analog supply(AVDD2).

C2,C8,G2,G8AVDD2POWER 3.3V analog supply for VCA

E2,E8AVDD_5V POWER5V supply for VCA

C3,D3,C4,D4,

E4,F4,G4,E5,

F5,G5,C6,D6,AVSS2GND Analog ground for VCA

E6,F6,G6,C7,

D7,J4,J5,J6

K1CLKM Input Negative clock input for ADS(connect to Ground in single-ended clock mode)

L1CLKP Input Positive clock input for ADS

K8CM Input/Output 1.5V common-mode I/O for ADS.Becomes input pin in one of the external reference modes.

C9CW0Output CW output0

D9CW1Output CW output1

E9CW2Output CW output2

F9CW3Output CW output3

G9CW4Output CW output4

G1CW5Output CW output5

F1CW6Output CW output6

E1CW7Output CW output7

D1CW8Output CW output8

C1CW9Output CW output9

L9EN_SM Input Enables access to the VCA register.Active high.Connect permanently to3.3V(AVDD2).

N8FCLKM Output LVDS frame clock(negative output)

N9FCLKP Output LVDS frame clock(positive output)

A1IN1Input LNA input Channel1

A2IN2Input LNA input Channel2

A3IN3Input LNA input Channel3

A4IN4Input LNA input Channel4

A9IN5Input LNA input Channel5

A8IN6Input LNA input Channel6

A7IN7Input LNA input Channel7

A6IN8Input LNA input Channel8

J3INT/EXT Input Internal/external reference mode select for ADS;internal=high

K9ISET Input Current bias pin for ADS.Requires56k?to ground.

N2LCLKM Output LVDS bit clock(6x);negative output

N1LCLKP Output LVDS bit clock(6x);positive output

R4OUT1M Output LVDS data output(negative),Channel1

P4OUT1P Output LVDS data output(positive),Channel1

R3OUT2M Output LVDS data output(negative),Channel2

P3OUT2P Output LVDS data output(positive),Channel2

R2OUT3M Output LVDS data output(negative),Channel3

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AFE5804

Table1.TERMINAL FUNCTIONS(continued)

PIN NO.PIN NAME FUNCTION DESCRIPTION

P2OUT3P Output LVDS data output(positive),Channel3

R1OUT4M Output LVDS data output(negative),Channel4

P1OUT4P Output LVDS data output(positive),Channel4

R6OUT5M Output LVDS data output(negative),Channel5

P6OUT5P Output LVDS data output(positive),Channel5

R7OUT6M Output LVDS data output(negative),Channel6

P7OUT6P Output LVDS data output(positive),Channel6

R8OUT7M Output LVDS data output(negative),Channel7

P8OUT7P Output LVDS data output(positive),Channel7

R9OUT8M Output LVDS data output(negative),Channel8

P9OUT8P Output LVDS data output(positive),Channel8

J9REFB Input/Output0.5V Negative reference of ADS.Decoupling to ground.Becomes input in external ref mode.

J8REFT Input/Output 2.5V Positive reference of ADS.Decoupling to ground.Becomes input in external ref mode.

H5RST Input RESET input for VCA.Connect to the VCA_CS pin(H4).

H4VCA_CS Output Connect to RST–pin(H5)

F2VB1Output Internal bias voltage.Bypass to ground with2.2μF.

D8VB2Output Internal bias voltage.Bypass to ground with0.1μF.

E3VB3Output Internal bias voltage.Bypass to ground with0.1μF.

E7VB4Output Internal bias voltage.Bypass to ground with0.1μF

F3VB5Output Internal bias voltage.Bypass to ground with0.1μF.

F8VB6Output Internal bias voltage.Bypass to ground with0.1μF.

B1VBL1Input Complementary LNA input Channel1;bypass to ground with0.1μF.

B2VBL2Input Complementary LNA input Channel2;bypass to ground with0.1μF.

B3VBL3Input Complementary LNA input Channel3;bypass to ground with0.1μF.

B4VBL4Input Complementary LNA input Channel4;bypass to ground with0.1μF.

B9VBL5Input Complementary LNA input Channel5;bypass to ground with0.1μF.

B8VBL6Input Complementary LNA input Channel6;bypass to ground with0.1μF.

B7VBL7Input Complementary LNA input Channel7;bypass to ground with0.1μF.

B6VBL8Input Complementary LNA input Channel8;bypass to ground with0.1μF.

A5VCA_PD Input Power-down pin for VCA;low=normal mode,high=power-down mode.

G3VCM Output VCA reference voltage.Bypass to ground with0.1μF.

D2VCNTL Input VCA control voltage input

F7VREFH Output Clamp reference voltage(2.7V).Bypass to ground with0.1μF.

G7VREFL Output Clamp reference voltage(2.0V).Bypass to ground with0.1μF.

B5,H2,H3,K2,

K4,M1,M2,DNC Do not connect

M8,M9

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TIMING CHARACTERISTICS (1)

AFE5804

SBOS442A–JUNE 2008–REVISED SEPTEMBER https://www.doczj.com/doc/8c18987208.html,

LVDS TIMING DIAGRAM

(1)Referenced to ADC Input (internal node)for illustration purposes only.

DEFINITION OF SETUP AND HOLD TIMES

AFE5804

PARAMETER

TEST CONDITIONS

MIN TYP

MAX UNIT t D(A)ADC aperture delay 1.5

4.5

ns Aperture delay variation Channel-to-channel within the same device (3σ)

±20ps t J

Aperture jitter

400f S ,rms Time to valid data after coming out of 50μs COMPLETE POWER-DOWN mode

Time to valid data after coming out of PARTIAL t WAKE

Wake-up time

POWER-DOWN mode (with clock continuing to

2μs run during power-down)Time to valid data after stopping and restarting

40μs the input clock

Clock Data latency

12cycles

(1)

Timing parameters are ensured by design and characterization;not production tested.

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LVDS OUTPUT TIMING CHARACTERISTICS(1)(2) LVDS OUTPUT TIMING CHARACTERISTICS(1)(2)AFE5804

https://www.doczj.com/doc/8c18987208.html,................................................................................................................................................SBOS442A–JUNE2008–REVISED SEPTEMBER2008 Typical values are at+25°C,minimum and maximum values over specified temperature range of T MIN=0°C to T MAX=+85°C,sampling

frequency=as specified,C LOAD=5pF(3),I OUT=3.5mA,R LOAD=100?(4),and no internal termination,unless otherwise noted.

AFE5804

40MSPS50MSPS

PARAMETER TEST CONDITIONS(5)MIN TYP MAX MIN TYP MAX UNIT

t SU Data setup time(6)Data valid(7)to zero-crossing of LCLKP0.670.47ns

Zero-crossing of LCLKP to data becoming

t H Data hold time(6)0.850.65ns

invalid(7)

Input clock(FCLK)rising edge cross-over to

t PROP Clock propagation delay101416.61012.514.1ns

output clock(FCLKP)rising edge cross-over

Duty cycle of differential clock,

LVDS bit clock duty cycle45.55053455053.5

(LCLKP–LCLKM)

Bit clock cycle-to-cycle jitter250250ps,pp

Frame clock cycle-to-cycle jitter150150ps,pp

Rise time is from–100mV to+100mV

t RISE,t FALL Data rise time,data fall time0.090.20.40.090.20.4ns

Fall time is from+100mV to–100mV

t CLKRISE,Output clock rise time,output Rise time is from–100mV to+100mV

0.090.20.40.090.20.4ns

t CLKFALL clock fall time Fall time is from+100mV to–100mV

(1)All characteristics are at the maximum rated speed for each speed grade.

(2)Timing parameters are ensured by design and characterization;not production tested.

(3)C LOAD is the effective external single-ended load capacitance between each output pin and ground.

(4)I OUT refers to the LVDS buffer current setting;R LOAD is the differential load resistance between the LVDS output pair.

(5)Measurements are done with a transmission line of100?characteristic impedance between the device and the load.

(6)Setup and hold time specifications take into account the effect of jitter on the output data and clock.These specifications also assume

that data and clock paths are perfectly matched within the receiver.Any mismatch in these paths within the receiver would appear as

reduced timing margin.

(7)Data valid refers to a logic high of+100mV and a logic low of–100mV.

Typical values are at+25°C,minimum and maximum values over specified temperature range of T MIN=0°C to T MAX=+85°C,sampling

frequency=as specified,C LOAD=5pF(3),I OUT=3.5mA,R LOAD=100?(4),and no internal termination,unless otherwise noted.

AFE5804

30MSPS20MSPS10MSPS

PARAMETER TEST CONDITIONS(5)MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT

Data valid(7)to zero-crossing of

t SU Data setup time(6)0.8 1.5 3.7ns

LCLKP

Zero-crossing of LCLKP to data

t H Data hold time(6) 1.2 1.9 3.9ns

becoming invalid(7)

Input clock(FCLK)rising edge

t PROP Clock propagation delay cross-over to output clock(FCLKP)9.513.517.39.514.517.31014.717.1ns

rising edge cross-over

Duty cycle of differential clock,

LVDS bit clock duty cycle46.55052485051495051

(LCLKP–LCLKM)

Bit clock cycle-to-cycle

250250750ps,pp jitter

Frame clock cycle-to-cycle

150150500ps,pp jitter

t RISE,Data rise time,data fall Rise time is from–100mV to+100mV

0.090.20.40.090.20.40.090.20.4ns

t FALL time Fall time is from+100mV to–100mV

t CLKRISE,Output clock rise time,Rise time is from–100mV to+100mV

0.090.20.40.090.20.40.090.20.4ns

t CLKFALL output clock fall time Fall time is from+100mV to–100mV

(1)All characteristics are at the speeds other than the maximum rated speed for each speed grade.

(2)Timing parameters are ensured by design and characterization;not production tested.

(3)C LOAD is the effective external single-ended load capacitance between each output pin and ground.

(4)I OUT refers to the LVDS buffer current setting;R LOAD is the differential load resistance between the LVDS output pair.

(5)Measurements are done with a transmission line of100?characteristic impedance between the device and the load.

(6)Setup and hold time specifications take into account the effect of jitter on the output data and clock.These specifications also assume

that data and clock paths are perfectly matched within the receiver.Any mismatch in these paths within the receiver would appear as

reduced timing margin.

(7)Data valid refers to a logic high of+100mV and a logic low of–100mV.

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TYPICAL CHARACTERISTICS

4030

20100

-0

0.1 1.2

G a i n (d B )

V (V)

CNTL 0.20.30.40.50.60.70.80.9 1.0 1.1

69121518

------0

N o r m a l i z e d G a

i n (d B )

Frequency (MHz)

69121518

------ 1.0

5.5

30.0

N o r m a l i z e d G a i n (d B )

Frequency (MHz)

10.0

14.5

19.0

23.5

28.0300250

200150

100

5000

0.1 1.2

N o i s e (n V /)

?H z V (V)

CNTL 0.20.3

0.40.50.60.70.80.9 1.0 1.1300250

200150

100

5000

0.1 1.2

N o i s e (n V /)

?H z V (V)

CNTL 0.20.30.4

0.50.60.70.80.9 1.0 1.1350300

2502001501005000

0.1 1.2

N o i s e (n V /)

?H z V (V)CNTL 0.20.30.40.50.6

0.70.80.9 1.0 1.1AFE5804

SBOS442A–JUNE 2008–REVISED SEPTEMBER https://www.doczj.com/doc/8c18987208.html,

AVDD_5V =5.0V,AVDD1=VDD2=DVDD =3.3V,LVDD =1.8V,single-ended input into LNA,ac-coupled with 1.0μF,

V CNTL =1.0V,f IN 5MHz,Clock =40MSPS,50%duty cycle,internal reference mode,ISET =56k ?,LVDS buffer setting =

3.5mA,at ambient temperature T A =+25°C,unless otherwise noted.

GAIN vs V CNTL AT 5MHz

12.5MHz FILTER RESPONSE

Figure 1.

Figure 2.

17MHz FILTER RESPONSE

OUTPUT-REFERRED NOISE vs V CNTL

Figure 3.

Figure 4.

OUTPUT-REFERRED NOISE vs V CNTL

Figure 5.Figure 6.

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400350300

2502001501005000

0.1 1.2

N o i s e (n V /)

?H z V (V)

CNTL 0.20.30.40.50.60.70.80.9 1.0 1.1

300250

200

150100

5000

0.1 1.2

N o i s e (n V /)

?H z V (V)

CNTL 0.20.30.40.50.60.70.80.9 1.0 1.1

300250

200150

100

5000

0.1 1.2

N o i s e (n V /)

?H z V (V)

CNTL 0.20.30.40.50.60.70.80.9 1.0 1.1

200180160

1401201008060402000

0.1 1.2

N o i s e (n V /)

?H z V (V)

CNTL 0.20.30.40.50.60.70.80.9 1.0

1.1200180160

1401201008060402000

0.1 1.2

N o i s e (n V /)

?H z V (V)

CNTL 0.20.30.40.50.60.70.80.9 1.0 1.1

160140120

1008060402000

0.1 1.2

N o i s e (n V /)

?H z V (V)

CNTL 0.20.30.40.50.60.70.80.9 1.0

1.1AFE5804

TYPICAL CHARACTERISTICS (continued)

AVDD_5V =5.0V,AVDD1=VDD2=DVDD =3.3V,LVDD =1.8V,single-ended input into LNA,ac-coupled with 1.0μF,V CNTL =1.0V,f IN 5MHz,Clock =40MSPS,50%duty cycle,internal reference mode,ISET =56k ?,LVDS buffer setting =3.5mA,at ambient temperature T A =+25°C,unless otherwise noted.

OUTPUT-REFERRED NOISE vs V CNTL

Figure 7.

Figure 8.

OUTPUT-REFERRED NOISE vs V CNTL

INPUT-REFERRED NOISE vs V CNTL

Figure 9.

Figure 10.

INPUT-REFERRED NOISE vs V CNTL

Figure 11.Figure 12.

Product Folder Link(s):AFE5804

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160140120

10080604020

0.1 1.2

N o i s e (n V /)

?H z V (V)

CNTL 0.20.30.40.50.60.70.80.9 1.0 1.1

5.04.54.03.53.02.52.01.51.0

0.501

N o i s e F i g u r e (d B )

Frequency (MHz)

65432101

I n p u t -R e f e r r e d N o i s e

(n V /)

?H z Frequency (MHz)

140013001200110010009008007006005004003002001000

N o i s e

(n V /)

?H z Frequency (MHz)

140013001200110010009008007006005004003002001000

110

N o i s e (n V /)

?H z Frequency (MHz)

140013001200110010009008007006005004003002001000

N o i s e (n V

?H z Frequency (MHz)

AFE5804

SBOS442A–JUNE 2008–REVISED SEPTEMBER https://www.doczj.com/doc/8c18987208.html,

TYPICAL CHARACTERISTICS (continued)

AVDD_5V =5.0V,AVDD1=VDD2=DVDD =3.3V,LVDD =1.8V,single-ended input into LNA,ac-coupled with 1.0μF,

V CNTL =1.0V,f IN 5MHz,Clock =40MSPS,50%duty cycle,internal reference mode,ISET =56k ?,LVDS buffer setting =3.5mA,at ambient temperature T A =+25°C,unless otherwise noted.

INPUT-REFERRED NOISE vs V CNTL

NOISE FIGURE vs FREQUENCY AND R S

Figure 13.

Figure 14.

INPUT-REFERRED NOISE vs FREQUENCY AND R S OUTPUT-REFERRED NOISE vs FREQUENCY AND R S

Figure 15.

Figure 16.

OUTPUT-REFERRED NOISE vs FREQUENCY AND R S

Figure 17.Figure 18.

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1.41.2

1.00.8

0.60.40.20

N o i s e (n V /)

?H z Gain Setting (PGA) 1.41.2

1.00.8

0.6

0.40.20

N o i s e (n V /)

?H z Gain Setting (PGA)

1.41.2

1.0

0.80.60.40.2

N o i s e (n V /)

?H z Gain Setting (PGA)

2000180016001400

120010008006004002000

-0.45C h a n n e l

Gain (dB)

0.050.100.2000.150.450.250.350.300.5

0.40-0.05-0.15-0.25-0.35-0.50-0.10-0.20-0.30-0.401800160014001200

10008006004002000

-0.45C h a n n e l

Gain (dB)

0.050.100.2000.150.450.250.350.300.50

0.40-0.05

-0.15-0.25-0.35-0.50-0.10-0.20-0.30-0.402000180016001400

120010008006004002000

-0.45C h a n n e l

Gain (dB)

0.050.100.2000.150.450.250.350.3

00.50

0.40-0.05-0.15-0.25-0.35-0.50-0.10-0.20-0.30-0.40AFE5804

TYPICAL CHARACTERISTICS (continued)

INPUT-REFERRED NOISE vs PGA

Figure 19.

Figure 20.

GAIN MATCH HISTOGRAM

INPUT-REFERRED NOISE vs PGA

(V CNTL =0.1V)

Figure 21.

Figure 22.

GAIN MATCH HISTOGRAM

(V CNTL =0.6V)

(V CNTL =1.0V)

Figure 23.

Figure 24.

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900800

700600

500400300

200100

2012C h a n n e l

Code

201620182022201420202072

20682064206020562052204820442040203620322024202820262070206620622058205420502046204220382034203

02500

2000

1500

1000

500

012.6

C h a n n e l

Transconductance (mA/V)

14.6

14.8

15.2

14.4

15.0

15.4

14.2

13.8

13.4

13.0

12.4

14.0

13.6

13.2

12.

-5560

657075

808590

-------0.6

1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.8

0.9 1.0

1.1

-4550

55606570758085

--------0.6

1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.8

0.9 1.0

1.1

-5560

7580

-----0.6

1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.8

0.9 1.0

1.1

-3540

455055

-----0.6

1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.8

0.9 1.0

1.1

AFE5804

SBOS442A–JUNE 2008–REVISED SEPTEMBER https://www.doczj.com/doc/8c18987208.html,

TYPICAL CHARACTERISTICS (continued)

AVDD_5V =5.0V,AVDD1=VDD2=DVDD =3.3V,LVDD =1.8V,single-ended input into LNA,ac-coupled with 1.0μF,

V CNTL =1.0V,f IN 5MHz,Clock =40MSPS,50%duty cycle,internal reference mode,ISET =56k ?,LVDS buffer setting =3.5mA,at ambient temperature T A =+25°C,unless otherwise noted.

CW ACCURACY HISTOGRAM

OUTPUT OFFSET HISTOGRAM

Figure 25.

Figure 26.

SECOND HARMONIC vs V CNTL AND FREQUENCY

Figure 27.

Figure 28.

THIRD HARMONIC vs V CNTL AND FREQUENCY

Figure 29.

Figure 30.

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-5560

657075808590

-------0.6

1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.8

0.9 1.0

1.1

-4550

55606570758085

--------0.6

1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.80.9 1.0 1.1

-5560

6570

7580

-----0.6

1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.8

0.9 1.0

1.1

-3540

5560

-----0.6 1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.70.80.9 1.0

1.1-5560

7075808590

-------0.6

1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.8

0.9 1.0

1.1

-4550

55606570758085

--------0.6

1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.8

0.9

1.0 1.1

AFE5804

TYPICAL CHARACTERISTICS (continued)

SECOND HARMONIC vs V CNTL AND FREQUENCY

Figure 31.

Figure 32.

THIRD HARMONIC vs V CNTL AND FREQUENCY

Figure 33.

Figure 34.

SECOND HARMONIC vs V CNTL AND FREQUENCY

Figure 35.Figure 36.

Product Folder Link(s):AFE5804

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-5560

7580

-----0.6

1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.8

0.9 1.0

1.1

-35

455055

-----0.6

1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.8

0.9 1.0

1.1

-5560

657075

8590

-------0.6

1.2D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.8

0.9 1.0

1.1

-4550

55606570758085

--------0.6

1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.8

0.9 1.0

1.1

-5560

707580

-----0.6

1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.8

0.9 1.0

1.1

-3540

5560

-----0.6

1.2

D i s t o r t i o n (d B F S )

V (V)

CNTL 0.7

0.8

0.9 1.0

1.1

AFE5804

SBOS442A–JUNE 2008–REVISED SEPTEMBER https://www.doczj.com/doc/8c18987208.html,

TYPICAL CHARACTERISTICS (continued)

AVDD_5V =5.0V,AVDD1=VDD2=DVDD =3.3V,LVDD =1.8V,single-ended input into LNA,ac-coupled with 1.0μF,

V CNTL =1.0V,f IN 5MHz,Clock =40MSPS,50%duty cycle,internal reference mode,ISET =56k ?,LVDS buffer setting =3.5mA,at ambient temperature T A =+25°C,unless otherwise noted.

THIRD HARMONIC vs V CNTL AND FREQUENCY

Figure 37.

Figure 38.

SECOND HARMONIC vs V CNTL AND FREQUENCY

Figure 39.

Figure 40.

THIRD HARMONIC vs V CNTL AND FREQUENCY

Figure 41.Figure 42.

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