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HYS72D128320GBR-5-B中文资料

元器件交易网https://www.doczj.com/doc/8216804610.html,

Edition 2004-04

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

? Infineon Technologies AG 2004.

Attention please!

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Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.

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For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (https://www.doczj.com/doc/8216804610.html,).

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Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

HYS72D32300GBR–[5/6/7]–B HYS72D643[00/20]GBR–[5/6/7]–B HYS72D128320GBR–[5/6/7]–B HYS72D643[00/20]GBR–[5/6/7]–B HYS72D128320GBR–[5/6/7]–B

Revision History:Rev.1.12004-04 Previous Version:Rev. 1.02003-12 Page Subjects (major changes since last revision)

21,22Registerd and PLL current added

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Table of Contents

1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Overview

1.1

Features

?184-Pin Registered 8-Byte Dual-In-Line

DDR SDRAM Module for “1U” PC, Workstation and Server main memory applications ?One rank 32M ×72, 64M × 72 and two ranks 64M × 72, 128M ×72 organization

?JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single +2.5V (±0.2V) power supply and a single +2.6V (±0.1V) power supply for DDR400?Built with 256-Mbit DDR-I SDRAMs in P-TFBGA-60-1 packages

??Auto Refresh (CBR) and Self Refresh ?All inputs and outputs SSTL_2 compatible

?Re-drive for all input signals using register and PLL devices.?Serial Presence Detect with E 2PROM ?

Low Profile Modules form factor:128.95 mm × 28.58 mm × 4.00 mm

133.35 mm × 30.48 mm (1.2”) × 4.00 mm (6.80 mm with stacked components)

?JEDEC standard reference layout for one rank 256MB and 512MB, two ranks 512MB and 1GByte:PC2700 Registered DIMM Raw Cards A,B,C,D ?

Gold plated contacts

1.2Description

The HYS72D[32/64/128]3[00/20]GBR are low profile versions of the standard Registered DIMM modules with less/equal 1.2” inch (30.48 mm) height for 1U Server Applications. The Low Profile DIMM versions are available as 32M × 72 (256MB), 64M × 72 (512MB) and 128M × 72 (1 GB).

The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E 2PROM device using the 2-pin I 2C protocol. The first 128bytes are programmed with configuration data and the second 128bytes are available to the customer.

Table 1

Performance

Part Number Speed Code -5–6-7Unit Speed Grade Component

DDR400B DDR333B DDR266A —Module

PC3200-3033

PC2700–2533PC2100-2033—max. Clock Frequency

@CL3f CK3200166–MHz @CL2.5f CK2.5166166143MHz @CL2

f CK2

133

MHz

Overview

Note:All “product type” end with a place code designating the silicon-die revision. Reference information available

on request. Example: HYS72D64300GR-5-B, indicating rev. C dies are used for SDRAM components. The “compliance code” is printed on the module labels describing the speed sort (for example “PC2700”), the latencies and SPD code definition (for example “20330” means CAS latency of 2.0clocks, RCD 1) latency of 3clocks, Row Precharge latency of 3clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.

Table 2Ordering Information

Type

Compliance Code

Description

SDRAM Technology

PC3200 (CL = 3, t RP = t RCD = 3 at t CK = 5ns)HYS72D32300GBR–5–B PC3200R-30330-A one rank 256MB Registered DIMM

256Mbit (×8)HYS72D64300GBR–5–B PC3200R-30330-C one rank 512MB Registered DIMM

256 Mbit (×4)HYS72D64320GBR–5–B

PC3200R-30330-B

two ranks 512MB Registered DIMM

256Mbit (×8)HYS72D128320GBR–5–B PC3200R-30331-D

two ranks 1 GB Registered DIMM

256Mbit (×4)

PC2700 (CL = 2.5, t RP = t RCD = 3 at t CK = 6ns)HYS72D32300GBR–6–B PC2700R-25330-A one rank 256MB Registered DIMM

256Mbit (×8)HYS72D64300GBR–6–B PC2700R-25330-C one rank 512MB Registered DIMM

256 Mbit (×4)HYS72D64320GBR–6–B

PC2700R-25330-B

two ranks 512MB Registered DIMM

256Mbit (×8)HYS72D128320GBR–6–B PC2700R-25330-D

two ranks 1GB Registered DIMM

256Mbit (×4)

PC2100 (CL = 2, t RP = t RCD = 3 at t CK = 7.5ns)HYS72D32300GBR–7–B PC2100R-20330-A one rank 256MB Registered DIMM

256Mbit (×8)HYS72D64300GBR–7–B PC2100R-20330-C one rank 512MB Registered DIMM

256 Mbit (×4)HYS72D64320GBR–7–B

PC2100R-20330-B

two ranks 512MB Registered DIMM

256Mbit (×8)HYS72D128320GBR–7–B PC2100R-20330-D

two ranks 1GB Registered DIMM

256Mbit (×4)

2Pin Configuration

The pin configuration of the Registered DDR SDRAM DIMM is listed by function in Table3 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table4 and Table5 respectively. The pin numbering is depicted in Figure1.

Table3Pin Configuration of RDIMM

Pin#Name Pin

Type Buffer

Type

Function

Clock Signals

137CK0I SSTL Clock Signal

138CK0I SSTL Complement Clock 21CKE0I SSTL Clock Enable Rank 0 111CKE1I SSTL Clock Enable Rank 1

Note:2-rank module NC NC SSTL Note:1-rank module Control Signals

157S0I SSTL Chip Select of Rank 0 158S1I SSTL Chip Select of Rank 1

Note:2-ranks module NC NC–Note:1-rank module 154RAS I SSTL Row Address Strobe 65CAS I SSTL Column Address

Strobe

63WE I SSTL Write Enable

10RESET I LV-

CMOS Register Reset Forces registered inputs low

Note:For detailed

description of the

Power Up and

Power

Management see

the Application

Note at the end of

data sheet

Address Signals

59BA0I SSTL Bank Address Bus

1:0

52BA1I SSTL

48A0I SSTL Address Bus 11:0 43A1I SSTL

41A2I SSTL

130A3I SSTL

37A4I SSTL 125A6I SSTL Address Bus 11:0

29A7I SSTL

122A8I SSTL

27A9I SSTL

141A10I SSTL

AP I SSTL

118A11I SSTL

115A12I SSTL Address Signal 12

Note:Module based on

256Mbit or larger

dies

NC NC–Note:128Mbit based

module

167A13I SSTL Address Signal 13

Note:1Gbit based

module

NC NC–Note:Module based on

512Mbit or

smaller dies Table3Pin Configuration of RDIMM (cont’d) Pin#Name Pin

Type

Buffer

Type

Function

Data Signals 2DQ0I/O SSTL Data Bus 63:0

4DQ1I/O SSTL 6DQ2I/O SSTL 8DQ3I/O SSTL 94DQ4I/O SSTL 95DQ5I/O SSTL 98DQ6I/O SSTL 99DQ7I/O SSTL 12DQ8I/O SSTL 13DQ9I/O SSTL 19DQ10I/O SSTL 20DQ11I/O SSTL 105DQ12I/O SSTL 106DQ13I/O SSTL 109DQ14I/O SSTL 110DQ15I/O SSTL 23DQ16I/O SSTL 24DQ17I/O SSTL 28DQ18I/O SSTL 31DQ19I/O SSTL 114DQ20I/O SSTL 117DQ21I/O SSTL 121DQ22I/O SSTL 123DQ23I/O SSTL 33DQ24I/O SSTL 35DQ25I/O SSTL 39DQ26I/O SSTL 40DQ27I/O SSTL 126DQ28I/O SSTL 127DQ29I/O SSTL 131DQ30I/O SSTL 133DQ31I/O SSTL 53DQ32I/O SSTL 55DQ33I/O SSTL 57DQ34I/O SSTL 60DQ35I/O SSTL 146DQ36I/O SSTL 147

DQ37

I/O

SSTL

Table 3Pin Configuration of RDIMM (cont’d)Pin#Name Pin Type Buffer Type

Function 150DQ38I/O SSTL Data Bus 63:0

151DQ39I/O SSTL 61DQ40I/O SSTL 64DQ41I/O SSTL 68DQ42I/O SSTL 69DQ43I/O SSTL 153DQ44I/O SSTL 155DQ45I/O SSTL 161DQ46I/O SSTL 162DQ47I/O SSTL 72DQ48I/O SSTL 73DQ49I/O SSTL 79DQ50I/O SSTL 80DQ51I/O SSTL 165DQ52I/O SSTL 166DQ53I/O SSTL 170DQ54I/O SSTL 171DQ55I/O SSTL 83DQ56I/O SSTL 84DQ57I/O SSTL 87DQ58I/O SSTL 88DQ59I/O SSTL 174DQ60I/O SSTL 175DQ61I/O SSTL 178DQ62I/O SSTL 179DQ63I/O SSTL 44CB0I/O SSTL Check Bits 7:045CB1I/O SSTL 49CB2I/O SSTL 51CB3I/O SSTL 134CB4I/O SSTL 135CB5I/O SSTL 142CB6I/O SSTL 144CB7I/O SSTL 5DQS0I/O SSTL Data Strobes 8:0Note:See block

diagram for corresponding DQ signals 14DQS1I/O SSTL 25DQS2I/O SSTL 36DQS3I/O SSTL 56DQS4I/O SSTL Table 3Pin Configuration of RDIMM (cont’d)Pin#Name Pin Type Buffer Type Function

78DQS6I/O SSTL Data Strobes 8:0

86DQS7I/O SSTL 47DQS8I/O SSTL 97

DM0I SSTL Data Mask 0

Note:×8 based module DQS9I/O SSTL Data Strobe 9Note:×4 based module 107

DM1

SSTL Data Mask 1

Note:×8 based module

DQS10I/O SSTL Data Strobe 10Note:×4 based module 119

DM2

SSTL Data Mask 2

Note:×8 based module

DQS11I/O SSTL Data Strobe 11Note:×4 based module 129

DM3

SSTL Data Mask 3

Note:×8 based module

DQS12I/O SSTL Data Strobe 12Note:×4 based module

149

DM4

SSTL Data Mask 4

Note:×8 based module

DQS13I/O SSTL Data Strobe 13Note:×4 based module 159

DM5

SSTL Data Mask 5

Note:×8 based module

DQS14I/O SSTL Data Strobe 14Note:×4 based module 169

DM6

SSTL Data Mask 6

Note:×8 based module

DQS15I/O SSTL Data Strobe 15Note:×4 based module 177

DM7

SSTL Data Mask 7

Note:×8 based module

DQS16I/O SSTL Data Strobe 16Note:×4 based module 140

DM8

SSTL Data Mask 8

Note:×8 based module

DQS17I/O

SSTL

Data Strobe 17Note:×4 based module Table 3Pin Configuration of RDIMM (cont’d)Pin#Name Pin Type Buffer Type Function EEPROM 92SCL I CMOS Serial Bus Clock 91SDA I/O OD

Serial Bus Data

181SA0I CMOS Slave Address Select Bus 2:0182SA1I CMOS 183SA2

CMOS

Power Supplies

1V REF AI –I/O Reference Voltage 184

V DDSPD PWR –

EEPROM Power Supply

15,22,30,54,62,77,96,104,112,128,136,143,156,164,172,180V DDQ PWR –

I/O Driver Power Supply

7,38,46,70,85,108,120,148,168

V DD PWR –Power Supply

Table 3Pin Configuration of RDIMM (cont’d)Pin#Name Pin Type Buffer Type

Function

3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176V

GND–Ground Plane

Other Pins

82V DDID O OD V DD Identification

Note:Pin in tristate,

indicating V DD

and V DDQ nets

connected on

PCB

9, 16, 17, 71, 75, 76, 90, 101, 102, 103, 113, 163, 173NC NC–Not connected

Pins not connected on

Infineon RDIMM’s

Table3Pin Configuration of RDIMM (cont’d)

Pin#Name Pin

Type Buffer

Type

Function

Table4Abbreviations for Pin Type

Abbreviation Description

I Standard input-only pin. Digital levels.

O Output. Digital levels.

I/O I/O is a bidirectional input/output signal.

AI Input. Analog levels.

PWR Power

GND Ground

NU Not Usable (JEDEC Standard)

NC Not Connected (JEDEC Standard)

Table5Abbreviations for Buffer Type

Abbreviation Description

SSTL Serial Stub Terminalted Logic (SSTL2)

LV-CMOS Low Voltage CMOS

CMOS CMOS Levels

OD Open Drain. The corresponding pin has 2

operational states, active low and tristate,

and allows multiple devices to share as a

wire-OR.

Table6Address Format

Density Organization Memory

Ranks SDRAMs# of

SDRAMs

# of

row/bank/

columns

bits

Refresh Period Interval

256 MB32M x 72132M×8913 / 2 / 108K64ms7.8μs 512MB64M×72164M×41813 / 2 / 118K64ms7.8μs 512MB64M×72232M×81813 / 2 / 108K64ms7.8μs 1GB128M×72264M×43613 / 2 / 118K64ms7.8μs

Figure 2

Block Diagram: One Rank 32M ×72 DDR SDRAM DIMM Module (32M ×8 components) HYS72D32300GBR on Raw Card A

PCK PCK

DQ4DQ5DQ6DQ7

DQ0DQ1DQ2DQ3DM D0

DM0/DQS9

DQ12DQ13DQ14DQ8DQ9DQ10DQ11DM D1

DM1/DQS10

DQ20DQ21DQ22DQ23

DQ16DQ17DQ18DQ19DM D2

DM2/DQS11

DQ28DQ29DQ30DQ31

DQ24DQ25DQ26DQ27DM D3

DM3/DQS12

DQ36DQ37DQ38DQ39

DQ32DQ33DQ34DQ35DM D4

DM4/DQS13

DQ44DQ45DQ46DQ47

DQ40DQ41DQ42DQ43DM D5

DM5/DQS14

DQ52DQ53DQ54DQ55

DQ48DQ49DQ50DQ51DM D6

DQ60DQ61DQ62DQ63

DQ56DQ57DQ58DQ59DM D7

DM7/DQS16

RS 0CS CS CS CS CS CS CS CS DQS0

DQS

DQS4

DQS1

DQS5

DQS DQS2

DQS

DQS3

DQS

DM6/DQS15

DQS6

DQS7

DQ15

CB4CB5CB6CB7

CB0CB1CB2CB3DM I/O 7I/O 6I/O 1I/O 0D8

I/O 5I/O 4I/O 3I/O 2

CS DQS8

DM8/DQS17

DQS

DQS DQS DQS

CK0,CK 0 --------- PLL*

* Wire per Clock Loading Table/Wiring Diagrams

CS0RS0 -> CS : SDRAMs D0-D8

BA0-BA1RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8A0-A12RA0-RA12 -> A0-A12: SDRAMs D0 - D8RAS RRAS ->RAS : SDRAMs D0 - D8CAS RCAS ->CAS : SDRAMs D0 - D8CKE0RCKE0 -> CKE: SDRAMs D0 - D8WE

RWE ->WE : SDRAMs D0 - D8

R E G I S T E R

RESET

I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7

Notes:

1. DQ-to-I/O wiring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

3. DQ, DQS, Adress and control resistors: 22 Ohms.

4. VDDID strap connections

STRAP OUT (OPEN): VDD = VDDQ

5. SDRAM placement alternates between the back and front of the DIMM.

V DD,V SS D0 - D8D0 - D8

V DDQ D0 - D8D0 - D8VREF V DDID

Strap: see Note 4

V DDSPD

EEPROM A0

Serial PD

SA0SA1SA2

SCL

SDA

DQ4DQ5DQ6DQ7

DQ0DQ1DQ2DQ3DM D0

DM0/DQS9

DM D9

DQ12DQ13DQ14DQ8DQ9DQ10DQ11DM D1

DM D10

DM1/DQS10

DQ20DQ21DQ22DQ23

DQ16DQ17DQ18DQ19DM D2

DM D11

DM2/DQS11

DQ28DQ29DQ30DQ31

DQ24DQ25DQ26DQ27DM D3

DM D12

DM3/DQS12

DQ36DQ37DQ38DQ39

DQ32DQ33DQ34DQ35DM D4

DM4/DQS13

DM D13

DQ44DQ45DQ46DQ47

DQ40DQ41DQ42DQ43DM D5

DM D14

DM5/DQS14

DQ52DQ53DQ54DQ55

DQ48DQ49DQ50DQ51DM D6

DM D15

DQ60DQ61DQ62DQ63DQ56DQ57DQ58DQ59DM D7

DM D16

DM7/DQS16

RS 0RS 1CS CS CS CS CS CS CS CS CS CS CS CS CS CS CS CS DQS0

DQS

DQS4

DQS1

DQS5

DQS DQS DQS2

DQS

DQS3

DQS

DM6/DQS15

DQS6

DQS7

DQ15

CB4CB5CB6CB7

CB0CB1CB2CB3DM D8

DM D17

CS CS DQS8

DM8/DQS17

DQS

DQS DQS

DQS DQS DQS

DQS

CK0,CK 0 --------- PLL*

* Wire per Clock Loading Table/Wiring Diagrams

CS1

RS1 -> CS : SDRAM D9-D17

BA0-BA1RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17A0-A12RA0-RA12 -> A0-A12: SDRAMs D0 - D17RAS RRAS ->RAS : SDRAMs D0 - D17CS0RS0 -> CS : SDRAM D0-D8CAS RCAS ->CAS : SDRAMs D0 - D17CKE0RCKE0 -> CKE: SDRAMs D0 - D8WE

RWE ->WE : SDRAMs D0 - D17R E G I S T E R

RCKE1 -> CKE: SDRAMs D9 - D17PCK PCK

CKE1RESET

I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7

Serial PD

SA0SA1SA2

SCL

SDA

Notes:

1. DQ-to-I/O wiring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

3. DQ, DQS, Adress and control resistors: 22 Ohms.

4. VDDID strap connections

STRAP OUT (OPEN): VDD = VDDQ

5. SDRAM placement alternates between the back and front of the DIMM.

V DD,V SS V DDQ VREF V DDID

Strap: see Note 4

V DDSPD EEPROM

D0 - D17D0 - D17

D0 - D17

RS 0A DQS4

DQS6

DQS2

DQ0DQ1DQ2DQ3

DQ8DQ9DQ10DQ11

DQ16DQ17DQ18DQ19

DQ24DQ25DQ26DQ27

DQ32DQ33DQ34DQ35

DQ40DQ41DQ42DQ43

DQ56DQ57DQ58DQ59

DQS

DQS DQS DQS DQS DQS

DQS DQS0

DQ48DQ49DQ50DQ51

DQS D6

DQ4DQ5DQ6DQ7

DQ12DQ13DQ14DQ15

DQ20DQ21DQ22DQ23

DQ28DQ29DQ30DQ31

DQ36DQ37DQ38DQ39

DQ44DQ45DQ46DQ47

DQ60DQ61DQ62DQ63

DQS D9

DQS I/O 0I/O 1I/O 2I/O 3DQS I/O 0I/O 1I/O 2I/O 3DQS I/O 0I/O 1I/O 2I/O 3

DQS I/O 0I/O 1I/O 2I/O 3

DQS I/O 0I/O 1I/O 2I/O 3DQS I/O 0I/O 1I/O 2I/O 3DM0/DQS9

D10

D11

D12

D13

D14

D16

DQ52DQ53DQ54DQ55

DQS

I/O 0I/O 1I/O 2I/O 3D15CB0CB1CB2CB3

DQS

CB4CB5CB6CB7

DQS I/O 0I/O 1I/O 2I/O 3

D17

CS CS CS CS CS CS CS CS CS CS CS CS CS CS CS CS CS CS VSS DQS1

DQS3

DQS8

DQS5

DQS7

DM6/DQS15

DM5/DQS14

DM4/DQS13

DM1/DQS10

DM2/DQS11

DM3/DQS12

DM7/DQS16

DM8/DQS17

RS 0B CK0,CK 0 --------- PLL*

* Wire per Clock Loading Table/Wiring Diagrams BA0-BA1RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17

A0-A11,A12RA0-RA11,RA12 -> A0-A11,A12: SDRAMs D0 - D17RAS RRAS ->RAS : SDRAMs D0 - D17CS0CAS RCAS ->CAS : SDRAMs D0 - D17CKE0RCKE0A -> CKE: SDRAMs D0 - D8WE

RWE ->WE : SDRAMs D0 - D17

R E G I S T E R

RCKEB -> CKE: SDRAMs D9 - D17

PCK

PCK RESET

I/O 0I/O 1I/O 2I/O 3

I/O 0I/O 1I/O 2I/O 3I/O 0I/O 1I/O 2I/O 3I/O 0I/O 1I/O 2I/O 3I/O 0I/O 1I/O 2I/O 3

I/O 0I/O 1I/O 2I/O 3I/O 0I/O 1I/O 2I/O 3I/O 0I/O 1I/O 2I/O 3I/O 0I/O 1I/O 2I/O 3I/O 0I/O 1I/O 2I/O 3

Serial PD

SA0SA1SA2

SCL

SDA

Notes:

1. DQ-to-I/O wiring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

3. DQ, DQS, Adress and control resistors: 22 Ohms.

4. VDDID strap connections

STRAP OUT (OPEN): VDD = VDDQ

5. SDRAM placement alternates between the back and front of the DIMM.

V DD,V SS

V DDQ VREF V DDID

Strap: see Note 4

V DDSPD

EEPROM

D0 - D17D0 - D17

D0 - D17RS 0 -> CS : SDRAMs D0-D17

Electrical Characteristics

3.1

Operating Conditions

Attention:Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This

is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit.Table 7Absolute Maximum Ratings

Parameter

Symbol

Values Unit Note/ Test

Condition min.

typ.max.

Voltage on I/O pins relative to V SS V IN , V OUT –0.5–V DDQ +

0.5V –Voltage on inputs relative to V SS V IN –0.5–+3.6V –Voltage on V DD supply relative to V SS V DD –0.5–+3.6V –Voltage on V DDQ supply relative to V SS V DDQ –0.5–+3.6V –Operating temperature (ambient)T A 0–+70°C –Storage temperature (plastic)

T STG -55–+150°C –Power dissipation (per SDRAM component)P D – 2.0–W –Short circuit output current

I OUT

–

Table 8Electrical Characteristics and DC Operating Conditions

Parameter

Symbol

Values Unit Note/Test Condition 1)

Min.

Typ.Max.Device Supply Voltage V DD

2.3 2.5 2.7V f CK ≤166MHz Device Supply Voltage

V DD

2.5 2.6 2.7V f CK >166MHz 2)Output Supply Voltage V DDQ 2.3 2.5 2.7V f CK ≤166MHz 3)Output Supply Voltage V DDQ 2.5 2.6 2.7V f CK >166MHz 2)3)

EEPROM supply voltage V DDSPD 2.3 2.5

3.6V —Supply Voltage, I/O Supply Voltage V SS , V SSQ 0

—

Input Reference Voltage V REF 0.49 × V DDQ 0.5 × V DDQ 0.51 × V DDQ V

4)I/O Termination Voltage (System)

V TT

V REF – 0.04V REF + 0.04V 5)

Input High (Logic1) Voltage V IH(DC)V REF + 0.15

V DDQ + 0.3V 8)Input Low (Logic0) Voltage V IL(DC)–0.3V REF – 0.15V 8)Input Voltage Level, CK and CK Inputs V IN(DC)–0.3V DDQ + 0.3V 8)

Input Differential Voltage, CK and CK Inputs V ID(DC)

0.36V DDQ + 0.6

V 8)6)

VI-Matching Pull-up Current to Pull-down Current

VI Ratio

0.71

1.4

—

Electrical Characteristics

Input Leakage Current

I I –2

μA

Any input 0V ≤V IN ≤V DD ; All other pins not under test =0V 8)9)

Output Leakage Current I OZ –55μA DQs are disabled; 0V ≤ V OUT ≤ V DDQ

Output High Current, Normal Strength Driver I OH —–16.2mA V OUT = 1.95 V Output Low

Current,Normal Strength Driver

I OL

16.2

—

V OUT = 0.35 V

1)0 °C ≤ T A ≤ 70 °C

2)DDR400 conditions apply for all clock frequencies above 166MHz 3)Under all conditions, V DDQ must be less than or equal to V DD .

4)Peak to peak AC noise on V REF may not exceed ±2% V REF (DC). V REF is also expected to track noise variations in V DDQ .5)V TT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal

to V REF , and must track variations in the DC level of V REF .6)V ID is the magnitude of the difference between the input level on CK and the input level on CK.

7)The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire

temperature and voltage range, for device drain to source voltage from 0.25 to 1.0V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation.8)Inputs are not recognized as valid until V REF stabilizes.9)Values are shown per DDR SDRAM component

Table 8Electrical Characteristics and DC Operating Conditions (cont’d)

Parameter

Symbol

Values Unit Note/Test Condition 1)

Min.

Typ.

Max.

Electrical Characteristics

Table 9

I DD Specifications

P r o d u c t T y p e & O r g a n i s a t i o n

H Y S 72D 32300G B R -5-B

H Y S 72D 64300G B R -5-B

H Y S 72D 64320G B R -5-B

H Y S 72D 128320G B R -5-B

Unit

Note/ Test Conditions 5)

256 MB ×721 Rank –5512 MB ×721 Rank –5512 MB ×72

2 Ranks –5 1 GByte ×72

2 Ranks –5typ.

max.typ.max.typ.max.typ.max.I DD0 1690 1960 2500 3040 2284 2599 3688 4318mA 1)4)1)The module I DD values are calculated from the component I DD datasheet values are:

n *I DD ×[component] for single bank modules (n: number of components per module bank)

n *I DD ×[component]+n *I DD3N [component] for two bank modules (n: number of components per module bank)I DD1 1825 2005 2770 3130 2419 2644 3958 4408mA 1)3)4)I DD2P 698 725 752 806 752 806 860 968mA 2)4)2)The module I DD values are calculated from the component I DD datasheet values are:

n *I DD ×[component] for single bank modules (n: number of components per module bank)

2*n *I DD ×[component] for single two bank modules (n: number of components per module bank)

I DD2F 1076 1139 1508 1634 1508 1634 2372 2624mA 2)4)I DD2Q 878 932 1112 1220 1112 1220 1580 1796mA 2)4)I DD3P 815 869 986 1094 986 1094 1328 1544mA 2)4)I DD3N 1238 1319 1832 1994 1832 1994 3020 3344mA 2)4)I DD4R 2005 2185 3130 3490 2599 2824 4318 4768mA 1)3)4)3)DQ I/O (I DDQ ) currents are not included into calculations: module I DD values will be measured differently depending on load

conditions I DD4W 2005 2194 3130 3508 2599 2833 4318 4786mA 1)4)I DD5 2320 2635 3760 4390 2914 3274 4948 5668mA 1)4)4)Module I DD is calculated on the basis of component I DD and includes Register and PLL I DD6 656.6 671 669.2 698 669.2 698 694.4 752mA 2)4)I DD7

3040

3310

5200

5740

3634

3949

6388

7018

1)3)4)5)

5)Test condition for maximum values: V DD =2.7V, T A =10°C