DGND
AGND
ADS1278
DGND
AGND
ADS1274
ADS1274
ADS1278
https://www.doczj.com/doc/8d14435343.html, SBAS367F–JUNE2007–REVISED FEBRUARY2011 Quad/Octal,Simultaneous Sampling,24-Bit Analog-to-Digital Converters
Check for Samples:ADS1274,ADS1278
FEATURES DESCRIPTION
?Simultaneously Measure Four/Eight Channels Based on the single-channel ADS1271,the ADS1274
(quad)and ADS1278(octal)are24-bit,delta-sigma ?Up to144kSPS Data Rate
(ΔΣ)analog-to-digital converters(ADCs)with data ?AC Performance:
rates up to144k samples per second(SPS),allowing 70kHz Bandwidth
simultaneous sampling of four or eight channels.The 111dB SNR(High-Resolution Mode)devices are offered in identical packages,permitting –108dB THD drop-in expandability.
?DC Accuracy:
Traditionally,industrial delta-sigma ADCs offering
0.8μV/°C Offset Drift
good drift performance use digital filters with large
1.3ppm/°C Gain Drift passband droop.As a result,they have limited signal ?Selectable Operating Modes:bandwidth and are mostly suited for dc High-Speed:144kSPS,106dB SNR measurements.High-resolution ADCs in audio
applications offer larger usable bandwidths,but the High-Resolution:52kSPS,111dB SNR
offset and drift specifications are significantly weaker Low-Power:52kSPS,31mW/ch
than respective industrial counterparts.The ADS1274 Low-Speed:10kSPS,7mW/ch
and ADS1278combine these types of converters,?Linear Phase Digital Filter allowing high-precision industrial measurement with
?SPI?or Frame-Sync Serial Interface excellent dc and ac specifications.
?Low Sampling Aperture Error The high-order,chopper-stabilized modulator ?Modulator Output Option(digital filter bypass)achieves very low drift with low in-band noise.The
onboard decimation filter suppresses modulator and ?Analog Supply:5V
signal out-of-band noise.These ADCs provide a ?Digital Core:1.8V usable signal bandwidth up to90%of the Nyquist
?I/O Supply:1.8V to3.3V rate with less than0.005dB of ripple.
Four operating modes allow for optimization of speed, APPLICATIONS
resolution,and power.All operations are controlled ?Vibration/Modal Analysis directly by pins;there are no registers to program.?Multi-Channel Data Acquisition The devices are fully specified over the extended
industrial range(–40°C to+105°C)and are available ?Acoustics/Dynamic Strain Gauges
in an HTQFP-64PowerPAD?package.
?Pressure Sensors
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments,Inc.
SPI is a trademark of Motorola,Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.?2007–2011,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas
Instruments standard warranty.Production processing does not
necessarily include testing of all parameters.
ADS1274
ADS1278
SBAS367F–JUNE2007–REVISED https://www.doczj.com/doc/8d14435343.html, This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information,see the Package Option Addendum at the end of this document,or visit the device product folder at https://www.doczj.com/doc/8d14435343.html,.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted(1)
ADS1274,ADS1278UNIT AVDD to AGND–0.3to+6.0V DVDD,IOVDD to DGND–0.3to+3.6V
AGND to DGND–0.3to+0.3V
Momentary100mA
Input current
Continuous10mA Analog input to AGND–0.3to AVDD+0.3V
Digital input or output to DGND–0.3to IOVDD+0.3V Maximum junction temperature+150°C
ADS1274–40to+125°C Operating temperature range
ADS1278–40to+105°C Storage temperature range–60to+150°C
(1)Stresses above these ratings may cause permanent damage.Exposure to absolute maximum conditions for extended periods may
degrade device reliability.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those specified is not implied.
2Submit Documentation Feedback?2007–2011,Texas Instruments Incorporated
Product Folder Link(s):ADS1274ADS1278
ADS1274
ADS1278 https://www.doczj.com/doc/8d14435343.html, SBAS367F–JUNE2007–REVISED FEBRUARY2011 ELECTRICAL CHARACTERISTICS
All specifications at T A=–40°C to+105°C,AVDD=+5V,DVDD=+1.8V,IOVDD=+3.3V,f CLK=27MHz,VREFP=2.5V, VREFN=0V,and all channels active,unless otherwise noted.
ADS1274,ADS1278
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS
Full-scale input voltage(FSR(1))V IN=(AINP–AINN)±V REF V Absolute input voltage AINP or AINN to AGND AGND–0.1AVDD+0.1V Common-mode input voltage(V CM)V CM=(AINP+AINN)/2 2.5V
High-Speed mode14k?
High-Resolution mode14k?Differential input impedance
Low-Power mode28k?
Low-Speed mode140k?
DC PERFORMANCE
Resolution No missing codes24Bits
f CLK=37MHz144,531SPS(3)
High-Speed mode(2)f CLK=32.768MHz128,000SPS
f CLK=27MHz105,469SPS Data rate(f DATA)
High-Resolution mode52,734SPS
Low-Power mode52,734SPS
Low-Speed mode10,547SPS Integral nonlinearity(INL)(4)Differential input,V CM=2.5V±0.0003±0.0012%FSR(1) Offset error0.252mV Offset drift0.8μV/°C Gain error0.10.5%FSR Gain drift 1.3ppm/°C High-Speed mode Shorted input8.516μV,rms
High-Resolution mode Shorted input 5.512μV,rms Noise
Low-Power mode Shorted input8.516μV,rms
Low-Speed mode Shorted input8.016μV,rms Common-mode rejection f CM=60Hz90108dB
AVDD80dB Power-supply rejection DVDD f PS=60Hz85dB
IOVDD105dB
V COM output voltage No load AVDD/2V
(1)FSR=full-scale range=2V REF.
(2)f CLK=37MHz max for High-Speed mode,and27MHz max for all other modes.See Table7for f CLK restrictions in High-Speed mode.
(3)SPS=samples per second.
(4)Best fit method.
?2007–2011,Texas Instruments Incorporated Submit Documentation Feedback3
Product Folder Link(s):ADS1274ADS1278
ADS1274
ADS1278
SBAS367F–JUNE2007–REVISED https://www.doczj.com/doc/8d14435343.html, ELECTRICAL CHARACTERISTICS(continued)
All specifications at T A=–40°C to+105°C,AVDD=+5V,DVDD=+1.8V,IOVDD=+3.3V,f CLK=27MHz,VREFP=2.5V, VREFN=0V,and all channels active,unless otherwise noted.
ADS1274,ADS1278
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
Crosstalk f=1kHz,–0.5dBFS(5)–107dB
High-Speed mode101106dB
V REF=2.5V103110dB
High-Resolution mode
Signal-to-noise ratio(SNR)(6)
V REF=3V111dB (unweighted)
Low-Power mode101106dB
Low-Speed mode101107dB
Total harmonic distortion(THD)(7)V IN=1kHz,–0.5dBFS–108–96dB Spurious-free dynamic range109dB Passband ripple±0.005dB Passband0.453f DATA Hz
–3dB Bandwidth0.49f DATA Hz
High-Resolution mode95dB
Stop band attenuation
All other modes100
High-Resolution mode0.547f DATA127.453f DATA Hz
Stop band
All other modes0.547f DATA63.453f DATA Hz
High-Resolution mode39/f DATA s Group delay
All other modes38/f DATA s
High-Resolution mode Complete settling78/f DATA s Settling time(latency)
All other modes Complete settling76/f DATA s VOLTAGE REFERENCE INPUTS
Negative reference input(VREFN)AGND–0.1AGND+0.1V
0.1≤f CLK≤27MHz0.5 2.5 3.1V
Reference input voltage(V REF)(8)
27 (V REF=VREFP–VREFN) 32.768MHz High-Speed mode 1.3k? High-Resolution mode 1.3k? ADS1274 Reference Input impedance Low-Power mode 2.6k? Low-Speed mode13k? High-Speed mode0.65k? High-Resolution mode0.65k? ADS1278 Reference Input impedance Low-Power mode 1.3k? Low-Speed mode 6.5k?DIGITAL INPUT/OUTPUT(IOVDD=1.8V to3.6V) V IH0.7IOVDD IOVDD V V IL DGND0.3IOVDD V V OH I OH=4mA0.8IOVDD IOVDD V V OL I OL=4mA DGND0.2IOVDD V Input leakage0 High-Speed mode(8)0.137MHz Master clock rate(f CLK) Other modes0.127MHz (5)Worst-case channel crosstalk between one or more channels. (6)Minimum SNR is ensured by the limit of the DC noise specification. (7)THD includes the first nine harmonics of the input signal;Low-Speed mode includes the first five harmonics. (8)f CLK=37MHz max for High-Speed mode,and27MHz max for all other modes.See Table7for V REF restrictions in High-Speed mode. 4Submit Documentation Feedback?2007–2011,Texas Instruments Incorporated Product Folder Link(s):ADS1274ADS1278 ADS1274 ADS1278 https://www.doczj.com/doc/8d14435343.html, SBAS367F–JUNE2007–REVISED FEBRUARY2011 ELECTRICAL CHARACTERISTICS(continued) All specifications at T A=–40°C to+105°C,AVDD=+5V,DVDD=+1.8V,IOVDD=+3.3V,f CLK=27MHz,VREFP=2.5V, VREFN=0V,and all channels active,unless otherwise noted. ADS1274,ADS1278 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY AVDD 4.755 5.25V 0.1≤f CLK≤32.768MHz 1.65 1.8 1.95V DVDD(9) 32.768MHz AVDD110μA Power-down current DVDD115μA IOVDD110μA ADS1274 High-Speed mode5075mA High-Resolution mode5075mA ADS1274 AVDD current Low-Power mode2335mA Low-Speed mode59mA High-Speed mode1824mA High-Resolution mode1217mA ADS1274 DVDD current Low-Power mode1015mA Low-Speed mode 2.5 4.5mA High-Speed mode0.150.5mA High-Resolution mode0.0750.3mA ADS1274 IOVDD current Low-Power mode0.0750.3mA Low-Speed mode0.020.15mA High-Speed mode285420mW High-Resolution mode275410mW ADS1274 Power dissipation Low-Power mode135210mW Low-Speed mode3055mW ADS1278 High-Speed mode97145mA High-Resolution mode97145mA ADS1278 AVDD current Low-Power mode4464mA Low-Speed mode914mA High-Speed mode2330mA High-Resolution mode1620mA ADS1278 DVDD current Low-Power mode1217mA Low-Speed mode 2.5 4.5mA High-Speed mode0.251mA High-Resolution mode0.1250.5mA ADS1278 IOVDD current Low-Power mode0.1250.5mA Low-Speed mode0.0350.2mA High-Speed mode530785mW High-Resolution mode515765mW ADS1278 Power dissipation Low-Power mode245355mW Low-Speed mode5080mW (9)f CLK=37MHz max for High-Speed mode,and27MHz max for all other modes.See Table7for DVDD restrictions in High-Speed mode. ?2007–2011,Texas Instruments Incorporated Submit Documentation Feedback5 Product Folder Link(s):ADS1274ADS1278 AINN7(1)AINP7(1)AINN8(1)AINP8(1)AVDD AGND PWDN1PWDN2PWDN3PWDN4PWDN5(1)PWDN6(1)PWDN7(1)PWDN8(1)MODE0MODE1 AINP2AINN2AINP1AINN1AVDD AGND DGND TEST0TEST1CLKDIV SYNC DIN DOUT8(1)DOUT7(1)DOUT6(1)DOUT5(1) A I N N 3 A I N P 3 A I N N 4A I N P 4 A V D D A G N D V R E F N V R E F P V C O M A G N D A V D D A I N P 5(1) A I N N 6(1)A I N P 6(1)A I N N 5(1) D O U T 4 D O U T 3 D O U T 2 D O U T 1 D G N D I O V D D I O V D D D G N D D G N D D V D D C L K S C L K D R D Y /F S Y N C F O R M A T 2 F O R M A T 1 F O R M A T 0 ADS1274/ADS1278 A G N D 12345678910111213141516 48474645444342 414039383736353433 17 18 19 20 21 22 23 24 25 26 27 28 29 30 3132 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (PowerPAD Outline) ADS1274ADS1278 SBAS367F –JUNE 2007–REVISED FEBRUARY 2011 https://www.doczj.com/doc/8d14435343.html, ADS1274/ADS1278PIN ASSIGNMENTS PAP PACKAGE HTQFP-64(TOP VIEW) (1)Boldface pin names indicate additional pins for the ADS1278;see Table 1. Table 1.ADS1274/ADS1278PIN DESCRIPTIONS PIN NAME NO.FUNCTION DESCRIPTION 6,43,54,AGND Analog ground Analog ground;connect to DGND using a single plane. 58,59 AINP13Analog input AINP21Analog input AINP363Analog input ADS1278: AINP[8:1]Positive analog input,channels 8through 1. AINP461Analog input AINP551Analog input ADS1274: AINP[8:5]Connected to internal ESD rails.The inputs may float.AINP[4:1]Positive analog input,channels 4through 1. AINP649Analog input AINP747Analog input AINP8 45 Analog input 6Submit Documentation Feedback ?2007–2011,Texas Instruments Incorporated Product Folder Link(s):ADS1274ADS1278 ADS1274 ADS1278 https://www.doczj.com/doc/8d14435343.html, SBAS367F–JUNE2007–REVISED FEBRUARY2011 Table1.ADS1274/ADS1278PIN DESCRIPTIONS(continued) PIN NAME NO.FUNCTION DESCRIPTION AINN14Analog input AINN22Analog input AINN364Analog input ADS1278:AINN[8:1]Negative analog input,channels8through1. AINN462Analog input AINN552Analog input ADS1274:AINN[8:5]Connected to internal ESD rails.The inputs may float. AINN[4:1]Negative analog input,channels4through1. AINN650Analog input AINN748Analog input AINN846Analog input AVDD5,44,53,60Analog power supply Analog power supply(4.75V to5.25V). VCOM55Analog output AVDD/2Unbuffered voltage output. VREFN57Analog input Negative reference input. VREFP56Analog input Positive reference input. CLK27Digital input Master clock input(f CLK). CLK input divider control:1=37MHz(High-Speed mode)/otherwise27MHz CLKDIV10Digital input 0=13.5MHz(low-power)/5.4MHz(low-speed) DGND7,21,24,25Digital ground Digital ground power supply. DIN12Digital input Daisy-chain data input. DOUT120Digital output DOUT1is TDM data output(TDM mode). DOUT219Digital output DOUT318Digital output ADS1278:DOUT[8:1]Data output for channels8through1. DOUT417Digital output DOUT516Digital output ADS1274:DOUT[8:5]Internally connected to active circuitry;outputs are driven. DOUT615Digital output DOUT[4:1]Data output for channels4through1. DOUT714Digital output DOUT813Digital output DRDY/ 29Digital input/output Frame-Sync protocol:frame clock input;SPI protocol:data ready output. FSYNC DVDD26Digital power supply Digital core power supply. FORMAT032Digital input FORMAT[2:0]Selects Frame-Sync/SPI protocol,TDM/discrete data outputs, FORMAT131Digital input fixed/dynamic position TDM data,and modulator mode/normal operating mode. FORMAT230Digital input IOVDD22,23Digital power supply I/O power supply(+1.65V to+3.6V). MODE034Digital input MODE[1:0]Selects High-Speed,High-Resolution,Low-Power,or Low-Speed mode operation. MODE133Digital input PWDN142Digital input PWDN241Digital input PWDN340Digital input ADS1278:PWDN[8:1]Power-down control for channels8through1. PWDN439Digital input PWDN538Digital input ADS1274:PWDN[8:5]must=0V. PWDN[4:1]Power-down control for channels4through1. PWDN637Digital input PWDN736Digital input PWDN835Digital input SCLK28Digital input/output Serial clock input,Modulator clock output. SYNC11Digital input Synchronize input(all channels). TEST08Digital input TEST[1:0]Test mode select:01=Do not use 00=Normal operation 10=Do not use 11=Test mode TEST19Digital input ?2007–2011,Texas Instruments Incorporated Submit Documentation Feedback7 Product Folder Link(s):ADS1274ADS1278 ADS1274ADS1278 SBAS367F –JUNE 2007–REVISED FEBRUARY 2011 https://www.doczj.com/doc/8d14435343.html, SPI FORMAT TIMING SPI FORMAT TIMING SPECIFICATION For T A =–40°C to +105°C,IOVDD =1.65V to 3.6V,and DVDD =1.65V to 1.95V,unless otherwise noted. SYMBOL PARAMETER MIN TYP MAX UNIT t CLK CLK period (1/f CLK )(1) 3710,000ns t CPW CLK positive or negative pulse width 15ns t CONV Conversion period (1/f DATA )(2) 256 2560 t CLK t CD (3)Falling edge of CLK to falling edge of DRDY 22 ns t DS (3)Falling edge of DRDY to rising edge of first SCLK to retrieve data 1 t CLK t MSBPD DRDY falling edge to DOUT MSB valid (propagation delay)16 ns t SD (3)Falling edge of SCLK to rising edge of DRDY 18 ns t SCLK (4) SCLK period 1t CLK t SPW SCLK positive or negative pulse width 0.4t CLK t DOHD (3)(5) SCLK falling edge to new DOUT invalid (hold time)10 ns 32ns t DOPD (3)SCLK falling edge to new DOUT valid (propagation delay)26 ns (6)t DIST New DIN valid to falling edge of SCLK (setup time)6ns t DIHD (5)Old DIN valid to falling edge of SCLK (hold time) 6 ns (1)f CLK =27MHz maximum. (2)Depends on MODE[1:0]and CLKDIV selection.See Table 8(f CLK /f DATA ).(3)Load on DRDY and DOUT =20pF. (4)For best performance,limit f SCLK /f CLK to ratios of 1,1/2,1/4,1/8,etc. (5)t DOHD (DOUT hold time)and t DIHD (DIN hold time)are specified under opposite worst-case conditions (digital supply voltage and ambient temperature).Under equal conditions,with DOUT connected directly to DIN,the timing margin is >4ns.(6) DOUT1,TDM mode,IOVDD =3.15V to 3.45V,and DVDD =1.7V to 1.9V. 8Submit Documentation Feedback ?2007–2011,Texas Instruments Incorporated Product Folder Link(s):ADS1274ADS1278 ADS1274ADS1278 https://www.doczj.com/doc/8d14435343.html, SBAS367F –JUNE 2007–REVISED FEBRUARY 2011 FRAME-SYNC FORMAT TIMING FRAME-SYNC FORMAT TIMING SPECIFICATION For T A =–40°C to +105°C,IOVDD =1.65V to 3.6V,and DVDD =1.65V to 2.2V,unless otherwise noted. SYMBOL PARAMETER MIN TYP MAX UNIT High-Speed mode 2710,000ns t CLK CLK period (1/f CLK )(see Table 7)Other modes 3710,000ns t CPW CLK positive or negative pulse width 11ns t CS Falling edge of CLK to falling edge of SCLK –0.250.25t CLK t FRAME Frame period (1/f DATA )(1) 2562560 t CLK t FPW FSYNC positive or negative pulse width 1t SCLK t FS Rising edge of FSYNC to rising edge of SCLK 5ns t SF Rising edge of SCLK to rising edge of FSYNC 5ns t SCLK SCLK period (2) 1t CLK t SPW SCLK positive or negative pulse width 0.4t CLK t DOHD (3)(4)SCLK falling edge to old DOUT invalid (hold time)10 ns 31ns t DOPD (4) SCLK falling edge to new DOUT valid (propagation delay) 21ns (5)25ns (6)31 ns t MSBPD FSYNC rising edge to DOUT MSB valid (propagation delay)21ns (5)25 ns (6)t DIST New DIN valid to falling edge of SCLK (setup time)6ns t DIHD (3) Old DIN valid to falling edge of SCLK (hold time) 6 ns (1)Depends on MODE[1:0]and CLKDIV selection.See Table 8(f CLK /f DATA ). (2)SCLK must be continuously running and limited to ratios of 1,1/2,1/4,and 1/8of f CLK . (3)t DOHD (DOUT hold time)and t DIHD (DIN hold time)are specified under opposite worst-case conditions (digital supply voltage and ambient temperature).Under equal conditions,with DOUT connected directly to DIN,the timing margin is >4ns.(4)Load on DOUT =20pF. (5)DOUT1,TDM mode,IOVDD =3.15V to 3.45V,and DVDD =2V to 2.2V.(6) DOUT1,TDM mode,IOVDD =3.15V to 3.45V,and DVDD =1.7V to 1.9V. ?2007–2011,Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s):ADS1274ADS1278 10 100 1k Frequency (Hz) 0-20-40 -60-80-100-120-140-160 A m p l i t u d e (d B ) 10k 100k High-Speed Mode f = 1kHz,0.5dBFS -IN 32,768 Points 10 100 1k Frequency (Hz) 0-20-40 -60-80-100-120-140-160 A m p l i t u d e (d B ) 10k 100k High-Speed Mode f = 1kHz,20dBFS -IN 32,768 Points 110 1001k Frequency (Hz) 0-20-40 -60-80-100-120-140-160 -180 A m p l i t u d e (d B ) 10k 100k High-Speed Mode Shorted Input 262,144 Points -3 -2-2-1-1223Output (V) m 25k 20k 15k 10k 5k N u m b e r o f O c c u r r e n c e s 10 100 1k Frequency (Hz) 0-20-40 -60-80-100-120-140-160 A m p l i t u d e (d B ) 10k 100k High-Resolution Mode f = 1kHz,0.5dBFS -IN 32,768 Points 10 100 1k Frequency (Hz) 0-20-40 -60-80-100-120-140-160 A m p l i t u d e (d B ) 10k 100k High-Resolution Mode f = 1kHz,20dBFS -IN 32,768 Points ADS1274ADS1278 SBAS367F –JUNE 2007–REVISED FEBRUARY 2011 https://www.doczj.com/doc/8d14435343.html, TYPICAL CHARACTERISTICS At T A =+25°C,High-Speed mode,AVDD =+5V,DVDD =+1.8V,IOVDD =+3.3V,f CLK =27MHz,VREFP =2.5V,and VREFN =0V,unless otherwise noted. OUTPUT SPECTRUM OUTPUT SPECTRUM Figure 1.Figure 2.OUTPUT SPECTRUM NOISE HISTOGRAM Figure 3.Figure 4.OUTPUT SPECTRUM OUTPUT SPECTRUM Figure 5.Figure 6. 10Submit Documentation Feedback ?2007–2011,Texas Instruments Incorporated Product Folder Link(s):ADS1274ADS1278 分销商库存信息: TI ADS1274IPAPT ADS1278IPAPT ADS1274IPAPR ADS1274IPAPRG4ADS1274IPAPTG4ADS1278IPAPR ADS1278IPAPRG4ADS1278IPAPTG4
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