General Description
The MAX3799 is a highly integrated limiting amplifier and VCSEL driver that operates up to 14Gbps, making it suitable for Ethernet and Fibre Channel applications.By providing a selectable data path with a noise-shap-ing filter, the MAX3799 enables a module with 10G optics to be fully compliant with both 1000BASE-SR and 10GBASE-SR specifications. Operating from a sin-gle +3.3V supply, this low-power integrated limiting amplifier and VCSEL driver IC enables a platform design for SFP MSA as well as for SFP+ MSA-based optical transceivers. The high-sensitivity limiting ampli-fier limits the differential input signal generated by a transimpedance amplifier into a CML-level differential output signal. The compact VCSEL driver provides a modulation and a bias current for a VCSEL diode. The optical average power is controlled by an average power control (APC) loop implemented by a controller that interfaces to the VCSEL driver through a 3-wire digital interface. All differential I/Os are optimally back-terminated for a 50Ωtransmission line PCB design.The use of a 3-wire digital interface reduces the pin count while enabling advanced Rx (rate selection, LOS threshold, LOS squelch, LOS polarity, CML output level,signal path polarity, deemphasis, and fast mode-select change time) and Tx settings (modulation current, bias current, polarity, and eye safety control) without the need for external components. The MAX3799 provides multiple current and voltage DACs to allow the use of low-cost controller ICs.
The MAX3799 is packaged in a lead-free, 5mm x 5mm,32-pin TQFN package.
Applications
1000BASE-SR/10G BASE-SR Multirate SFP+Optical Transceiver
1x/2x/4x/8x/16x SFF/SFP/SFP+ MSA Fibre Channel (FC) Optical Transceiver
Features
?Enables Single-Module Design Compliance with 1000BASE-SR and 10GBASE-SR Specifications ?-21.5dBm Optical Sensitivity at 1.25Gbps Using a 10.32Gbps ROSA (-19.7dBm OMA)?Low Power Dissipation of 320mW at 3.3V Power Supply ?Typical Electrical Performance of 14.025Gbps on Rx/Tx (Non-Retimed 16x Fibre Channel Solution)?3mV P-P Receiver Sensitivity at 10.32Gbps ?4ps P-P DJ at Receiver Output at 8.5Gbps 8B/10B ?4ps P-P DJ at Receiver Output at 10.32Gbps 231- 1 PRBS ?26ps Rise and Fall Time at Rx/Tx Output ?Rate Select for 1Gbps Mode or 10Gbps Mode ?CML Output Squelch ?Polarity Select for Rx and Tx ?LOS Assert Level Adjustment ?LOS Polarity Select
?Modulation Current Up to 12mA Into 100ΩDifferential Load ?Bias Current Up to 15mA ?Integrated Eye Safety Features ?3-Wire Digital Interface
?Programmable Deemphasis at Tx Output
MAX3799
Amplifier and VCSEL Driver
________________________________________________________________Maxim Integrated Products 1
Ordering Information
For pricing, delivery, and ordering information,please contact Maxim Direct at 1-888-629-4642,or visit Maxim’s website at https://www.doczj.com/doc/8b394149.html,.
+Denotes a lead(Pb)-free/RoHS-compliant package.*EP = Exposed pad.**Tested at T A = +25°C.
PART TEMP RANGE PIN-PACKAGE MAX3799E TJ+ -40°C to +85°C 32 TQFN-E P* MAX3799E /D -40°C to +85°C Dice**
Typical Application Circuit and Pin Configuration appear at end of data sheet.
M A X 3799
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver 2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V CC = 2.85V to 3.63V, T A = -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, C AZ = 1nF, transmitter out-put load is AC-coupled to differential 100Ω(see Figure 1), typical values are at +25°C, V CC = 3.3V, I BIAS = 6mA, I MOD = 6mA, unless otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
V CCR , V CCT , V CCD .................................................-0.3V to +4.0V Voltage Range at DISABLE, SDA, SCL, CSEL,
RSEL, FAULT, BMON, LOS, CAZ2.........-0.3V to (V CC + 0.3V)Voltage Range at ROUT+, ROUT-.....(V CC - 1V) to (V CC + 0.3V)Voltage at TIN+, TIN-........................(V CC - 2.5V) to (V CC - 0.5V)Voltage Range at TOUT+, TOUT-......(V CC - 2V) to (V CC + 0.3V)Voltage at BIAS ............................................................0V to V CC Voltage at RIN+, RIN-..........................(V CC - 2V) to (V CC - 0.2V)Current Range into FAULT, LOS...........................-1mA to +5mA
Current Range into SDA........................................-1mA to +1mA Current into ROUT+, ROUT-...............................................40mA Current into TOUT+, TOUT-................................................60mA Continuous Power Dissipation (T A = +70°C)
32-Pin TQFN (derate 34.5W/°C above +70°C)...........2759mW Operating Junction Temperature Range...........-55°C to +150°C Storage Temperature Range.............................-65°C to +160°C Lead Temperature (soldering, 10s).................................+300°C Soldering Temperature (reflow).......................................+260°C
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 2.85V to 3.63V, T A = -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, C AZ = 1nF, transmitter out-put load is AC-coupled to differential 100Ω(see Figure 1), typical values are at +25°C, V CC = 3.3V, I BIAS = 6mA, I MOD = 6mA, unless
M A X 3799
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 2.85V to 3.63V, T A = -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, C AZ = 1nF, transmitter out-put load is AC-coupled to differential 100Ω(see Figure 1), typical values are at +25°C, V CC = 3.3V, I BIAS = 6mA, I MOD = 6mA, unless otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 2.85V to 3.63V, T A = -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, C AZ = 1nF, transmitter out-put load is AC-coupled to differential 100Ω(see Figure 1), typical values are at +25°C, V CC = 3.3V, I BIAS = 6mA, I MOD = 6mA, unless otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-
M A X 3799
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 2.85V to 3.63V, T A = -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, C AZ = 1nF, transmitter out-put load is AC-coupled to differential 100Ω(see Figure 1), typical values are at +25°C, V CC = 3.3V, I BIAS = 6mA, I MOD = 6mA, unless otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
_______________________________________________________________________________________7
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 2.85V to 3.63V, T A = -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, C AZ = 1nF, transmitter out-put load is AC-coupled to differential 100Ω(see Figure 1), typical values are at +25°C, V CC = 3.3V, I BIAS = 6mA, I MOD = 6mA, unless otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-
the supply current. BIAS must be connected to 2.0V. TOUT+/- must be connected through 50Ωload resistors to a separate supply voltage.
Note 2:Guaranteed by design and characterization, T A = -40°C to +95°C.
Note 3:The data input transition time is controlled by a 4th-order Bessel filter with -3dB frequency = 0.75 x data rate. The determin-istic jitter caused by this filter is not included in the DJ generation specifications.
Note 4:Test pattern is 00001111 at 1.25Gbps for RATE_SEL = 0. Test pattern is 00001111 at 8.5Gbps for RATE_SEL = 1.
Note 5:Receiver deterministic jitter is measured with a repeating 231- 1 PRBS equivalent pattern at 10.32Gbps. For 1.25Gbps to
8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is defined as the arithmetic sum of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ).
Note 6:Measured with a k28.5 pattern from 1.0625Gbps to 8.5Gbps. Measured with 231- 1 PRBS at 10.32Gbps.
Note 7:Measurement includes an input AC-coupling capacitor of 100nF and C CAZ of 100nF. The signal at the input is switched
between two amplitudes: Signal_ON and Signal_OFF.
1) Receiver operates at sensitivity level plus 1dB power penalty.a) Signal_OFF = 0
Signal_ON = (+8dB) + 10log(min_assert_level)b) Signal_ON = (+1dB) + 10log(max_deassert_level)Signal_OFF = 0
2) Receiver operates at overload.Signal_OFF = 0
Signal_ON = 1.2V P-P
max_deassert_level and the min_assert_level are measured for one LOS_THRESHOLD setting.
Note 8:Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and V CC
from +2.95V to +3.63V. Reference current measured at V CC = +3.2V, T A = +25°C.
Note 9:Transmitter deterministic jitter is measured with a repeating 27- 1 PRBS, 72 0s, 27- 1 PRBS, and 72 1s pattern at
10.32Gbps. For 1.0625Gbps to 8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is defined as the arithmetic sum of PWD and PDJ.
Note 10:Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and V CC
from +2.85V to +3.63V. Reference current measured at V CC = +3.3V, T A = +25°C.
M A X 3799
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver 8_______________________________________________________________________________________
Figure 1. Test Circuit for VCSEL Driver Characterization
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
_______________________________________________________________________________________9
Typical Operating Characteristics—Limiting Amplifier
(V CC = 3.3V, T A = +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
RANDOM JITTER vs. INPUT AMPLITUDE
INPUT AMPLITUDE (mV P-P )R A N D O M J I T T E R (p s )
1000
800
600
400
200
310320330340350360370300
1200DETERMINISTIC JITTER vs.INPUT AMPLITUDE AT 1.25Gbps
INPUT AMPLITUDE (mV P-P )D E T E R M I N I S T I C J I T T E R (p s )
1000
800
600
400
200
57911131517192123253
1200
DETERMINISTIC JITTER vs. INPUT AMPLITUDE
INPUT AMPLITUDE (mV P-P )
D E T E R M I N I S T I C J I T T E R (p s )
10008006004002002
345671
1200
DETERMINISTIC JITTER
vs. DATA RATE
DATA RATE (Gbps)D E T E R M I N I S T I C J I T T E R (p s )
12
10
2
4
6
8
34567
891020
14
BER vs. INPUT AMPLITUDE
INPUT AMPLITUDE (mV P-P )
B E R
2.52.01.0 1.51.0E-011.0E-021.0E-031.0E-041.0E-051.0E-061.0E-071.0E-081.0E-091.0E-101.0E-111.0E-13
1.0E-120.5 3.0
OUTPUT EYE DIAGRAM AT 1.25Gbps
MAX3799 toc06
200ps/div
150mV/div
RATE_SEL = 0
OUTPUT EYE DIAGRAM AT 4.25Gbps
50ps/div 50mV/div RATE_SEL = 1
OUTPUT EYE DIAGRAM AT 8.5Gbps
MAX3799 toc08
20ps/div 50mV/div OUTPUT EYE DIAGRAM AT 10.32Gbps
MAX3799 toc09
20ps/div
50mV/div
M A X 3799
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver 10______________________________________________________________________________________
Typical Operating Characteristics—Limiting Amplifier (continued)
(V CC = 3.3V, T A = +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
OUTPUT EYE DIAGRAM AT 14.025Gbps
20ps/div
50mV/div
RATE_SEL = 1, RXDE_EN = 1
TRANSITION TIME vs. INPUT AMPLITUDE
INPUT AMPLITUDE (mV P-P )
T R A N S I T I O N T I M E (p s )
1000
800
600
400
200
102030405060700
1200
LOS THRESHOLD vs. DAC SETTING
SET_LOS[5:0]
L O S T H R E S H O L D (m V )
56
49
35
42
14
21
28
7
20406080100120140160180
00
63
SENSITIVITY vs. DATA RATE
DATA RATE (Gbps)
S E N S I T I V I T Y O M A (d B m )
9
7
5
3
-21-20-19-18-17-16-15
-14-13-12-22
1
11
RATE_SEL = 1
RATE_SEL = 0
USING FINISAR ROSA
Rx INPUT RETURN LOSS
M A X 3799 t o c 14
FREQUENCY (Hz)S D D 11 (d B )
10G 1G -50
-40-30-20-100-60100M
100G
Rx OUTPUT RETURN LOSS
M A X 3799 t o c 15
FREQUENCY (Hz)
S D D 22 (d B )
10G 1G -45
-40-35-30-25-20-15-10-50
-50100M
100G
CML OUTPUT AMPLITUDE
vs. DAC SETTING
M A X 3799 t o c 16
SET_CML[7:0]C M L O U T P U T A M P L I T U D E (m V P -P )250
200
150
100
50
20040060080010001200140000
300TOTAL SUPPLY CURRENT vs. TEMPERATURE
TEMPERATURE (°C)S U P P L Y C U R R E N T (m A )
80
65
35
50
-10
5
20
-25506070809010011012013014040
-4095
TOTAL SUPPLY CURRENT vs. TEMPERATURE
TEMPERATURE (°C)
S U P P L Y C U R R E N T (m A )
80
65
35
50
-10
5
20
-25506070809010011012013014015016040
-4095
分销商库存信息:
MAXIM
MAX3799ETJ+MAX3799ETJ+T