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FEATURES APPLICATIONS
DESCRIPTION
PCM1742
SBAS176A–DECEMBER2000–REVISED APRIL2005 24-Bit,192-kHz Sampling,Enhanced Multilevel,Delta-Sigma,
Audio Digital-to-Analog Converter
?AV Receivers
?24-Bit Resolution
?DVD Movie Players
?Analog Performance(V CC=5V):
?DVD Add-On Cards for High-End PCs –Dynamic Range:
?DVD Audio Players
?106dB,Typical(PCM1742KE)
?HDTV Receivers
?100dB,Typical(PCM1742E)
?Car Audio Systems
–SNR:
?Other Applications Requiring24-Bit Audio ?106dB,Typical(PCM1742KE)
?100dB,Typical(PCM1742E)
–THD+N:The PCM1742is a CMOS,monolithic,integrated ?0.002%,Typical(PCM1742KE)circuit which includes stereo digital-to-analog con-
verters(DACs)and support circuitry in a small ?0.003%,Typical(PCM1742E)
SSOP-16package.The data converters use Texas –Full-Scale Output:3.1V p-p,Typical
Instruments'enhanced multilevel delta-sigma archi-?4x/8x Oversampling Digital Filter:tecture that employs fourth-order noise shaping and Stop-Band Attenuation:–55dB8-level amplitude quantization to achieve excellent Pass-Band Ripple:±0.03dB dynamic performance and improved tolerance to
clock jitter.The PCM1742accepts industry-standard ?Sampling Frequency:5kHz to200kHz
audio data formats with16-to24-bit data,providing ?System Clock:128f S,192f S,256f S,384f S,easy interfacing to audio DSP and decoder chips.
512f S,768f S With Autodetect Sampling rates up to200kHz are supported.A full ?Accepts16-,18-,20-,and24-Bit Audio Data set of user-programmable functions is accessible
through a3-wire serial control port that supports ?Data Formats:Standard,I2S,and
register write functions.
Left-Justified
?User-Programmable Mode Controls:
Digital Attenuation:0dB to–63dB,0.5
dB/Step
Digital De-Emphasis
Digital Filter Rolloff:Sharp or Slow
Soft Mute
Zero Flags for Each Output
?Dual-Supply Operation:5-V Analog,3.3-V
Digital
?5-V Tolerant Digital Inputs
?Small SSOP-16Package
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FilterPro is a trademark of Texas Instruments.
System Two,Audio Precision are trademarks of Audio Precision,Inc.
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ABSOLUTE MAXIMUM RATINGS (1)
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
PCM1742
SBAS176A–DECEMBER 2000–REVISED APRIL 2005over operating free-air temperature range (unless otherwise noted)
Power supply voltage,V DD
–0.3V to 4V Power supply voltage,V CC
–0.3V to 6.5V Supply voltage difference,V CC ,V DD
V CC –V DD <3V Ground voltage differences
±0.1V Digital input voltage
–0.3V to 6.5V Input current (except power supply pins)
±10mA Ambient temperature under bias
–40°C to 125°C Storage temperature,T stg
–55°C to 150°C Junction temperature,T J
150°C Lead temperature (soldering)
260°C,5s Package temperature (IR reflow,peak)
235°C (1)Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings
only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
over operating free-air temperature range
MIN
NOM MAX UNIT Digital supply voltage,V DD
3 3.3 3.6V Analog supply voltage,V CC
4.55
5.5V
Digital input logic family
TTL System clock 8.19236.864MHz Digital input clock frequency
Sampling clock 32192kHz Analog output load resistance
5k ?Analog output load capacitance
50pF Digital output load capacitance
20pF Operating free-air temperature,T A –2585°C All specifications at T A =25°C,V CC =5V,V DD =3.3V,f S =44.1kHz,system clock =384f S ,and 24-bit data (unless
otherwise noted)
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT Resolution
24Bits
DATA FORMAT
Audio data interface formats
Standard,I 2S,left-justified Audio data bit length
16-,18-,20-,24-bit selectable Audio data format
MSB-first,binary 2s complement f S Sampling frequency
5200kHz System clock frequency
128,192,256,384,512,768f S DIGITAL INPUT/OUTPUT
Logic family
TTL compatible Input Logic Level
V IH
High-level input votlage 2Vdc V IL Low-level input voltage 0.8Vdc
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PCM1742 SBAS176A–DECEMBER2000–REVISED APRIL2005
ELECTRICAL CHARACTERISTICS(continued)
All specifications at T
A =25°C,V
CC
=5V,V
DD
=3.3V,f
S
=44.1kHz,system clock=384f
S
,and24-bit data(unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input Logic Current
I IH High-level input current(1)V IN=V DD10μA
I IL Low-level input current(1)V IN=0V–10μA
I IH High-level input current(2)V IN=V DD65100μA
I IL Low-level input current(2)V IN=0V–10μA Output Logic Level
V OH High-level output voltage(3)I OH=–2mA 2.4Vdc
V OL Low-level output voltage(3)I OL=2mA1Vdc DYNAMIC PERFORMANCE(4)(5)
PCM1742E
V OUT=0dB,f S=44.1kHz0.003%0.008%
V OUT=0dB,f S=96kHz0.004%
V OUT=0dB,f S=192kHz0.005%
THD+N Total harmonic distortion+noise
V OUT=–60dB,f S=44.1kHz 1.2%
V OUT=–60dB,f S=96kHz 1.6%
V OUT=–60dB,f S=192kHz 1.8%
EIAJ,A-weighted,f S=44.1kHz94100
Dynamic range A-weighted,f S=96kHz98dB
A-weighted,f S=192kHz96
EIAJ,A-weighted,f S=44.1kHz94100
SNR Signal-to-noise ratio A-weighted,f S=96kHz98dB
A-weighted,f S=192kHz96
f S=44.1kHz9198
Channel separation f S=96kHz96dB
f S=192kHz94
Level linearity error V OUT=–90dB±0.5dB
(1)Pins1,2,3,16(SCK,BCK,LRCK,DATA).
(2)Pins13–15(MD,MC,ML).
(3)Pins11,12(ZEROR,ZEROL).
(4)Analog performance specifications are tested with a Shibasoku#725THD meter with400-Hz HPF on,30-kHz LPF on,and an average
mode with20-kHz bandwidth limiting.The load connected to the analog output is5k?or larger,via capacitive coupling.
(5)Conditions in192-kHz operation are:system clock=128f S and oversampling rate=64f S(under register control).
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PCM1742
SBAS176A–DECEMBER 2000–REVISED APRIL 2005ELECTRICAL CHARACTERISTICS (continued)
All specifications at T A =25°C,V CC =5V,V DD =3.3V,f S =44.1kHz,system clock =384f S ,and 24-bit data (unless
otherwise noted)
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT
PCM1742KE
V OUT =0dB,f S =44.1kHz
0.002%0.006%V OUT =0dB,f S =96kHz
0.003%V OUT =0dB,f S =192kHz
0.004%THD+N Total harmonic distortion +noise V OUT =–60dB,f S =44.1kHz
0.65%V OUT =–60dB,f S =96kHz
0.8%V OUT =–60dB,f S =192kHz
0.95%EIAJ,A-weighted,f S =44.1kHz
100106Dynamic range A-weighted,f S =96kHz
104dB A-weighted,f S =192kHz
102EIAJ,A-weighted,f S =44.1kHz
100106SNR Signal-to-noise ratio A-weighted,f S =96kHz
104dB A-weighted,f S =192kHz
102f S =44.1kHz
97103Channel separation
f S =96kHz 101dB f S =192kHz 100Level linearity error
V OUT =–90dB ±0.5dB DC ACCURACY
Gain error
±1±6%of FSR Gain mismatch,channel-to-channel
±1±3%of FSR Bipolar zero error
V OUT =0.5V CC at bipolar zero ±30±60mV ANALOG OUTPUT
Output voltage
Full scale (0dB)0.62V CC Vp-p Center voltage
0.5V CC Vdc Load Impedance
AC load 5k ?DIGITAL FILTER PERFORMANCE
Filter Characteristics,Sharp Rolloff
Pass band
±0.03dB 0.454f S Pass band
–3dB 0.487f S Stop band
0.546f S Pass-band ripple
±0.03dB Stop band =0.546f S –50Stop-band attenuation
dB Stop band =0.567f S –55Filter Characteristics,Slow Rolloff
Pass band
±0.5dB 0.198f S Pass band
–3dB 0.39f S Stop band
0.884f S Pass-band ripple
±0.5dB Stop-band attenuation
Stop band =0.884f S –40dB Delay time
20/f S s De-emphasis error
±0.1dB ANALOG FILTER PERFORMANCE
f =20kHz
–0.03Frequency response dB f =44kHz –0.20
https://www.doczj.com/doc/7b3809021.html, Functional Block Diagram
BCK
LRCK DATA ML MC MD
V OUT L V COM V OUT R
V D D D G N D Z E R O L Z E R O R SCK V C C
A G N D PCM1742SBAS176A–DECEMBER 2000–REVISED APRIL 2005
ELECTRICAL CHARACTERISTICS (continued)
All specifications at T A =25°C,V CC =5V,V DD =3.3V,f S =44.1kHz,system clock =384f S ,and 24-bit data (unless
otherwise noted)
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY REQUIREMENTS
(6)V DD
3 3.3 3.6Voltage range Vdc V CC
4.55
5.5f S =44.1kHz 610I DD Supply current f S =96kHz
13mA f S =192kHz
16f S =44.1kHz
8.513I CC Supply current f S =96kHz
9mA f S =192kHz
9f S =44.1kHz
6298Power dissipation
f S =96kHz 88mW f S =192kHz 98TEMPERATURE RANGE
T A
Operation temperature –2585°C θJA
Thermal resistance 115°C/W (6)Conditions in 192-kHz operation are:system clock =128f S and oversampling rate =64f S (under register control).
https://www.doczj.com/doc/7b3809021.html, PIN ASSIGNMENTS
BCK
DATA
LRCK
DGND
V DD
V CC
V OUT L
V OUT R
SCK
ML
MC
MD
ZEROL/NA
ZEROR/ZEROA
V COM
AGND 1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PCM1742
PCM1742
SBAS176A–DECEMBER2000–REVISED APRIL2005
PCM1742DBQ PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
AGND9–Analog ground
BCK1I Audio data bit clock input(1)
DATA2I Audio data digital input(1)
DGND4–Digital ground
LRCK3I L-channel and R-channel audio-data latch-enable input(1)
MC14I Mode control clock input(2)
MD13I Mode control data input(2)
ML15I Mode control latch input(2)
SCK16I System clock input(1)
V CC6–Analog power supply,5V
V COM10–Common voltage decoupling
V DD5–Digital power supply,3.3V
V OUT L7O Analog output for L-channel
V OUT R8O Analog output for R-channel
ZEROL/NA12O Zero-flag output for L-channel/No assign
ZEROR/ZEROA11O Zero-flag output for R-channel/Zero-flag output for L-/R-channel
(1)Schmitt-trigger input,5-V tolerant.
(2)Schmitt-trigger input with internal pulldown,5-V tolerant.
https://www.doczj.com/doc/7b3809021.html, TYPICAL PERFORMANCE CURVES
Digital Filter (De-Emphasis Off)
0?20
?40
?60?80?100
?120
?140
012
34Frequency (x f S )A m p l i t u d e (d B )0.050.040.030.020.010?0.01?0.02?0.03?0.04?0.0500.1
0.20.30.40.5Frequency (x f S )
A m p l i t u d e (d
B )0
?20
?40
?60?80?100
?120
?140
012
34Frequency (x f S )A m p l i t u d e (d B )543210?1?2?3?4?500.1
0.20.30.40.5Frequency (x f S )
A m p l i t u d e (d
B )PCM1742
SBAS176A–DECEMBER 2000–REVISED APRIL 2005
All specifications at T A =25°C,V CC =5V,V DD =3.3V,f S =44.1kHz,system clock =384f S ,and 24-bit input data,unless
otherwise noted
FREQUENCY RESPONSE (SHARP ROLLOFF)
PASS-BAND FREQUENCY RESPONSE (SHARP ROLLOFF)Figure 1.
Figure 2.FREQUENCY RESPONSE (SLOW ROLLOFF)
TRANSITION CHARACTERISTICS (SLOW ROLLOFF)Figure 3.Figure 4.
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TYPICAL PERFORMANCE CURVES (continued)
Digital Filter (De-Emphasis)
0.0
?1.0
?2.0
?3.0
?4.0?5.0?6.0
?7.0
?8.0
?9.0
?10.0
024********
Frequency (kHz)L e v e l (d B
)
0.50.40.30.20.10.0?0.1?0.2?0.3?0.4?0.502468101214Frequency (kHz)E r r o r (d B
)0.0
?1.0
?2.0
?3.0
?4.0?5.0?6.0
?7.0
?8.0
?9.0
?10.0
02468101214161820
Frequency (kHz)L e v e l (d B
)
0.50.40.30.20.10.0?0.1?0.2?0.3?0.4?0.502468101214161820Frequency (kHz)
E r r o r (d B
)0.0
?1.0
?2.0
?3.0
?4.0?5.0?6.0
?7.0
?8.0
?9.0
?10.0
02468101214161822
Frequency (kHz)L e v e l (d B
)
0.50.40.30.20.10.0?0.1?0.2?0.3?0.4?0.502468101214161822Frequency (kHz)
E r r o r (d B
)PCM1742
SBAS176A–DECEMBER 2000–REVISED APRIL 2005All specifications at T A =25°C,V CC =5V,V DD =3.3V,f S =44.1kHz,system clock =384f S ,and 24-bit input data,unless
otherwise noted
DE-EMPHASIS (f S =32kHz)
DE-EMPHASIS ERROR (f S =32kHz)
Figure 5.
Figure 6.DE-EMPHASIS (f S =44.1kHz)
DE-EMPHASIS ERROR (f S =44.1kHz)Figure 7.
Figure 8.DE-EMPHASIS (f S =48kHz)
DE-EMPHASIS ERROR (f S =48kHz)Figure 9.Figure 10.
https://www.doczj.com/doc/7b3809021.html, TYPICAL PERFORMANCE CURVES (continued)
ANALOG DYNAMIC PERFORMANCE
Supply Voltage Characteristics
110108106104102100
98
96
4 4.5
5 5.56V CC (V)D y n a m i c R a n g e (d B )
4 4.55
5.56V CC (V)T H D +N (%)
10
1
0.10.01
0.0001110
108
106
104102
100
98
96
4 4.55
5.56V CC (V)S N R (d B )1101081061041021009896
4 4.5
5 5.56
V CC (V)C h a n n e l S e p a r a t i o n (d B )PCM1742
SBAS176A–DECEMBER 2000–REVISED APRIL 2005
All specifications at T A =25°C,V CC =5V,V DD =3.3V,and 24-bit input data,unless otherwise specified.Conditions in
192-kHz operation are system clock =128f S and oversampling rate =64f S (under register control).
TOTAL HARMONIC DISTORTION +NOISE DYNAMIC RANGE vs vs V CC (V DD =3.3V)
V CC (V DD =3.3V)Figure 11.
Figure 12.SIGNAL-TO-NOISE RATIO CHANNEL SEPARATION vs vs V CC (V DD =3.3V)
V CC (V DD =3.3V)Figure 13.Figure 14.
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TYPICAL PERFORMANCE CURVES (continued)
ANALOG DYNAMIC PERFORMANCE (continued)
Temperature Characteristics
110108106104102100
98
96
?50?250255075100
D y n a m i c R a n g e (d B )
Temperature (°C)10
1
0.10.010.0010.0001
?50?250255075100T H D +N (%
)Temperature (°C)110
108
106
104102
100
98
96
?50?250255075100
S N R (d B
)Temperature (°C)1101081061041021009896?50?250255075100C h a n n e l S e p a r a t i o n (d B
)Temperature (°C)
PCM1742
SBAS176A–DECEMBER 2000–REVISED APRIL 2005All specifications at T A =25°C,V CC =5V,V DD =3.3V,and 24-bit input data,unless otherwise specified.Conditions in
192-kHz operation are system clock =128f S and oversampling rate =64f S (under register control).
TOTAL HARMONIC DISTORTION +NOISE DYNAMIC RANGE vs vs TEMPERATURE (T A )
TEMPERATURE (T A )Figure 15.
Figure 16.SIGNAL-TO-NOISE RATIO CHANNEL SEPARATION vs vs TEMPERATURE (T A )
TEMPERATURE (T A )Figure 17.Figure 18.
https://www.doczj.com/doc/7b3809021.html, SYSTEM CLOCK AND RESET FUNCTIONS
SYSTEM CLOCK INPUT
2V
0.8V System Clock
H
L
PCM1742
SBAS176A–DECEMBER 2000–REVISED APRIL 2005
The PCM1742requires a system clock for operating the digital interpolation filters and multilevel delta-sigma
modulators.The system clock is applied at the SCK input (pin 16).Table 1shows examples of system clock
frequencies for common audio sampling rates.
Figure 19shows the timing requirements for the system clock input.For optimal performance,it is important to
use a clock source with low phase jitter and noise.The PLL1700multiclock generator from Texas Instruments is
an excellent choice for providing the PCM1742system clock.
Table 1.System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
SYSTEM CLOCK FREQUENCY (f SCLK )(MHz)128f S
192f S 256f S 384f S 512f S 768f S 8kHz
(1)(1) 2.048 3.072 4.096 6.14416kHz
(1)(1) 4.096 6.1448.19212.28832kHz
(1)(1)8.19212.28816.38424.57644.1kHz
(1)(1)11.289616.934422.579233.868848kHz
(1)(1)12.28818.43224.57636.86488.2kHz
(1)(1)22.579233.868845.1584(1)96kHz
(1)(1)24.57636.86449.152(1)192kHz
24.57636.864(1)(1)(1)(1)(1)This system clock is not supported for the given sampling frequency.
SYMBOL
DESCRIPTION MIN MAX UNIT t SCKY
System clock cycle time (1)20ns t SCKH
System clock pulse duration,HIGH 7ns t SCKL
System clock pulse duration,LOW 7ns (1)1/128f S ,1/192f S ,1/256f S ,1/384f S ,1/512f S ,or 1/768f S
Figure 19.System Clock Input Timing
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POWER-ON RESET FUNCTIONS
V DD
Internal Reset
2.4V
2.0V
1.6V
0V System Clock AUDIO SERIAL INTERFACE
PCM1742
SBAS176A–DECEMBER 2000–REVISED APRIL 2005The PCM1742includes a power-on-reset function,as shown in Figure 20.With the system clock active and V DD >2V (typical,1.6V to 2.4V),the power-on-reset function is enabled.The initialization sequence requires 1024
system clocks from the time V DD >2V.After the initialization period,the PCM1742is set to its reset default
state,as described in the Mode Control Registers section of this data sheet.
During the reset period (1024system clocks),the analog outputs are forced to the bipolar zero level,or V CC /2.
After the reset period,all the mode control registers are initialized in the next 1/f S period and,if SCK,BCK,and
LRCK are provided continuously,the PCM1742provides proper analog output with group delay corresponding to
the input data.
Figure 20.Power-On-Reset Timing
The audio serial interface for the PCM1742comprises a 3-wire synchronous serial port.It includes LRCK (pin 3),
BCK (pin 1),and DATA (pin 2).BCK is the serial audio bit clock,which is used to clock the serial data present on
DATA into the audio interface serial shift register.Serial data is clocked into the PCM1742on the rising edge of
BCK.LRCK is the serial audio left/right word clock used to latch serial data into the serial audio interface internal
registers.
Both LRCK and BCK must be synchronous to the system clock.Ideally,it is recommended that LRCK and BCK
be derived from the system clock input,SCK.LRCK is operated at the sampling frequency,f S .BCK can be
operated at 32(16-bit,right-justified only),48,or 64times the sampling frequency.Internal operation of the
PCM1742is synchronized with LRCK.Accordingly,internal operation of the device is suspended when the
sampling rate clock of LRCK is changed or SCK and/or BCK is interrupted at least for three bit-clock cycles.If
SCK,BCK,and LRCK are provided continuously after this suspended state,the internal operation is
resynchronized automatically within a period of less than 3/f S .During this resynchronization period and for a 3/f S time thereafter,the analog output is forced to the bipolar zero level,or V CC /2.External resetting is not required.
https://www.doczj.com/doc/7b3809021.html, AUDIO DATA FORMATS AND TIMING
LRCK BCK
(=48or 64f S )
18?Bit Right?Justified
DATA DATA (2)I 2
S Data Form at:(3)Left?Justified (1)Sta ndard Data LRCK BCK
(=32,48or 64f S )
LRCK BCK
(=48or 64f S )
DATA DATA DATA DATA 24?Bit Right?Justified
20?Bit Right?Justified
DATA 16?Bit Right?16?Bit Right?PCM1742
SBAS176A–DECEMBER 2000–REVISED APRIL 2005
The PCM1742supports industry-standard audio data formats,including standard,I 2S,and left-justified,as shown
in Figure 21.Data formats are selected using the format bits,FMT[2:0],in control register 20.The default data
format is 24-bit,left-justified.All formats require binary 2s complement,MSB-first audio data.See Figure 22for a
detailed timing diagram of the serial audio interface.
Figure 21.Audio Data Input Formats
https://www.doczj.com/doc/7b3809021.html,
LRCK BCK DATA 50%of V
DD 50%of V DD 50%of V DD
PCM1742
SBAS176A–DECEMBER2000–REVISED APRIL2005
SYMBOL DESCRIPTION MIN MAX UNIT t BCY BCK pulse cycle time1/(64f S)(1)
t BCH BCK high-level time35ns t BCL BCK low-level time35ns t BL BCK rising edge to LRCK edge10ns t LB LRCK falling edge to BCK rising edge10ns t DS DATA setup time10ns t DH DATA hold time10ns
(1)f S is the sampling frequency(e.g.,44.1kHz,48kHz,96kHz,etc.).
Figure22.Audio Interface Timing
https://www.doczj.com/doc/7b3809021.html, SERIAL CONTROL INTERFACE
REGISTER WRITE OPERATION IDX5IDX60IDX4IDX2IDX3IDX1IDX0D7D6D 5D4D 3D 2D1D0
MSB
Register Index (or Address)Register Data
LSB
0D7D6D5D4D3D20IDX6
D1D0X X X IDX6IDX5IDX4IDX3IDX2IDX1IDX0ML
MC
MD PCM1742
SBAS176A–DECEMBER 2000–REVISED APRIL 2005
The serial control interface is a 3-wire serial port that operates asynchronously to the serial audio interface.The
serial control interface is used to program the on-chip mode registers.The serial control interface includes
MD (pin 13),MC (pin 14),and ML (pin 15).MD is the serial data input,used to program the mode registers;MC
is the serial bit clock,used to shift data into the control port;and ML is the control-port latch clock.
All write operations for the serial control port use 16-bit data words.Figure 23shows the control data word
format.The most significant bit must be a 0.Seven bits,labeled IDX[6:0],set the register index (or address)for
the write operation.The least significant eight bits,D[7:0],contain the data to be written to the register specified
by IDX[6:0].
Figure 23.Control Data Word Format for MD
Figure 24shows the functional timing diagram for writing to the serial control port.ML is held at a logic-1state
until a register needs to be written.To start the register write cycle,ML is set to logic-0.Sixteen clocks are then
provided on MC,corresponding to the 16bits of the control data word on MD.After the sixteenth clock cycle has
completed,ML is set to logic-1to latch the data into the indexed mode control register.
Figure 24.Register Write Operation
https://www.doczj.com/doc/7b3809021.html,
CONTROL INTERFACE TIMING REQUIREMENTS
50%of V DD 50%of V DD 50%of V DD
ML
MC
MD
MODE CONTROL REGISTERS
User-Programmable Mode Controls
PCM1742
SBAS176A–DECEMBER 2000–REVISED APRIL 2005See Figure 25for a detailed timing diagram of the serial control interface.These timing parameters are critical for
proper control port operation.
SYMBOL
PARAMETER MIN TYP MAX UNIT t MCY
MC pulse cycle time 100ns t MCL
MC low-level time 50ns t MCH
MC high-level time 50ns t MHH
ML high-level time 3/(256×f S )(2)ns t MLS
ML falling edge to MC rising edge 20ns t MLH
ML hold time (1)20ns t MDH
MD hold time 15ns t MDS
MD setup time 20ns (1)
MC rising edge for LSB to ML rising edge (2)f S =sampling rate
Figure 25.Control Interface Timing
The PCM1742includes a number of user-programmable functions that are accessed via control registers.The
registers are programmed using the serial control interface that is discussed in a preceding section of this data
sheet.Table 2lists the available mode control functions,along with their reset default conditions and associated
register index.
Table https://www.doczj.com/doc/7b3809021.html,er-Programmable Mode Controls
FUNCTION
RESET DEFAULT CONTROL INDEX IDX[6:0]REGISTER Digital attenuation control,0dB to –63dB in 0.5-dB steps
0dB,no attenuation 16and 17AT1[7:0],AT2[7:0]Soft mute control
Mute disabled 18MUT[2:0]Oversampling rate control (64f S or 128f S )
64-f S oversampling 18OVER DAC operation control
DAC1and DAC2enabled 19DAC[2:1]De-emphasis function control
De-emphasis disabled 19DM12De-emphasis sample rate selection
44.1kHz 19DMF[1:0]Audio data format control
24-bit,left-justified 20FMT[2:0]Digital filter rolloff control
Sharp rolloff 20FLT Zero-flag function select
L-/R-channels independent 22AZRO Output phase select
Normal phase 22DREV Zero-flag polarity select High 22ZREV
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Register Map
REGISTER DEFINITIONS
ATx[7:0]–Digital Attenuation Level Setting
PCM1742 SBAS176A–DECEMBER2000–REVISED APRIL2005
The mode control register map is shown in Table3.Each register includes an index(or address)indicated by the IDX[6:0]bits.
Table3.Mode Control Register Map
IDX REGIS-B15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0 (B14–B8)TER
10h160IDX6IDX5IDX4IDX3IDX2IDX1IDX0AT17AT16AT15AT14AT13AT12AT11AT10 11h170IDX6IDX5IDX4IDX3IDX2IDX1IDX0AT27AT26AT25AT24AT23AT22AT21AT20 12h180IDX6IDX5IDX4IDX3IDX2IDX1IDX0RSV(1)OVER RSV(1)RSV(1)RSV(1)RSV(1)MUT2MUT1 13h190IDX6IDX5IDX4IDX3IDX2IDX1IDX0RSV(1)DMF1DMF0DM12RSV(1)RSV(1)DAC2DAC1 14h200IDX6IDX5IDX4IDX3IDX2IDX1IDX0RSV(1)RSV(1)FLT RSV(1)RSV(1)FMT2FMT1FMT0 15h210IDX6IDX5IDX4IDX3IDX2IDX1IDX0RSV(1)RSV(1)RSV(1)RSV(1)RSV(1)RSV(1)RSV(1)RSV(1) 16h220IDX6IDX5IDX4IDX3IDX2IDX1IDX0RSV(1)RSV(1)RSV(1)RSV(1)RSV(1)AZRO ZREV DREV (1)RSV:Reserved for test operation.It should be set to0during normal operation.
B15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0 REGISTER160IDX6IDX5IDX4IDX3IDX2IDX1IDX0AT17AT16AT15AT14AT13AT12AT11AT10 REGISTER170IDX6IDX5IDX4IDX3IDX2IDX1IDX0AT27AT26AT25AT24AT23AT22AT21AT20
where x=1or2,corresponding to the DAC output V OUT L(x=1)and V OUT R(x=2).
Default value:11111111b
Each DAC channel(V OUT L and V OUT R)includes a digital attenuator function.The attenuation level can be set from0dB to–63dB,in0.5-dB steps.Changes in attenuation levels are made by incrementing or decrementing, by one step(0.5dB),for every8/f S time interval until the programmed attenuator setting is reached.Alternatively, the attenuation level can be set to infinite attenuation,or mute.The attenuation data for each channel can be set individually.
The attenuation level is calculated using the following formula:
Attenuation level(dB)=0.5(ATx[7:0]DEC–255)
where:ATx[7:0]DEC=0through255
for:ATx[7:0]DEC=0through128,the attenuator is set to infinite attenuation.
The following table shows attenuator levels for various settings.
ATx[7:0]DECIMAL VALUE ATTENUATOR LEVEL SETTING
11111111b2550dB,no attenuation(default)
11111110b254–0.5dB
11111101b253–1dB
:::
10000011b131–62dB
10000010b130–62.5dB
10000001b129–63dB
10000000b128Mute
:::
00000000b0Mute
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MUTx –Soft Mute Control
OVER –Oversampling Rate Control
PCM1742
SBAS176A–DECEMBER 2000–REVISED APRIL 2005B15
B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0REGISTER 180IDX6IDX5IDX4IDX3IDX2IDX1IDX0
RSV OVER RSV RSV RSV RSV MUT2MUT1where x =1or 2,corresponding to the DAC output V OUT L (x =1)and V OUT R (x =2).
Default value:0
MUTx =0
Mute disabled (default)MUTx =1Mute enabled
The mute bits,MUT1and MUT2,are used to enable or disable the soft mute function for the corresponding DAC
outputs,V OUT L and V OUT R.The soft mute function is incorporated into the digital attenuators.When mute is
disabled (MUTx =0),the attenuator and DAC operate normally.When mute is enabled by setting MUTx =1,the
digital attenuator for the corresponding output is decreased from the current setting to the infinite attenuation
setting by one attenuator step (0.5dB)at a time for every 8/f S period.This provides a pop-free muting of the
DAC output.
By setting MUTx =0,the attenuator is increased by one step for every 8/f S period to the previously programmed
attenuation level.
Default value:0
System clock rate =256f S ,384f S ,512f S ,or 768f S
OVER =0
64×oversampling (default)OVER =1128×oversampling
System clock rate =128f S or 192f S
OVER =0
32×oversampling (default)OVER =164×oversampling
The OVER bit is used to control the oversampling rate of the delta-sigma DACs.The OVER =1setting is
recommended when the oversampling rate is 192kHz (system clock is 128f S or 192f S ).
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DACx–DAC Operation Control
DM12–Digital De-Emphasis Function Control
DMF[1:0]–Sampling Frequency Selection for the De-Emphasis Function PCM1742
SBAS176A–DECEMBER2000–REVISED APRIL2005 B15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0 REGISTER190IDX6IDX5IDX4IDX3IDX2IDX1IDX0RSV DMF1DMF0DM12RSV RSV DAC2DAC1
where x=1or2,corresponding to the DAC output V OUT L(x=1)or V OUT R(x=2).
Default value:0
DACx=0DAC operation enabled(default)
DACx=1DAC operation disabled
The DAC operation controls are used to enable and disable the DAC outputs,V OUT L and V OUT R.When DACx= 0,the corresponding output generates the audio waveform dictated by the data present on the DATA pin.When DACx=1,the corresponding output is set to the bipolar zero level,or V CC/2.
Default value:0
DM12=0De-emphasis disabled(default)
DM12=1De-emphasis enabled
The DM12bit is used to enable or disable the digital de-emphasis function.Refer to the Typical Performance Curves section of this data sheet for more information.
Default value:00
DMF[1:0]De-Emphasis Sample Rate Selection
0044.1kHz(default)
0148kHz
1032kHz
11Reserved
The DMF[1:0]bits select the sampling frequency used for the digital de-emphasis function when it is enabled.
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FMT[2:0]–Audio Interface Data Format
FLT –Digital Filter Rolloff Control
PCM1742
SBAS176A–DECEMBER 2000–REVISED APRIL 2005B15
B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0REGISTER 200IDX6IDX5IDX4IDX3IDX2IDX1IDX0
RSV RSV FLT RSV RSV FMT2FMT1FMT0Default value:101
The FMT[2:0]bits are used to select the data format for the serial audio interface.The following table shows the
available format options.
FMT[2:0]
Audio Data Format Selection 000
24-bit standard format,right-justified data 001
20-bit standard format,right-justified data 010
18-bit standard format,right-justified data 011
16-bit standard format,right-justified data 100
I 2S format,16-to 24-bit 101
Left-justified format,16-to 24-bit (default)110
Reserved 111Reserved
Default value:0
FLT =0
Sharp rolloff (default)FLT =1Slow rolloff
The FLT bit allows the user to select the digital filter rolloff that is best suited to their application.Two filter rolloff
selections are available:sharp or slow.The filter responses for these selections are shown in the Typical
Performance Curves section of this data sheet.