January 2007
1/138
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev. 3
ST7L15, ST7L19
8-bit MCU for automotive with single voltage Flash/ROM memory,
data EEPROM, ADC, 5 timers, SPI
PRELIMINARY DATA
Features
■
Memories
–4 Kbytes single voltage extended Flash (XFlash) or ROM with readout protection, In-Circuit programming and In-Application Pro-gramming (ICP and IAP), 10K write/erase cy-cles guaranteed, data retention 20 years at 55°C
–256 bytes RAM
–128 bytes data E2PROM with readout protec-tion, 300K write/erase cycles guaranteed,data retention 20 years at 55°C
■
Clock, Reset and Supply Management –Enhanced reset system
–Enhanced low voltage supervisor (LVD) for main supply
–Clock sources: Internal 1% RC oscillator,crystal/ceramic resonator or external clock –Optional x4 or x8 PLL for 4 or 8MHz internal clock (only x8 PLL available for ROM devices)–5 power saving modes: Halt, Active Halt, Auto Wake-Up from Halt, Wait and Slow ■
I/O Ports
–Up to 17 multifunctional bidirectional I/O lines –7 high sink outputs ■
5 Timers
–Configurable watchdog timer
–Two 8-bit Lite timers with prescaler, 1 realtime base and 1 input capture
–Two 12-bit autoreload timers with 4 PWM out-puts, 1 input capture, 1 pulse and 4 output compare functions
■
Communication Interface
–SPI synchronous serial interface ■
Interrupt Management
–12 interrupt vectors plus TRAP and RESET –15 external interrupt lines (on 4 vectors)■
A/D Converter –7 input channels –10-bit precision ■
Instruction Set
–8-bit data manipulation
–63 basic instructions with illegal opcode de-tection
–17 main addressing modes
–8 x 8 unsigned multiply instructions ■
Development Tools
–Full hardware/software development package –DM (Debug Module)
Device Summary
Features
ST7L15
ST7L19
Program Memory - bytes 4K RAM (stack) - bytes 256 (128)
Data EEPROM - bytes -128
Peripherals
Lite Timer with Watchdog, Autoreload Timer, SPI, 10-bit ADC
Operating Supply 3V to 5.5V
CPU Frequency
Up to 8 MHz (w/ext OSC up to 16 MHz and int 1 MHz RC 1%, PLLx8/4 MHz)
Operating Temperature Up to -40 to +85°C / -40 to +125°C
Packages
SO20 300mil
Table of Contents
1381 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.1DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2PARAMETRIC DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.3DEBUG MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104.1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104.2MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104.3PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104.4ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114.5MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.6RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.7REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135.1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135.2MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135.3MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145.4POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.5ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.6DATA EEPROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.7REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186.1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186.2MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186.3CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.1INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.2PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227.3REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227.4MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247.5RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257.6SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318.1NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318.2EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318.3PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359.1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359.2SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359.3WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369.4HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379.5ACTIVE HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389.6AUTO WAKE-UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3910 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table of Contents
10.1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.2FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.3I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.4UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.5LOW-POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.6INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.7DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.8MULTIPLEXED INPUT/OUTPUT PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.1WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.2DUAL 12-BIT AUTORELOAD TIMER 4 (AT4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.3LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.4SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
11.510-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.2INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
13.1PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
13.2ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
13.3OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13.4SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
13.5CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.6MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.7EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.8I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.9CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.10COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 120
13.1110-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14.1PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14.2SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 126
15.1OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
15.2DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
15.3DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
15.4ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
ST7L15, ST7L19
1 INTRODUCTION
1.1 DESCRIPTION
The ST7L1x is a member of the ST7 microcontrol-ler family suitable for automotive applications. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruc-tion set.
The ST7L1 features Flash memory with byte-by-byte In-Circuit Programming (ICP) and In-Applica-tion Programming (IAP) capability.
Under software control, the ST7L1 device can be placed in WAIT, SLOW or HALT mode, reducing power consumption when the application is in idle or standby state.
The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 micro-controllers feature true bit manipulation, 8x8 un-signed multiplication and indirect addressing modes.
1.2 PARAMETRIC DATA
For easy reference, all parametric data is located in section 13 on page 98.1.3 DEBUG MODULE
The ST7L1 features an on-chip Debug Module (DM) to support In-Circuit Debugging (ICD). For a description of the DM registers, refer to the ST7ICC Protocol Reference Manual .
Figure 1. General Block Diagram
*Note : Not available on ROM devices.
8-bit CORE
ALU
ADDRESS AND DATA BUS
OSC1OSC2
RESET
PORT A INTERNAL CLOCK
CONTROL RAM (256 bytes)
PA7:0(8 bits)V SS V DD POWER SUPPLY PROGRAM (up to 4Kbytes)
LVD
MEMORY PLL x8Ext.1 MHz Int.1 MHz
8-bit
LITE TIMER 2
PORT B SPI
PB6:0(7 bits)DATA EEPROM (128 bytes)
1% RC OSC to 16 MHz
ADC
12-bit
AUTORELOAD TIMER 4CLKIN
/ 2
or PLL x4*
WATCHDOG
DEBUG MODULE
PORT C*
PC1:0(2 bits)
ST7L15, ST7L19
2 PIN DESCRIPTION
Figure 2. 20-Pin SO Package Pinout
Notes:
1. This pin cannot be configured as external interrupt in ROM devices.
2. OSC1 and OSC2 are not multiplexed in ROM devices and Port C is not present.
Legend / Abbreviations for Table 1:Type: I = input, O = output, S = supply
In/Output level:C T = CMOS 0.3V DD /0.7V DD with input trigger Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:– Input:float = floating, wpu = weak pull-up, int = interrupt, ana = analog – Output: OD = open drain, PP = push-pull
The RESET configuration of each pin (shown in bold) is valid as long as the device is in reset state.Table 1. Device Pin Description
201918171615141312345678V SS V DD AIN5/PB5CLKIN/AIN4/PB4
MOSI/AIN3/PB3MISO/AIN2/PB2SCK/AIN1/PB1SS/AIN0/PB0OSC1/CLKIN/PC02)OSC2/PC12)
PA5 (HS)/ATPWM3/ICCDATA PA4 (HS)/ATPWM2
PA3 (HS)/ATPWM1PA2 (HS)/ATPWM0PA1 (HS)/ATIC PA0 (HS)/LTIC 1)(HS)20mA High sink capability
eix associated external interrupt vector
1211
910
AIN6/PB6
PA7 (HS)
PA6/MCO/ICCCLK/BREAK RESET ei3
ei2
ei0
ei1
Pin No.
Pin Name
T y p e
Level
Port / Control Main Function (after reset)
Alternate Function
SO20I n p u t
O u t p u t Input Output f l o a t
w p u
i n t
a n a O D
P P
1V SS S Ground 2V DD
S
Main power supply
3
RESET I/O C T X
X
Top priority non maskable interrupt (active low)
ST7L15, ST7L19
Notes:
1. This pin cannot be configured as external interrupt in ROM devices.
2. OSC1 and OSC2 are not multiplexed in ROM devices and Port C is not present.
3. PCOR not implemented but p-transistor always active in output mode (refer to Figure 29 on page 45)
4PB0/AIN0/SS
I/O C T
X
ei3
X X X Port B0
ADC Analog Input 0 or SPI Slave Select (active low)
Caution: No negative current injec-tion allowed on this pin.
5PB1/AIN1/SCK I/O C T X X X X Port B1ADC Analog Input 1 or SPI Serial Clock
6PB2/AIN2/MISO I/O C T X X X X Port B2ADC Analog Input 2 or SPI Master In/ Slave Out Data
7PB3/AIN3/MOSI I/O C T X ei2
X X X Port B3ADC Analog Input 3 or SPI Master Out / Slave In Data
81)PB4/AIN4/CLKIN/COMPIN-I/O C T X X X X Port B4ADC Analog Input 4 or External clock input
91)PB5/AIN5I/O C T X X X X Port B5ADC Analog Input 5 101)PB6/AIN6I/O C T
X
X
X X Port B6ADC Analog Input 6
111)
PA7
I/O C T HS X
ei1X
X
Port A7
12
PA6 /MCO/
ICCCLK/BREAK
I/O C T
X ei1X X Port A6
Main Clock Output or In-Circuit Communication Clock or External BREAK
Caution: During normal operation this pin must be pulled- up, internal-ly or externally (external pull-up of 10k mandatory in noisy environ-ment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset puts it back in input pull-up
13PA5 /ICCDATA/ATPWM3I/O C T HS X ei1
X X Port A5In-Circuit Communication Data or Autoreload Timer PWM314PA4/ATPWM2I/O C T HS X X X Port A4Autoreload Timer PWM215PA3/ATPWM1I/O C T HS X ei0
X
X Port A3Autoreload Timer PWM116PA2/ATPWM0I/O C T HS X X X Port A2Autoreload Timer PWM017PA1/ATIC I/O C T HS X X X Port A1Autoreload Timer Input Capture 181)PA0/LTIC I/O C T HS X X
X Port A0Lite Timer Input Capture
192)OSC2/PC1
I/O
X X Port C13)Resonator oscillator inverter output 202)
OSC1/CLKIN/PC0I/O
X
X
Port C03)
Resonator oscillator inverter input or External clock input
Pin No.
Pin Name
T y p e
Level
Port / Control Main Function (after reset)
Alternate Function
SO20
I n p u t
O u t p u t Input Output f l o a t
w p u
i n t
a n a O D
P P
ST7L15, ST7L19
3 REGISTER AND MEMORY MAP
As shown in Figure 3, the MCU can address 64Kbytes of memories and I/O registers.
The available memory locations consist of 128bytes of register locations, 256 bytes of RAM, 128bytes of data EEPROM and up to 4Kbytes of Flash program memory. The RAM space includes up to 128 bytes for the stack from 180h to 1FFh.The highest address bytes contain the user reset and interrupt vectors.
The Flash memory contains two sectors (see Fig-ure 3) mapped in the upper part of the ST7 ad-dressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh).
The size of Flash Sector 0 and other device op-tions are configurable by Option byte (refer to sec-tion 15.1 on page 126).
IMPORTANT: Memory locations marked as “Re-served” must never be accessed. Accessing a re-served area can have unpredictable effects on the device.
Figure 3. Memory Map
Notes:
1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes containing also the RC calibration values which are read-accessible only in user mode. If all the EEPROM data or Flash space (including the RC calibration values locations) has been erased (after the readout protection removal), then the RC calibration values can still be obtained through these four addresses.
0000h RAM Flash Memory
(4K)
Interrupt and Reset Vectors
HW Registers 0080h 007Fh 0FFFh (see Table 2)1000h 107Fh FFE0h FFFFh
(see Table 5)
0180h Reserved 017Fh Short Addressing RAM (zero page)
0080h
00FFh (128 bytes)Data EEPROM (128 bytes)
F000h
1080h
EFFFh Reserved
FFDFh 128bytes Stack
0100h 017Fh 1 Kbyte 3 Kbytes (SECTOR 1)(SECTOR 0)
4K FLASH
FFFFh
FC00h FBFFh F000h PROGRAM MEMORY
DEE0h
RCCRH1RCCRL1
See section 7.1 on page 21and note 1.
00FFh 01FFh 0100h Reserved
RAM (128 bytes)Reserved
0200h
0180h 01FFh
DEE1h DEE2h RCCRH0RCCRL0 DEE3h
ST7L15, ST7L19
REGISTER AND MEMORY MAP (cont’d)Table 2. Hardware Register Map
Address Block
Register Label Register Name
Reset Status
Remarks 0000h 0001h 0002h Port A
PADR PADDR PAOR Port A Data Register
Port A Data Direction Register Port A Option Register FFh 1)00h 40h R/W R/W R/W 0003h 0004h 0005h Port B
PBDR PBDDR PBOR Port B Data Register
Port B Data Direction Register Port B Option Register FFh 1)00h 00h R/W R/W R/W 2)0006h 0007h Port C
PCDR PCDDR Port C Data Register
Port C Data Direction Register 0xh 00h R/W R/W 0008h 0009h 000Ah 000Bh 000Ch LITE TIMER 2
LTCSR2LTARR LTCNTR LTCSR1LTICR Lite Timer Control/Status Register 2Lite Timer Autoreload Register Lite Timer Counter Register
Lite Timer Control/Status Register 1Lite Timer Input Capture Register 00h 00h 00h 0x00 0000b
xxh R/W R/W
Read Only R/W
Read Only 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h AUTO-RELOAD TIMER 4
ATCSR CNTR1H CNTR1L ATRH ATRL PWMCR PWM0CSR PWM1CSR PWM2CSR PWM3CSR DCR0H DCR0L DCR1H DCR1L DCR2H DCR2L DCR3H DCR3L ATICRH ATICRL ATCSR2BREAKCR ATR2H ATR2L DTGR BREAKEN
Timer Control/Status Register Counter Register 1 High Counter Register 1 Low Autoreload Register High Autoreload Register Low
PWM Output Control Register PWM 0 Control/Status Register PWM 1 Control/Status Register PWM 2 Control/Status Register PWM 3 Control/Status Register PWM 0 Duty Cycle Register High PWM 0 Duty Cycle Register Low PWM 1 Duty Cycle Register High PWM 1 Duty Cycle Register Low PWM 2 Duty Cycle Register High PWM 2 Duty Cycle Register Low PWM 3 Duty Cycle Register High PWM 3 Duty Cycle Register Low Input Capture Register High Input Capture Register Low Timer Control/Status Register 2Break Control Register Autoreload Register 2 High Autoreload Register 2 Low
Dead Time Generation Register Break Enable Register
0x00 0000b
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 03h 00h 00h 00h 00h 03h
R/W
Read Only Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Read Only Read Only R/W R/W R/W R/W R/W R/W
0027h to 002Dh Reserved area (7 bytes)
002Eh WDG WDGCR Watchdog Control Register 7Fh R/W 0002Fh FLASH FCSR Flash Control/Status Register
00h R/W 00030h
EEPROM
EECSR
Data EEPROM Control/Status Register
00h
R/W
ST7L15, ST7L19
Legend : x =undefined, R/W =read/write
Notes :
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the Debug Module registers, see ST7 ICC Protocol Reference Manual .
0031h 0032h 0033h SPI
SPIDR SPICR SPICSR SPI Data I/O Register SPI Control Register
SPI Control Status Register xxh 0xh 00h R/W R/W R/W 0034h 0035h 0036h ADC ADCCSR ADCDRH ADCDRL A/D Control Status Register A/D Data Register High Data Low Register
00h xxh 0xh R/W
Read Only R/W 0037h ITC EICR External Interrupt Control Register 00h R/W 0038h MCC MCCSR Main Clock Control/Status Register 00h R/W 0039h 003Ah Clock and Reset RCCR SICSR RC oscillator Control Register
System Integrity Control/Status Register FFh 0110 0xx0b
R/W R/W 003Bh PLL clock select PLLTST PLL test register
00h R/W 003Ch ITC
EISR
External Interrupt Selection Register
0Ch
R/W
003Dh to 0048h Reserved area (12 bytes)
0049h 004Ah AWU
AWUPR AWUCSR AWU Prescaler Register
AWU Control/Status Register FFh 00h R/W R/W 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h DM 3)
DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L DMCR2
DM Control Register DM Status Register
DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low DM Control Register 2
00h 00h 00h 00h 00h 00h 00h
R/W R/W R/W R/W R/W R/W R/W
0052h to 007Fh
Reserved area (46 bytes)
Address Block
Register Label Register Name
Reset Status
Remarks
ST7L15, ST7L19
4 FLASH PROGRAM MEMORY
4.1 INTRODUCTION
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Program-ming.
The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.4.2 MAIN FEATURES
■ICP (In-Circuit Programming)
■IAP (In-Application Programming)
■
ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM ■Sector 0 size configurable by option byte ■
Readout and write protection
4.3 PROGRAMMING MODES
The ST7 can be programmed in three different ways:
–Insertion in a programming tool. In this mode,Flash sectors 0 and 1, option byte row and data EEPROM (if present) can be pro-grammed or erased.
–In-Circuit Programming. In this mode, Flash sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased without removing the device from the application board.
–In-Application Programming. In this mode,sector 1 and data EEPROM (if present) can be programmed or erased without removing the device from the application board and while the application is running.
4.3.1 In-Circuit Programming (ICP)
ICP uses a protocol called ICC (In-Circuit Commu-nication) which allows an ST7 plugged on a print-ed circuit board (PCB) to communicate with an ex-ternal programming device connected via a cable.ICP is performed in three steps:
–Switch the ST7 to ICC mode (In-Circuit Com-munications). This is done by driving a specif-ic signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RE-SET vector which points to the ST7 System Memory containing the ICC protocol routine.This routine enables the ST7 to receive bytes from the ICC interface.
–Download ICP Driver code in RAM from the ICCDATA pin
–Execute ICP Driver code in RAM to program the Flash memory
Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).
4.3.2 In-Application Programming (IAP)
This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode).
IAP mode is fully controlled by user software, al-lowing it to be adapted to the user application (such as a user-defined strategy for entering pro-gramming mode or a choice of communications protocol used to fetch the data to be stored). This mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the pro-gramming operation.
ST7L15, ST7L19
FLASH PROGRAM MEMORY (cont’d)4.4 ICC INTERFACE
ICP needs a minimum of four and up to six pins to be connected to the programming tool. These pins are:
––V SS : Device power supply ground –ICCCLK: ICC output serial clock pin –ICCDATA: ICC input serial data pin
–OSC1: Main clock input for external source (not required on devices without OSC1/OSC2pins)
–V DD : Application board power supply (option-al, see Note 3)
Notes:
1. If the ICCCLK or ICCDATA pins are only used as out-puts in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board,even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor must be implemented in case another de-vice forces the signal. Refer to the Programming Tool documentation for recommended resistor values.
2. During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push-pull output or pull-up resistor <1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R >1K or a reset man-agement IC with open drain output and pull-up resistor >1K, no additional components are needed. In all cases the user must ensure that no external reset is gen-erated by the application during the ICC session.
3. The use of pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be con-nected when using most ST Programming Tools (it is
used to monitor the application power supply). Please re-fer to the Programming Tool Manual .
4. Pin 9 must be connected to the OSC1 pin of the ST7when the clock is not available in the application or if the selected clock option is not programmed in the option byte. On ST7 devices with multi-oscillator capability,OSC2 must be grounded in this case.
5. In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. For ST7L1 devices which do not support the internal RC oscillator, the “option byte disabled” mode must be used (35-pulse ICC mode entry, clock provided by the tool).
Caution: During normal operation the ICCCLK pin must be pulled up, internally or externally (external pull-up of 10k mandatory in noisy environment).This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset puts it back in input pull-up.
ST7L15, ST7L19
FLASH PROGRAM MEMORY (cont’d)4.5 MEMORY PROTECTION
There are two different types of memory protec-tion: Readout Protection and Write/Erase Protec-tion, which can be applied individually.4.5.1 Readout Protection
Readout protection, when selected, protects against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreaka-ble, the feature provides a very high level of pro-tection for a general purpose microcontroller. Both program and data E 2 memory are protected.
In Flash devices, this protection is removed by re-programming the option. In this case, both pro-gram and data E 2 memory are automatically erased and the device can be reprogrammed.Readout protection selection depends on the de-vice type:
– In Flash devices it is enabled and removed through the FMP_R bit in the option byte.– In ROM devices it is enabled by the mask option specified in the Option List.4.5.2 Flash Write/Erase Protection
Write/erase protection, when set, makes it impos-sible to both overwrite and erase program memo-ry. It does not apply to E 2 data. Its purpose is to provide advanced security to applications and pre-vent any change being made to the memory con-tent.
Warning : Once set, Write/erase protection can never be removed. A write-protected Flash device is no longer reprogrammable.
Write/erase protection is enabled through the FMP_W bit in the option byte.4.6 RELATED DOCUMENTATION
For details on Flash programming and ICC proto-col, refer to the ST7 Flash Programming Refer-ence Manual and to the ST7 ICC Protocol Refer-ence Manual .
4.7 REGISTER DESCRIPTION
FLASH CONTROL/STATUS REGISTER (FCSR)Read/Write
Reset Value: 000 0000 (00h)1st RASS Key: 0101 0110 (56h)2nd RASS Key: 1010 1110 (AEh)
Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing op-erations.
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.
700
OPT
LAT
PGM
ST7L15, ST7L19
5 DATA EEPROM
5.1 INTRODUCTION
The Electrically Erasable Programmable Read Only Memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter.
5.2 MAIN FEATURES
■Up to 32 bytes programmed in the same cycle ■EEPROM mono-voltage (charge pump)■Chained erase and programming cycles
■
Internal control of the global programming cycle duration
■WAIT mode management ■
Readout protection
Figure 5. EEPROM Block Diagram
EECSR
HIGH VOLTAGE
PUMP
0E2LAT 00000E2PGM
EEPROM MEMORY MATRIX (1ROW =32x 8BITS)
ADDRESS DECODER
DATA MULTIPLEXER
32x 8BITS DATA LATCHES
ROW DECODER
DATA BUS
44
4
128128
ADDRESS BUS
ST7L15, ST7L19
DATA EEPROM (cont’d)5.3 MEMORY ACCESS
The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEP-ROM Control/Status register (EECSR). The flow-chart in Figure 6 describes these different memory access modes.
Read Operation (E2LAT =0)
The EEPROM can be read as a normal ROM loca-tion when the E2LAT bit of the EECSR register is cleared.
On this device, Data EEPROM can also be used to execute machine code. Do not write to the Data EEPROM while executing from it. This would re-sult in an unexpected code being executed.Write Operation (E2LAT =1)
To access the write mode, the E2LAT bit must be set by software (the E2PGM bit remains cleared).When a write access to the EEPROM area occurs,the value is latched inside the 32 data latches ac-cording to its address.
When PGM bit is set by the software, all the previ-ous bytes written in the data latches (up to 32) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEP-ROM write sequence. To avoid wrong program-ming, the user must ensure that all the bytes writ-ten between two programming sequences have the same high address: Only the five Least Signif-icant Bits of the address can change.
At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.
Note : Care should be taken during the program-ming cycle. Writing to the same memory location over-programs the memory (logical AND between the two write access data results) because the data latches are only cleared at the end of the pro-gramming cycle and by the falling edge of the E2LAT bit.
It is not possible to read the latched data.
This note is illustrated by the Figure 8 on page 16.
Figure 6. Data EEPROM Programming Flowchart
READ MODE E2LAT =0E2PGM =0WRITE MODE E2LAT =1E2PGM =0
READ BYTES IN EEPROM AREA
WRITE UP TO 32BYTES IN EEPROM AREA
(with the same 11MSB of the address)
START PROGRAMMING CYCLE
E2LAT =1
E2PGM =1(set by software)
E2LAT
1
CLEARED BY HARDWARE
ST7L15, ST7L19
DATA EEPROM (cont’d)
Figure 7. Data EEPROM Write Operation
Note:
If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed.
Byte 1Byte 2
Byte 32PHASE 1
Programming cycle
Read operation impossible
PHASE 2
Read operation possible
E2LAT bit
E2PGM bit
Writing data latches
Waiting E2PGM and E2LAT to fall
Set by USER application
Cleared by hardware
? Row / Byte ?
1
2
3
...
3031
Physical Address
000h...1Fh 120h...3Fh ...N
Nx20h...Nx20h+1Fh
ROW
DEFINITION
ST7L15, ST7L19
DATA EEPROM (cont’d)5.4 POWER SAVING MODES
Wait mode
The data EEPROM can enter WAIT mode on exe-cution of the WFI instruction of the microcontroller or when the microcontroller enters ACTIVE HALT mode.The data EEPROM immediately enters this mode if there is no programming in progress, oth-erwise the data EEPROM finishes the cycle and then enters WAIT mode.Active Halt mode Refer to WAIT mode.
Halt mode
The data EEPROM immediately enters HALT mode if the microcontroller executes the HALT in-struction. Therefore, the EEPROM stops the func-tion in progress, and data may be corrupted.
5.5 ACCESS ERROR HANDLING
If a read access occurs while E2LAT =1, then the data bus is not driven.
If a write access occurs while E2LAT =0, then the data on the bus is not latched.
If a programming cycle is interrupted (by RESET action), the integrity of the data in memory is not guaranteed.
5.6 DATA EEPROM READOUT PROTECTION The readout protection is enabled through an op-tion bit (see option byte section).
When this option is selected, the programs and data stored in the EEPROM memory are protected against readout (including a rewrite protection). In Flash devices, when this protection is removed by reprogramming the Option Byte, the entire Pro-gram memory and EEPROM is first automatically erased.
Note: Both Program Memory and data EEPROM are protected using the same option bit.
Figure 8. Data EEPROM Programming Cycle
LAT
ERASE CYCLE
WRITE CYCLE
PGM
t PROG
READ OPERATION NOT POSSIBLE
WRITE OF DATA LATCHES
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING VOLTAGE
ST7L15, ST7L19
DATA EEPROM (cont’d)5.7 REGISTER DESCRIPTION
EEPROM CONTROL/STATUS REGISTER (EEC-SR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:2 = Reserved, forced by hardware to 0.Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hard-ware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared.
0: Read mode 1: Write mode
Bit 0 = E2PGM Programming control and status This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware.
0: Programming finished or not yet started 1: Programming cycle is in progress
Note : If the E2PGM bit is cleared during the pro-gramming cycle, the memory data is not guaran-teed
Table 3. Data EEPROM Register Map and Reset Values
70
E2LAT E2PGM
Address (Hex.)Register Label 7
6
5
4
3
2
100030h
EECSR
Reset Value
000000
E2LAT 0
E2PGM 0
ST7L15, ST7L19
6 CENTRAL PROCESSING UNIT
6.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.6.2 MAIN FEATURES
■63 basic instructions
■Fast 8-bit by 8-bit multiply ■17 main addressing modes ■Two 8-bit index registers ■16-bit stack pointer ■Low power modes
■Maskable hardware interrupts ■
Non-maskable software interrupt
6.3 CPU REGISTERS
The six CPU registers shown in Figure 9 are not present in the memory mapping and are accessed by specific instructions.Accumulator (A)
The Accumulator is an 8-bit general purpose reg-ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation.(The Cross-Assembler generates a precede in-struction (PRE) to indicate that the following in-struction refers to the Y register.)
The Y register is not affected by the interrupt auto-matic procedures (not pushed to and popped from the stack).
Program Counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
Figure 9. CPU Registers
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
STACK POINTER
CONDITION CODE REGISTER
PROGRAM COUNTER
7
01C
11H I
N Z RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
7
07
007
15
8PCH
PCL
15
87
RESET VALUE = STACK HIGHER ADDRESS
RESET VALUE =1X
11X 1X X RESET VALUE = XXh RESET VALUE = XXh RESET VALUE = XXh
X = Undefined Value
ST7L15, ST7L19
CPU REGISTERS (cont’d)
CONDITION CODE REGISTER (CC) Read/Write
Reset Value: 111x1xxx
The 8-bit Condition Code register contains the in-terrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in-structions.
These bits can be individually tested and/or con-trolled by specific instructions.
Bit 4 = H Half carry
This bit is set by hardware when a carry occurs be-tween bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.
0: No half carry has occurred.1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruc-tion. The H bit is useful in BCD arithmetic subrou-tines.
Bit 3 = I Interrupt mask
This bit is set by hardware when entering in inter-rupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET in-structions and is tested by the JRM and JRNM in-structions.
Note: Interrupts requested while I is set are latched and can be processed when I is cleared.By default an interrupt routine is not interruptible
because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur-rent interrupt routine.
Bit 2 = N Negative
This bit is set and cleared by hardware. It is repre-sentative of the result sign of the last arithmetic,logical or data manipulation. It is a copy of the 7th bit of the result.
0: The result of the last operation is positive or null.1: The result of the last operation is negative (that is, the most significant bit is a logic 1).This bit is accessed by the JRMI and JRPL instruc-tions.Bit 1 = Z Zero
This bit is set and cleared by hardware. This bit in-dicates that the result of the last arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow
This bit is set and cleared by hardware and soft-ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation.0: No overflow or underflow has occurred.1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
701
1
1
H
I
N
Z
C
ST7L15, ST7L19
CPU REGISTERS (cont’d)STACK POINTER (SP)Read/Write
Reset Value: 01FFh
The Stack Pointer is a 16-bit register which always points to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 10).
Since the stack is 128 bytes deep, the 9 most sig-nificant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruc-tion (RSP), the Stack Pointer contains its reset val-ue (the SP6 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by an LD in-struction.
Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, with-out indicating the stack overflow. The previously stored information is then overwritten and there-fore lost. The stack also wraps in case of an under-flow.
The stack is used to save the return address dur-ing a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instruc-tions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 10.
– When an interrupt is received, the SP is decre-mented and the context is pushed on the stack.– On return from interrupt, the SP is incremented and the context is popped from the stack.
A subroutine call occupies two locations and an in-terrupt occupies five locations in the stack area.
Figure 10. Stack Manipulation Example
15800
1701
SP6
SP5
SP4
SP3
SP2
SP1
SP0
PCH
PCL
SP
PCH PCL
SP
PCL PCH X
A CC PCH PCL
SP
PCL PCH X A CC PCH PCL
SP
PCL PCH X A CC PCH PCL
SP
SP
Y CALL Subroutine
Interrupt Event
PUSH Y
POP Y IRET
RET or RSP
@ 01FFh
@ 0180h
Stack Higher Address = 01FFh Stack Lower Address =0180h