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IC datasheet pdf-ADS8284,pdf (Pseudo-Bipolar Differential SAR ADC with On-Chip ADC Driver )

FEATURES APPLICATIONS

DESCRIPTION

ADS8284 https://www.doczj.com/doc/609191932.html,...................................................................................................................................................................................................SLAS628–MARCH2009

18-BIT,1-MSPS,PSEUDO-BIPOLAR DIFFERENTIAL SAR ADC WITH ON-CHIP ADC DRIVER(OPA)AND4-CHANNEL DIFFERENTIAL MULTIPLEXER

?Medical Imaging/CT Scanners

? 1.0-MHz Sample Rate,Zero Latency at Full

Speed?Automated Test Equipment

?High-Speed Data Acquisition Systems

?18-Bit Resolution

?High-Speed Closed-Loop Systems ?Supports Pseudo-Bipolar Differential Input

Range:-4V to+4V with2-V Common-Mode

?Built-In Four Channel,Differential Ended

Multiplexer;with Channel Count Selection and The ADS8284is a high-performance analog Auto/Manual Mode system-on-chip(SoC)device with an18-bit,1-MSPS

A/D converter,4-V internal reference,an on-chip ?On-Board Differential ADC Driver(OPA)

ADC driver(OPA),and a4-channel differential ?Buffered Reference Output to Level Shift multiplexer.The channel count of the multiplexer and Bipolar±4-V Input with External Resistance auto/manual scan modes of the device are user Divider selectable.

?Reference/2Output to Set Common-Mode for The ADC driver is designed to leverage the very high External Signal Conditioner noise performance of the differential ADC at optimum ?18-/16-/8-Bit Parallel Interface power usage levels.

?SNR:98.4dB Typ at2-kHz I/P The ADS8284outputs a buffered reference signal for

level shifting of a±4-V bipolar signal with an external ?THD:–119dB Typ at2-kHz I/P

resistance divider.A V ref/2output signal is available ?Power Dissipation:331.25mW at1MSPS

to set the common-mode of a signal conditioning Including ADC Driver

circuit.The device also includes an18-/16-/8-bit ?Internal Reference parallel interface.

?Internal Reference Buffer The ADS8284is available in a9mm x9mm,64-pin ?64-Pin QFN Package QFN package and is characterized from-40°C to

85°C.

HIGH-SPEED SAR CONVERTER FAMILY

TYPE/SPEED500kHz~600kHz750kHz1MHz 1.25MHz2MHz3MHz4MHz

ADS8383ADS8381ADS8481

18-Bit Pseudo-Diff

ADS8380(s)

ADS8382(s)ADS8284ADS8484

18-Bit Pseudo-Bipolar,Fully Diff

ADS8482

ADS8327ADS8370(s)ADS8371ADS8471ADS8401ADS8411

16-Bit Pseudo-Diff ADS8328ADS8405ADS8410(s)

ADS8319

ADS8318ADS8372(s)ADS8472ADS8402ADS8412ADS8422

16-Bit Pseudo-Bipolar,Fully Diff

ADS8254ADS8406ADS8413(s)

14-Bit Pseudo-Diff ADS7890(s)ADS7891

12-Bit Pseudo-Diff ADS7886ADS7883ADS7881

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.Copyright?2009,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas

Instruments standard warranty.Production processing does not

necessarily include testing of all parameters.

ADS8284

SLAS628–https://www.doczj.com/doc/609191932.html, AUTO, C1, C2, C3,

2Submit Documentation Feedback Copyright?2009,Texas Instruments Incorporated

Product Folder Link(s):ADS8284

ABSOLUTE MAXIMUM RATINGS(1)ADS8284

https://www.doczj.com/doc/609191932.html,...................................................................................................................................................................................................SLAS628–MARCH2009 These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION(1)

MAXIMUM MAXIMUM NO MISSING

TRANSPORT INTEGRAL DIFFERENTIAL CODES AT PACKAGE PACKAGE TEMPERATURE ORDERING MODEL MEDIA LINEARITY LINEARITY RESOLUTION TYPE DESIGNATOR RANGE INFORMATION

QUANTITY (LSB)(LSB)(BIT)

ADS8284IBRGCT250

ADS8284lB±2.5+1.5/–118

ADS8284IBRGCR2000

–40°C to

64-pin QFN RGC

85°C ADS8284IRGCT250

ADS8284l±4.5+1.5/–118

ADS8284IRGCR2000 (1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI

website at https://www.doczj.com/doc/609191932.html,.

over operating free-air temperature range(unless otherwise noted)

VALUE UNIT

CH(i)to AGND(both P and M inputs)VEE–0.3to VCC+0.3V

VCC to VEE-0.3to18V

+VA to AGND–0.3to7V

+VBD to BDGND–0.3to7V

ADC control digital input voltage to GND–0.3to(+VBD+0.3)V

ADC control digital output to GND–0.3to(+VBD+0.3)V

Multiplexer control digital input voltage to GND–0.3to(+VA+0.3)V

Power control digital input voltage to GND–0.3to(+VCC+0.3)V

Operating temperature range–40to85°C

Storage temperature range–65to150°C

Junction temperature(T J max)150°C

Power dissipation(T J Max–T A)/θJA

QFN package

θJA Thermal impedance86°C/W

Vapor phase(60sec)215°C Lead temperature,soldering

Infrared(15sec)220°C (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings

only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Product Folder Link(s):ADS8284

SPECIFICATIONS

ADS8284

SLAS628–MARCH https://www.doczj.com/doc/609191932.html,

T A =–40°C to 85°C,VCC =5V,VEE =–5V,+VA =5V,+VBD =5V or 3.3V,V ref =4V,f SAMPLE =1MSPS (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT ANALOG INPUT

Full-scale input voltage at multiplexer input (1)CH(i)P–CH(i)M –V ref V ref

V Absolute input range at multiplexer input CH (i)

–0.2V ref +0.2

V [CH(i)P +CH(i)M]/2

(V ref )/2(V ref )/2

(V ref )/2Input common-mode voltage V

–0.2

+0.2

SYSTEM PERFORMANCE Resolution 18

Bits ADS8284IB 18No missing codes Bits ADS8284I 18ADS8284IB –2.5±1.25 2.5Integral linearity

(2)

LSB

(3)

ADS8284I –4.5±1.5 4.5ADS8284IB –1±0.6 1.5Differential linearity At 18-bit level

LSB (3)ADS8284I –1±0.6 1.5ADS8284IB –0.5±0.050.5Offset error mV ADS8284I –0.5±0.050.5ADS8284IB –0.1±0.0250.1Gain error (4)

External reference

%FS ADS8284I

–0.1

±0.025

0.1

At 3FFF0H output code.For +VA or VCC,VEE DC power supply rejection ratio 80

variation of 0.5V individually SAMPLING DYNAMICS +VBD =5V 625650ns Conversion time +VDB =3V 625650

ns +VBD =5V 320350ns

Acquisition time

+VDB =3V

320

350

Maximum throughput rate 1.0

MHz Aperture delay 4ns Aperture jitter

ps For ADC only

150ns Settling time to 0.5LSB For OPA (OP1,OP2)+mux 700Over voltage recovery

For ADC only

150ns

DYNAMIC CHARACTERISTICS

ADS8284I –119V IN =4V pp at 2kHz dB ADS8284IB

–119ADS8284I –105Total harmonic distortion V IN =4V pp at 10kHz dB (THD)(5)

ADS8284IB –105ADS8284I –100V IN =4V pp at 100kHz,dB LoPWR =0ADS8284IB –100ADS8284I 98.4

V IN =4V pp at 2kHz dB ADS8284IB

97.5

98.4ADS8284I 98Signal-to-noise ratio (SNR)

V IN =4V pp at 10kHz dB ADS8284IB 98ADS8284I 95V IN =4V pp at 100kHz,dB

LoPWR =0

ADS8284IB

(1)Ideal input span,does not include gain or offset error.(2)This is endpoint INL,not best fit.(3)LSB means least significant bit.

(4)Calculated on the first nine harmonics of the input frequency.(5)Measured relative to acutal measured reference.

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SPECIFICATIONS(continued)

T A=–40°C to85°C,VCC=5V,VEE=–5V,+VA=5V,+VBD=5V or3.3V,V ref=4V,f SAMPLE=1MSPS(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADS8284I98.3

V IN=4V pp at2kHz dB ADS8284IB98.3

ADS8284I97.2

Signal-to-noise+distortion

V IN=4V pp at10kHz dB (SINAD)ADS8284IB97.2

ADS8284I93.8

V IN=4V pp at100kHz,

LoPWR=0

ADS8284IB95.23

ADS8284I121

V IN=4V pp at2kHz dB ADS8284IB121

ADS8284I106

Spurious free dynamic

V IN=4V pp at10kHz dB range(SFDR)ADS8284IB106

ADS8284I101

V IN=4V pp at100kHz,

LoPWR=0

ADS8284IB101

–3dB small signal bandwidth8MHz VOLTAGE REFERENCE INPUT(REFIN)

Reference voltage at REFIN,V ref 3.0 4.096+VA–0.8V Reference input current(6)11μA INTERNAL REFERENCE OUTPUT(REFOUT)

Internal reference start-up time From95%(+VA),with1-μF storage capacitor120ms Reference voltage range,V ref 4.081 4.096 4.111V Source current Static load10μA Line regulation+VA=4.75V to5.25V60μV Drift I O=0±6PPM/°C BUFFERED REFERENCE OUTPUT(BUF-REF)

Output current REFIN=4V,at85°C70mA REFERENCE/2OUTPUT(VCMO)

Output current REFIN=4V,at+85°C50μA ANALOG MULTIPLEXER

Number of channels4

Channel to channel crosstalk100kHz i/p–95dB

Auto sequencer with selection of channel count or

Channel selection

manual selection through control lines

DIGITAL INPUT-OUTPUT

ADC CONTROL PINS

Logic Family-CMOS

V IH I IH=5μA+V BD–1+V BD+0.3V

V IL I IL=5μA0.30.8V Logic level

V OH I OH=2TTL loads+V BD–0.6+V BD V

V OL I OL=2TTL loads00.4V MULTIPLEXER CONTROL PINS

Logic Family-CMOS

I IH I IH=5μA 2.3+VA+0.3V Logic level

I IL I IL=5μA–0.30.8V POWER CONTROL PINS

Logic Family-CMOS

V IH I IH=5μA 2.3+VA+0.3V Logic level

V IL I IL=5μA–0.30.8V POWER SUPPLY REQUIREMENTS

(6)Can vary±20%

Product Folder Link(s):ADS8284

ADS8284

SLAS628–https://www.doczj.com/doc/609191932.html,

SPECIFICATIONS(continued)

T A=–40°C to85°C,VCC=5V,VEE=–5V,+VA=5V,+VBD=5V or3.3V,V ref=4V,f SAMPLE=1MSPS(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT +VBD 2.7 3.3 5.25V

+VA 4.755 5.25V Power supply voltage

VCC 4.7557.5V

VEE–7.5–5–3V

ADC driver positive supply(VCC)current(for OP1and VCC=+5,VEE=-5V,CH0-CH3p and m inputs

11.65mA OP2together)shorted to each other and connected to2V

ADC driver negative supply(VEE)current(for OP1and VCC=+5V,CH0-CH3p and m inputs shorted to

9.6mA OP1together)each other and connected to2V

+VA supply current,1-MHz sample rate4550mA

VCC=+5,PD-RBUF=0,Quiescent current8mA Reference buffer(BUF-REF)supply current(VCC to

GND)VCC=5,PD-RBUF=1(7)10μA TEMPERATURE RANGE

Operating free-air–4085°C (7)PD-RBUF=1powers down the reference buffer(BUF-REF),note that it does not3-state the BUF-REF output.

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TIMING REQUIREMENTS ADS8284

All specifications typical at–40°C to85°C,+VA=+VBD=5V(1)(2)(3)

PARAMETER MIN TYP MAX UNIT

t(CONV)Conversion time650ns

t(ACQ)Acquisition time320ns

t(HOLD)Sample capacitor hold time25ns

t pd1CONVST low to BUSY high40ns

t pd2Propagation delay time,end of conversion to BUSY low15ns

t pd3Propagation delay time,start of convert state to rising edge of BUSY15ns

t w1Pulse duration,CONVST low40ns

t su1Setup time,CS low to CONVST low20ns

t w2Pulse duration,CONVST high20ns CONVST falling edge jitter10ps

t w3Pulse duration,BUSY signal low t(ACQ)min ns

t w4Pulse duration,BUSY signal high650ns

t h1Hold time,first data bus transition(RD low,or CS low for read cycle,or BYTE or

40ns BUS18/16input changes)after CONVST low

t d1Delay time,CS low to RD low0ns

t su2Setup time,RD high to CS high0ns

t w5Pulse duration,RD low50ns

t en Enable time,RD low(or CS low for read cycle)to data valid20ns

t d2Delay time,data hold from RD high5ns

t d3Delay time,BUS18/16or BYTE rising edge or falling edge to data valid1020ns

t w6Pulse duration,RD high20ns

t w7Pulse duration,CS high20ns

t h2Hold time,last RD(or CS for read cycle)rising edge to CONVST falling edge50ns

t pd4Propagation delay time,BUSY falling edge to next RD(or CS for read cycle)falling

0ns edge

t d4Delay time,BYTE edge to BUS18/16edge skew0ns

t su3Setup time,BYTE or BUS18/16transition to RD falling edge10ns

t h3Hold time,BYTE or BUS18/16transition to RD falling edge10ns

t dis Disable time,RD high(CS high for read cycle)to3-stated data bus20ns

t d5Delay time,BUSY low to MSB data valid delay0ns

t d6Delay time,CS rising edge to BUSY falling edge50ns

t d7Delay time,BUSY falling edge to CS rising edge50ns

t su5BYTE transition setup time,from BYTE transition to next BYTE transition,or BUS18/16

50ns transition setup time,from BUS18/16to next BUS18/16.

t su(ABORT)Setup time from the falling edge of CONVST(used to start the valid conversion)to the

next falling edge of CONVST(when CS=0and CONVST are used to abort)or to the60550ns

next falling edge of CS(when CS is used to abort).

(1)All input signals are specified with t r=t f=5ns(10%to90%of+VBD)and timed from a voltage level of(V IL+V IH)/2.

(2)See timing diagrams.

(3)All timing are measured with20pF equivalent loads on all data bits and BUSY pins.

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TIMING REQUIREMENTS

MULTIPLEXER TIMING REQUIREMENTS

ADS8284

SLAS628–MARCH https://www.doczj.com/doc/609191932.html,

All specifications typical at –40°C to 85°C,+VA =5V +VBD =3V

(1)(2)(3)

PARAMETER

MIN TYP MAX UNIT t (CONV)Conversion time 650

ns t (ACQ)Acquisition time

320

ns t (HOLD)Sample capacitor hold time 25ns t pd1CONVST low to BUSY high

40ns t pd2Propagation delay time,end of conversion to BUSY low

25ns t pd3Propagation delay time,start of convert state to rising edge of BUSY 25

ns t w1Pulse duration,CONVST low 40ns t su1Setup time,CS low to CONVST low 20ns t w2Pulse duration,CONVST high 20

ns CONVST falling edge jitter 10

ps t w3Pulse duration,BUSY signal low t (ACQ)min

ns t w4Pulse duration,BUSY signal high

650

ns t h1Hold time,first data bus transition (RD low,or CS low for read cycle,or BYTE or 40ns BUS18/16input changes)after CONVST low t d1Delay time,CS low to RD low 0ns t su2Setup time,RD high to CS high 0ns t w5Pulse duration,RD low

ns t en Enable time,RD low (or CS low for read cycle)to data valid 30

ns t d2Delay time,data hold from RD high

5ns t d3Delay time,BUS18/16or BYTE rising edge or falling edge to data valid 1030

ns t w6Pulse duration,RD high 20ns t w7Pulse duration,CS high

20ns t h2Hold time,last RD (or CS for read cycle )rising edge to CONVST falling edge 50ns t pd4Propagation delay time,BUSY falling edge to next RD (or CS for read cycle)falling 0ns edge

t d4Delay time,BYTE edge to BUS18/16edge skew

0ns t su3Setup time,BYTE or BUS18/16transition to RD falling edge 10ns t h3Hold time,BYTE or BUS18/16transition to RD falling edge 10

ns t dis Disable time,RD high (CS high for read cycle)to 3-stated data bus 30ns t d5Delay time,BUSY low to MSB data valid delay 0ns t d6Delay time,CS rising edge to BUSY falling edge 50ns t d7Delay time,BUSY falling edge to CS rising edge

50ns t su5

BYTE transition setup time,from BYTE transition to next BYTE transition,or BUS18/1650ns transition setup time,from BUS18/16to next BUS18/16.

t su(ABORT)Setup time from the falling edge of CONVST (used to start the valid conversion)to the

next falling edge of CONVST (when CS =0and CONVST are used to abort)or to the 70

550

next falling edge of CS (when CS is used to abort).(1)All input signals are specified with t r =t f =5ns (10%to 90%of +VBD)and timed from a voltage level of (V IL +V IH )/2.(2)See timing diagrams.

(3)

All timing are measured with 20-pF equivalent loads on all data bits and BUSY pins.

VCC =4.75V to 7.5V,VEE =-3V to -7.5V

MIN

TYP

MAX UNIT t su6Setup time C1,C2or C3to MXCLK rising edge

600

ns t d8

Multiplexer and driver settle time (from MXCLK rising edge to CONVST falling edge)

600

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PIN ASSIGNMENTS

QFN PACKAGE (TOP VIEW)

A U T C C C M X C L +V A G N +V A G N D

B 1D B 1D B 1D B 1D B 1D B 1D B 1ADS8284

PIN FUNCTIONS

I/O

DESCRIPTION

NAME

MULTIPLEXER INPUT PINS Non-inverting analog input for differential multiplexer channel number 0.Device performance is optimized for 50-?source 17CH0P I impedance at this input.

Inverting analog input for differential multiplexer channel number 0.Device performance is optimized for 50-?source 18CH0M I impedance at this input.

Non-inverting analog input for differential multiplexer channel number 1.Device performance is optimized for 50-?source 19CH1P I impedance at this input.

Inverting analog input for differential multiplexer channel number 1.Device performance is optimized for 50-?source 20CH1M I impedance at this input.

Non-inverting analog input for differential multiplexer channel number 2.Device performance is optimized for 50-?source 29CH2P I impedance at this input.

Inverting analog input for differential multiplexer channel number 2.Device performance is optimized for 50-?source 30CH2M I impedance at this input.

Non-inverting analog input for differential multiplexer channel number 3.Device performance is optimized for 50ohm source 31CH3P I impedance at this input.

Inverting analog input for differential multiplexer channel number 3.Device performance is optimized for 50-?source 32

CH3M

impedance at this input.

ADC INPUT PINS 25INP I ADC Non inverting input.,connect 1-nF capacitor across INP and INM 27INM I ADC Inverting input,connect 1-nF capacitor across INP and INM REFERENCE INPUT/OUTPUT PINS

8,9REFM I Reference ground.

10REFIN I Reference Input.Add 0.1-μF decoupling capacitor between REFIN and REFM.

REFOUT

Reference Output.Add 1-μF capacitor between the REFOUT pin and REFM pin when internal reference is used.

Product Folder Link(s):ADS8284

ADS8284

SLAS628–https://www.doczj.com/doc/609191932.html,

PIN FUNCTIONS(continued)

I/O DESCRIPTION

NO NAME

14VCMO O This pin outputs REFIN/2and can be used to set common-mode voltage of differential analog inputs.

15BUF-REF O Buffered reference https://www.doczj.com/doc/609191932.html,eful to level shift bipolar signals using external resistors.

POWER CONTROL PINS

21PD-RBUF I High on this pin powers down the reference buffer(BUF-REF).

MULTIPLEXER CONTROL PINS

33AUTO I High level on this pin selects auto mode for multiplexer scanning.Low level selects manual mode of multiplexer scanning

In auto mode(AUTO=1)multiplexer channel selection is reset to CH0on rising edge of MXCLK while C3=1.The pin is do 34C3I

not care in manual mode.

Acts as multiplexer address bit when AUTO=0(manual mode).In auto mode(AUTO=1)C2and C1select the last 35C2I

multiplexer channel(channel count)in the auto scan sequence.

Acts as multiplexer address LSB when AUTO=0(manual mode).In auto mode(AUTO=1)C2and C1select the last 36C1I

multiplexer channel(channel count)in the auto scan sequence.

Multiplexer channel is selected on rising edge of MXCLK irrespective of whether it is auto or manual mode.Device BUSY 37MXCLK I

output can be connected to MXCLK so that device selects next channel at the end of every sample.

ADC DATA BUS

8-BIT BUS16-BIT BUS18-BIT BUS

42-49,

Data Bus BYTE=0BYTE=1BYTE=1BYTE=0BYTE=0BYTE=0

52-61

BUS18/16=0BUS18/16=0BUS18/16=1BUS18/16=0BUS18/16=1BUS18/16=0 42DB17O D17(MSB)D9All ones D17(MSB)All ones D17(MSB) 43DB16O D16D8All ones D16All ones D16

44DB15O D15D7All ones D15All ones D15

45DB14O D14D6All ones D14All ones D14

46DB13O D13D5All ones D13All ones D13

47DB12O D12D4All ones D12All ones D12

48DB11O D11D3D1D11All ones D11

49DB10O D10D2D0(LSB)D10All ones D10

52DB9O D9All ones All ones D9All ones D9

53DB8O D8All ones All ones D8All ones D8

54DB7O D7All ones All ones D7All ones D7

55DB6O D6All ones All ones D6All ones D6

56DB5O D5All ones All ones D5All ones D5

57DB4O D4All ones All ones D4All ones D4

58DB3O D3All ones All ones D3D1D3

59DB2O D2All ones All ones D2D0(LSB)D2

60DB1O D1All ones All ones D1All ones D1

61DB0O D0(LSB)All ones All ones D0(LSB)All ones D0(LSB)

ADC CONTROL PINS

62BUSY O Status output.This pin is held high when device is converting.

64BUS18_16I Bus size select https://www.doczj.com/doc/609191932.html,ed for selecting18-bit or16-bit wide bus transfer.Refer to ADC DATA BUS description above.

1BYTE I Byte Select https://www.doczj.com/doc/609191932.html,ed for8-bit bus reading.Refer to ADC DATA BUS description above.

2CONVST I Convert start.This input is active low and can act independent of the CS input.

3RD I Synchronization pulse for the parallel output.

4CS I Chip select.

DEVICE POWER SUPPLIES

22VEE Negative supply for OPA(OP1,OP2)

23,24VCC Positive supply for OPA(OP1,OP2,BUF-REF)

5,7,

13,38,+VA Analog power supply.

6,12,

26,39,AGND Analog ground.

50,63+VBD Digital power supply for ADC bus.

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DEVICE OPERATION AND TIMING DIAGRAMS

ADS8284

PIN FUNCTIONS (continued)

I/O

DESCRIPTION

NO NAME 51BGND Digital ground for ADC bus interface digital supply.NOT CONNECTED PINS

16,28

No connection.

The ADS8284is analog system-on-chip (SoC)device.The device includes a multiplexer,a differential input/differential output ADC driver and differential input high-performance ADC,an additional internal reference,a buffered reference output,and a REF/2output.

Figure 1shows the basic operation of the device (including all elements).Subsequent sections describe the of the individual blocks of the device (primarily the multiplexer and ADC).

Figure 1.Device Operation

As shown in the diagram,the device can be controlled with only one (CONVST)digital input.On the falling edge of the BUSY output of the device goes high.A high level on BUSY indicates the device has sampled the signal and it is converting the sample into its digital equivalent.After the conversion is complete,the BUSY output falls to a logic low level and the device output data corresponding to the recently converted sample is available for reading.

Product Folder Link(s):ADS8284

ADS8284

SLAS628–https://www.doczj.com/doc/609191932.html, It is recommended(not mandatory)to short the BUSY output of the device to the MXCLK input.The device selects a new channel at every rising edge of MXCLK.The multiplexer is differential.The multiplexer and ADC driver are designed to settle to the18-bit level before sampling;even at the maximum conversion speed.

ADC control and timing:The timing diagrams in this section describe ADC operation;multiplexer operation is described in a later section.

?Signal internal to device

Figure2.Timing for Conversion and Acquisition Cycles with and Toggling

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CONVST

BUSY

CONVERT?

(When CS Toggle)

BYTE

BUS 18/16

RD = 0

DB[17:12]

DB[11:10]

DB[9:0]

Figure3.Timing for Conversion and Acquisition Cycles with CS Toggling,RD Tied to BDGND

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ADS8284

SLAS628–https://www.doczj.com/doc/609191932.html,

?Signal internal to device

Figure4.Timing for Conversion and Acquisition Cycles With CS Tied to BDGND,RD Toggling

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?Signal internal to device ADS8284

Figure5.Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND-Auto Read

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BYTE

BUS 18/16

DB[17:0]

ADS8284

SLAS628–MARCH https://www.doczj.com/doc/609191932.html,

Figure 6.Detailed Timing for Read Cycles

Multiplexer:The multiplexer has two modes of sequencing namely auto sequencing and manual sequencing.Multiplexer mode selection and operation is controlled with the AUTO,C1,C2,C3,and MXCLK pins.

Auto sequencing:A logic one level on the AUTO pin selects auto sequencing mode.It is possible to select the number of channels to be scanned (always starting from channel zero)in auto sequencing mode.Pins C1and C2select the channel count (last channel in the auto sequence).

On every rising edge of MXCLK while C3is at the logic zero level,the next higher channel (in ascending order)is selected.Channel selection rolls over to channel zero on the rising edge of MXCLK after channel selection reaches the channel count (last channel in the auto sequence selected by pins C1and C2).

Any time during the sequence the channel sequence can be reset to channel zero.A rising edge on MXCLK while C3is at the logic one level resets channel selection to channel zero.

Table 1.Channel Selection in Auto Mode

CHANNEL COUNT PINS CLOCK PIN LAST CHANNEL IN SEQUENCE

CHANNEL SEQUENCE

C3C2C1MXCLK

000↑00,0,0,0..001↑10,1,0,1,..010↑20,1,2,0,1,2,0...011↑30,1,2,3,0,1,2,3,0 (1)

↑

n →0(channel reset to zero)

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AUTO =1,device operation in auto mode

Selected Channel

AUTO =0,device operation in manual mode

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Figure 7.Multiplexer Auto Mode Timing Diagram

Manual sequencing:A logic zero level on the AUTO pin selects manual sequencing mode.Pins C1and C2set the channel address.On the rising edge of MXCLK,the addressed channel is connected to the ADC driver input.

Table 2.Channel Selection in Manual Mode

MODE CHANNEL ADDRESS PINS CLOCK PIN CHANNEL

AUTO C3C2C1MXCLK

0X 00↑00X 01↑10X 10↑20

↑

Figure 8.Multiplexer Manual Mode Timing Diagram

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TYPICAL CHARACTERISTICS

4.0955

-40

-25-1052035506580

T - Free-Air Temperature - °C

A R e f e r e n c e V o l t a g e - V

1000012000140001600018000200001310313104131041310413104131041310413104131041310413104131050

500

10001500

200025003000131039

131040

131041

1042

131043

131044

131045

131046

131047

131048

131049

13103

Supply Voltage - V

R e f e r e n c e V o l t a g e - V

4242.2542.542.754343.2543.543.75

444.70

4.80

4.905

5.10 5.20 5.30 5.40

+VA -Analog Voltage - V

I A - S u p p l y C u r r e n t - m

42.25

42.5

42.754343.2543.543.75

44S u p p l y C u r r e n t - m A

T - Free-Air Temperature - °C

404142434446Sample Rate - KSPS

S u p p l y C u r r e n t -

m A

11.111.211.311.411.511.611.711.811.9

56V - Supply Voltage - V

CC+7I - S u p p l y C u r r e n t - m A

C C -40

-20020406080T - Free-Air Temperature - °C

A 99.5

1010.51111.51212.51313.5

I - S u p p l y C u r r e n t - m A

C C ADS8284

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INTERNAL REFERENCE VOLTAGE

DC HISTOGRAM

(CH0without mux switching)

(CH0with mux switching,CH 0-1-0)

FREE-AIR TEMPERATURE

Figure 9.

Figure 10.

Figure 11.

ANALOG VOLTAGE (+VA)SUPPLY

INTERNAL REFERENCE VOLTAGE

CURRENT (IA)

SUPPLY CURRENT (IA)

SUPPLY VOLTAGE

FREE-AIR TEMPERATURE

ANALOG VOLTAGE (+VA)

Figure 12.Figure 13.

Figure 14.

OPA POSITIVE SUPPLY CURRENT

(I CC )ANALOG SUPPLY CURRENT

(I CC )vs

OPA POSITIVE SUPPLY VOLTAGE

SAMPLE RATE

FREE-AIR TEMPERATURE

(+VCC)

Figure 15.Figure 16.Figure 17.

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88.599.510

10.5

T - Free-Air Temperature - °C

A I - S u p p l y C u r r e n t - m A

E E 9.4

9.45

9.5

9.55

9.6

9.65

-8

-7

-6-5-4-3-2

V - Voltage Supply - V

EE I - S u p p l y C u r r e n t - m A

E E -1-0.75-0.5-0.2500.250.50.751

D N L - D i f f e r e n t i a l N o n L i n e a r i t y - L S B

T - Free-Air Temperature - °C

+VA -Analog Supply - V

00.250.50.751

D N L - D i f f e r e n

t i a l N o n L i n e a r i t y - L S B

00.20.40.60.81

D N L - D i f f e r e n t i a l N o n L i n e a r i t y - L S B

V - Supply Voltage - V

CC V - Reference Voltage - V

REF D N L - D i f f e r e n

t i a l N o n L i n e a r i t y - L S B

Multiplexer Channels

-1-0.8-0.6-0.4-0.200.20.40.60.8

D N L - D i f f

e r e n t i a l N o n L i n e a r i t y - L S B

+VA -Analog Voltage - V

-2-1.5-1-0.500.511.52

I N L - I n t e g r a l N o n L i n e a r i t y - L S

00.511.52

I N L - I n t e g r a l N o n L i n e a r i t y - L S B

T - Free-Air Temperature - °C

A ADS8284

TYPICAL CHARACTERISTICS (continued)

OPA NEGATIVE SUPPLY CURRENT

(IEE)OPA -VE SUPPLY CURRENT (IEE)

DIFFERENTIAL NONLINEARITY

OPA NEGATIVE SUPPLY VOLTAGE

FREE-AIR TEMPERATURE

(-VEE)

FREE-AIR TEMPERATURE

Figure 18.

Figure 19.

Figure 20.

DIFFERENTIAL NONLINEARITY

ANALOG SUPPLY VOLTAGE (+VA)

REFERENCE VOLTAGE

OPA SUPPLY VOLTAGE (VCC)

Figure 21.

Figure 22.

Figure 23.

DIFFERENTIAL NONLINEARITY

INTEGRAL NONLINEARITY

MULTIPLEXER CHANNELS

FREE-AIR TEMPERATURE

ANALOG SUPPLY VOLTAGE (+VA)

Figure 24.Figure 25.

Figure 26.

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-2-1.5-1-0.500.511.52I N L - I n t e g r a l N o n L i n e a r i t y - L S B

Multiplexer Channels

-2

-1.5-1-0.500.51

1.5

I N L - I n t e g r a l N o n L i n e a r i t y - L S B

V - Reference Voltage - V

REF

00.511.52I N L - I n t e g r a l N o n L i n e a r i t y - L S B

V - Supply Voltage - V

0F u l l c h i p o f f s e t -V

m +VA -Analog Voltage - V

050100

150F u l l C h i p O f f s e t -V

m T - Free-Air Temperature - °C

A F u l l c h i p o f f s e t -V

V - Supply Voltage - V

CC -150

-135

-120-105-90-75-60-45-30

-150Channels

F u l l C h i p O f f s e t -V

F u l l C h i p

G a i n

E r r o r - % o f

F S

T - Free-Air Temperature - °C

A 0F u l l c h i p o f f s e t -V

m V - Reference Voltage - V

REF ADS8284

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TYPICAL CHARACTERISTICS (continued)

INTEGRAL NONLINEARITY

REFERENCE VOLTAGE

OPA SUPPLY VOLTAGE (+VCC)

MULTIPLEXER CHANNELS

Figure 27.

Figure 28.

Figure 29.

FULL CHIP OFFSET ERROR

FREE-AIR TEMPERATURE

OPA SUPPLY VOLTAGE (VCC)

ANALOG SUPPLY VOLTAGE (+VA)

Figure 30.

Figure 31.

Figure 32.

FULL CHIP OFFSET ERROR

FULL CHIP GAIN ERROR

vs vs

REFERENCE VOLTAGE

CHANNEL

FREE-AIR TEMPERATURE

Figure 33.Figure 34.Figure 35.

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