Microinstruction Format SELECT: Indicates the source of the next address
(absolute or a derived address)
p
ADDR: Specifies an absolute address
Very Simple CPU State Diagram ‘To
sequence
g
through
these states
and to
generate the
μ‐ops
For that
state’
A Very Simple Microsequencer Size of micro
code memory?
Register?
Mux. In/out?
Mapping Logic
Preliminary Horizontal Microcode ‘μ‐ops field’ in micro instruction accommodates all μ‐ops
Optimized Horizontal Microcode ARDR and IRDR has the same value in all states ‐combine
Control Signals
‘Derived from the RTL code of all the states’
Control Signals
Generic Vertical Microcode
Decoding
‘Lots of zeros
‘Lots of zeros
in horizontal
μcode -most
are inactive’
Grouped into
fields: no more
fi ld
than one μ-op
in a field is
active in a
state
Micro--operation Generation Micro
Nanoinstructions
128 μ-instructions with 32 μ-
operations need 128*32bits.
16 unique combinations: nano-
memory 16*32,
Access these 16 locations
using 4-bits.
Microcode memory is then
128*4
Final Register Section