Features
x 128K x 36, 256K x 18 memory configurations x
Supports fast access times:Commercial:
–7.5ns up to 117MHz clock frequency Commercial and Industrial:
–8.0ns up to 100MHz clock frequency –8.5ns up to 87MHz clock frequency
x LBO input selects interleaved or linear burst mode
x
Self-timed write cycle with global write control (GW ), byte write enable (BWE ), and byte writes (BW x)x 3.3V core power supply
x Power down controlled by ZZ input x 2.5V I/O
x
Optional - Boundary Scan JTAG Interface (IEEE 1149.1compliant)
x
Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA)
Pin Description Summary
Description
The IDT71V2577/79 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V2577/79 SRAMs contain write, data,address and control registers. There are no registers in the data output path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle.
The burst mode feature offers the highest level of performance to the system designer, as the IDT71V2577/79 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edge of the same cycle. If burst mode operation is selected (ADV =LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin.
The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA).
A 0-A 17Address Inputs Input Synchronous CE Chip Enable Input Synchronous CS 0, CS 1Chip Selects Input Synchronous OE Output Enable Input Asynchronous GW Global Write Enable Input Synchronous BWE
Byte Write Enable
Input Synchronous BW 1, BW 2, BW 3, BW 4(1)Individual Byte Write Selects Input Synchronous
CLK Clock
Input N/A ADV Burst Address Advance Input Synchronous ADSC Address Status (Cache Controller)Input Synchronous ADSP Address Status (Processor)Input Synchronous
LBO Linear / Interleaved Burst Order Input DC TMS Test Mode Select Input Synchronous TDI Test Data Input Input Synchronous
TCK Test Clock Input N/A TDO Test Data Output Output Synchronous TRST JTAG Reset (Optional)Input Asynchronous ZZ
Sleep Mode Input Asynchronous I/O 0-I/O 31, I/O P1-I/O P4Data Input / Output I/O Synchronous
V DD , V DDQ Core Power, I/O Power Supply N/A V SS
Ground
Supply
N/A
128K x 36, 256K x 18
3.3V Synchronous SRAMs
2.5V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
IDT71V2577S IDT71V2579S IDT71V2577SA IDT71V2579SA
Pin Definition (1)
NOTE:
1.All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol Pin Function I/O Active Description
A 0-A 17Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK and ADSC Low or ADSP Low and CE Low.
ADSC Address Status (Cache Controller)I LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the address registers with new addresses.
ADSP Address Status (Processor)I LOW Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address registers with new addresses. ADSP is gated by CE .
ADV
Burst Address Advance I
LOW
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not incremented; that is, there is no address advance.
BWE Byte Write Enable
I LOW
Synchronous byte write enable gates the byte write inputs BW 1-BW 4. If BWE is LOW at the rising edge of CLK then BW x inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
BW 1-BW 4
Individual Byte Write Enables I LOW Synchronous byte write enables. BW 1 controls I/O 0-7, I/O P1, BW 2 controls I/O 8-15, I/O P2, etc. Any active byte write causes all outputs to be disabled.
CE Chip Enable I LOW Synchronous chip enable. CE is used with CS 0 and CS 1 to enable the IDT71V2577/79. CE also gates ADSP .
CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this input.CS 0Chip Select 0I HIGH Synchronous active HIGH chip select. CS 0 is used with CE and CS 1 to enable the chip.CS 1Chip Select 1I LOW Synchronous active LOW chip select. CS 1 is used with CE and CS 0 to enable the chip.
GW Global Write Enable I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of CLK. GW supersedes individual byte write enables.
I/O 0-I/O 31I/O P1-I/O P4Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data output path is flow-through (no output register).
LBO
Linear Burst Order
I
LOW
Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst sequence is
selected. When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state while the device is operating.
OE Output Enable I LOW Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
TMS Test ModeSelect I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.TDI T est Data Input I N/A Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal pullup.
TCK Test Clock I N/A Clock input of TAP controller. Each TAP event is clocked. T est inputs are captured on rising edge of TCK,while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TDO
Test DataOutput O
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the T AP controller.
TRST JT AG Reset (Optional)
I LOW
Optional Asynchronous JTAG reset. Can be used to reset the T AP controller, but not required. JT AG reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can be left floating. This pin has an internal pullup. Only available in BGA package.
ZZ Sleep Mode I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V2577/79to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull down.
V DD Power Supply N/A N/A 3.3V core power supply.V DDQ Power Supply N/A N/A 2.5V I/O Supply.V SS Ground N/A N/A Ground.
NC
No Connect
N/A
N/A
NC pins are not electrically connected to the device.
4877 tbl 02
Functional Block Diagram
A 0-A
BW BW BW BW CS CS I/O 0-I/O I/O P1-I/O 4877drw 01
ZZ
TMS TDI TCK TRST (Optional)
TDO
100 Pin TQFP Capacitance (T A = +25°C, f = 1.0MHz)Recommended DC Operating Conditions
Recommended Operating Temperature and Supply Voltage
Absolute Maximum Ratings(1)
NOTES:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.V DD terminals only.
3.V DDQ terminals only.
4.Input terminals only.
5.I/O terminals only.
6.This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage on any input or I/O pin cannot exceed V DDQ during power supply ramp up.
7.TA is the “instant on” case temperature.NOTES:
1.V IH (max) = V DDQ + 1.0V for pulse width less than t CYC/2, once per cycle.
2.V IL (min) = -1.0V for pulse width less than t CYC/2, once per cycle.
Symbol Rating
Commerical & Industrial Values
Unit
V TERM(2)T erminal Voltage with
Respect to GND
-0.5 to +4.6V
V TERM(3,6)T erminal Voltage with
Respect to GND
-0.5 to V DD V
V TERM(4,6)T erminal Voltage with
Respect to GND
-0.5 to V DD +0.5V
V TERM(5,6)T erminal Voltage with
Respect to GND
-0.5 to V DDQ +0.5V
T A(7)Commercial
Operating T emperature
-0 to +70o C
Industrial
Operating T emperature
-40 to +85o C
T BIAS T emperature
Under Bias
-55 to +125o C
T STG Storage
T emperature
-55 to +125o C P T Power Dissipation 2.0W I OUT DC Output Current50mA
4877 tbl 03
Grade Temperature(1)V SS V DD V DDQ Commercial0°C to +70°C0V 3.3V±5% 2.5V±5% Industrial-40°C to +85°C0V 3.3V±5% 2.5V±5%
4877 tbl 04
Symbol Parameter Min.Typ.Max.Unit V DD Core Supply Voltage 3.135 3.3 3.465V V DDQ I/O Supply Voltage 2.375 2.5 2.625V V SS Supply Voltage000V V IH Input High Voltage - Inputs 1.7____V DD + 0.3V V IH Input High Voltage - I/O 1.7____V DDQ + 0.3(1)V V IL Input Low Voltage-0.3(2)____0.7V
4877 tbl 05
Symbol Parameter(1)Conditions Max.Unit C IN Input Capacitance V IN = 3dV5pF C I/O I/O Capacitance V OUT = 3dV7pF
4877 tbl 07119 BGA Capacitance
(T A = +25°C, f = 1.0MHz)
Symbol Parameter(1)Conditions Max.Unit
C IN Input Capacitance V IN = 3dV7pF
C I/O I/O Capacitance V OUT = 3dV7pF
4877 tbl 07a NOTES:
1.TA is the “instant on” case temperature.
165 fBGA Capacitance
(T A = +25°C, f = 1.0MHz)
Symbol Parameter(1)Conditions Max.Unit
C IN Input Capacitance V IN = 3dV7pF
C I/O I/O Capacitance V OUT = 3dV7pF
4877 tbl 07b
Pin Configuration 128K x 36
100 TQFP Top View
NOTES:
1.Pin 14 does not have to be directly connected to V SS as long as the input voltage is < V IL .
2.Pin 64 can be left unconnected and the device will always remain in active mode.
6
7
C E S 0
B W 4
B W 3
B W 2
B W 1
C S 1
D D
S S
C L K W B W E O E A
D S C A D S P A D V 8
9
I/O I/O I/O V V I/O I/O I/O I/O V V I/O I/O V SS V I/O I/O V V I/O I/O I/O I/O V V I/O I/O I/O I/O P2I/O 14V DDQ V SS I/O 13I/O 12I/O 11I/O 10V SS V DDQ I/O 9I/O 8V SS NC V DD ZZ (2)I/O 7I/O 6V DDQ V SS I/O 5I/O 4I/O 3I/O 2V SS V DDQ I/O 1I/O 0I/O P1
V I/O 15drw 02a
Pin Configuration 256K x 18
100 TQFP Top View
NOTES:
1.Pin 14 does not have to be directly connected to V SS as long as the input voltage is < V IL .
2.Pin 64 can be left unconnected and the device will always remain in active mode.
A 17
N C N C L B O A 15
A 14
A 13
A 12
A 11
V D D
V S S
A 0
A 1
A 2
A 3
A 4
A 5
V V I/O I/O I/O V V I/O I/O V V I/O I/O V V I/O I/O V V A 10NC V DDQ V SS NC I/O P1I/O 7I/O 6V SS V DDQ I/O 5I/O 4V SS NC V DD ZZ (2)I/O 3I/O 2V DDQ V SS I/O 1I/O 0NC NC V SS V DDQ NC NC NC
V SS NC A 16
02b
N C N C
Pin Configuration 256K x 18, 119 BGA
Pin Configuration 128K x 36, 119 BGA
Top View
Top View
NOTES:
1.R5 does not have to be directly connected to V SS as long as the input voltage is < V IL .
2.These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to V SS , V DD or left floating.
3. T7 can be left unconnected and the device will always remain in active mode.
1
234567A V DDQ A 6A 4ADSP A 8A 16V DDQ B NC CS 0A 3ADSC A 9CS 1NC C A 7A 2V DD A 12A 15NC D I/O 16I/O P3V SS NC V SS I/O P2I/O 15E I/O 17I/O 18V SS CE V SS I/O 13I/O 14F V DDQ I/O 19V SS OE V SS I/O 12V DDQ G I/O 20I/O 21BW 3ADV BW 2I/O 11I/O 10H I/O 22I/O 23V SS GW V SS I/O 9I/O 8J V DDQ V DD NC V DD NC V DD V DDQ K I/O 24I/O 26V SS CLK V SS I/O 6I/O 7L I/O 25I/O 27BW 4NC BW 1I/O 4I/O 5M V DDQ I/O 28V SS BWE V SS I/O 3V DDQ N I/O 29I/O 30V SS A 1V SS I/O 2I/O 1P I/O 31I/O P4V SS A 0V SS I/O 0I/O P1R NC A 5LBO V DD NC A 13T NC NC
A 10
A 11
A 14NC
ZZ (3)
U
V DDQ
V DDQ
NC V SS 4877drw 02c
NC/TMS (2)NC/TDI (2)NC/TCK (2)NC/TDO (2)
NC/TRST (2,4)1
234567A V DDQ A 6A 4ADSP A 8A 16V DDQ B NC CS 0A 3ADSC A 9CS 1NC C A 7A 2V DD A 13A 17NC D I/O 8NC V SS NC V SS I/O 7NC E NC I/O 9V SS CE V SS NC I/O 6F V DDQ NC V SS OE V SS I/O 5V DDQ G NC I/O 10ADV BW 2NC I/O 4H I/O 11NC V SS GW V SS I/O 3NC J V DDQ V DD NC V DD NC V DD V DDQ K NC I/O 12V SS CLK V SS NC I/O 2L I/O 13NC NC BW 1I/O 1NC M V DDQ I/O 14V SS BWE V SS NC V DDQ N I/O 15NC V SS A 1V SS I/O 0NC P NC I/O P2V SS A 0V SS NC I/O P1R NC A 5LBO V DD NC A 12V SS T NC A 10
A 15
NC
A 14
A 11
ZZ (3)
U
V DDQ
V DDQ
4877drw 02d
NC V SS V SS NC/TMS (2)NC/TDI (2)NC/TCK (2)NC/TDO (2)NC/TRST (2,4)
Pin Configuration 256K x 18, 165 fBGA
Pin Configuration 128K x 36, 165 fBGA
NOTES:
1.H1 does not have to be directly V SS as long as input voltage is < V IL .
2.These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to V SS , V DD or left floating.
3.H11 can be left unconnected and the device will always remain in active mode.
4.Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.
1
234567891011A NC (4)A 7CE 1BW 3BW 2CS 1BWE ADSC ADV A 8NC B NC A 6CS 0BW 4BW 1CLK GW OE ADSP A 9NC (4)C I/O P3NC V DDQ V SS V SS V SS V SS V SS V DDQ NC I/O P2D I/O 17I/O 16V DDQ V DD V SS V SS V SS V DD V DDQ I/O 15I/O 14E I/O 19I/O 18V DDQ V DD V SS V SS V SS V DD V DDQ I/O 13I/O 12F I/O 21I/O 20V DDQ V DD V SS V SS V SS V DD V DDQ I/O 11I/O 10G I/O 23I/O 22V DDQ V DD V SS V SS V SS V DD V DDQ I/O 9I/O 8H V SS (1)NC NC V DD V SS V SS V SS V DD NC NC ZZ (3)J I/O 25I/O 24V DDQ V DD V SS V SS V SS V DD V DDQ I/O 7I/O 6K I/O 27I/O 26V DDQ V DD V SS V SS V SS V DD V DDQ I/O 5I/O 4L I/O 29I/O 28V DDQ V DD V SS V SS V SS V DD V DDQ I/O 3I/O 2M I/O 31I/O 30V DDQ V DD V SS
V SS V SS V DD V DDQ I/O 1I/O 0N I/O P4NC V DDQ V SS NC/TRST (2,5)
NC (4)NC V SS V DDQ NC I/O P1P NC NC (4)A 5A 2NC/TDI (2)A 1NC/TDO (2)A 10A 13A 14NC (4)R
LBO
NC (4)
A 4
A 3
NC/TMS (2)
A 0
NC/TCK (2)
A 11
A 12
A 15
A 16
4877 tbl 17
1
234567891011A NC (4)A 7CE BW 2NC CS 1BWE ADSC ADV A 8A 10B NC A 6CS 0NC BW 1CLK GW OE ADSP A 9NC (4)C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC I/O P1D NC I/O 8V DDQ V DD V SS V SS V SS V DD V DDQ NC I/O 7E NC I/O 9V DDQ V DD V SS V SS V SS V DD V DDQ NC I/O 6F NC I/O 10V DDQ V DD V SS V SS V SS V DD V DDQ NC I/O 5G NC I/O 11V DDQ V DD V SS V SS V SS V DD V DDQ NC I/O 4H V SS (1)NC NC V DD V SS V SS V SS V DD NC NC ZZ (3)J I/O 12NC V DDQ V DD V SS V SS V SS V DD V DDQ I/O 3NC K I/O 13NC V DDQ V DD V SS V SS V SS V DD V DDQ I/O 2NC L I/O 14NC V DDQ V DD V SS V SS V SS V DD V DDQ I/O 1NC M I/O 15NC V DDQ V DD V SS
V SS V SS V DD V DDQ I/O 0NC N I/O P2NC V DDQ V SS NC/TRST (2,5)
NC (4)NC V SS V DDQ NC NC P NC NC (4)A 5A 2NC/TDI (2)A 1NC/TDO (2)A 11A 14A 15NC (4)R
LBO
NC (4)
A 4
A 3
NC/TMS (2)
A 0
NC/TCK (2)
A 12
A 13
A 16
A 17
4877 tbl 17a
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (V DD = 3.3V ± 5%)
AC Test Conditions
(V DDQ = 2.5V)
NOTE:
1.The LBO, TMS, TDI, TCK, and TRST pins will be internally pulled to V DD and the ZZ pin will be internally pulled to V SS if they are not actively driven in the application.
NOTES:
1.All values are maximum guaranteed values.
2.At f = f MAX, inputs are cycling at the maximum frequency of read cycles of 1/t CYC while ADSC = LOW; f=0 means no input lines are changing.
3.For I/Os V HD = V DDQ - 0.2V, V LD = 0.2V. For other inputs V HD = V DD - 0.2V, V LD = 0.2V.
4877d03
Sym bol Param eter
Test Conditions
Min.
Max.Unit |I LI |Input Le akag e Curre nt
V DD = M ax., V IN = 0V to V DD ___
5μA |I L I |ZZ, LBO and JTA G Input Leakag e Curre nt (1)V DD = M ax., V IN = 0V to V DD
___30μA |I LO |Outp ut Leakag e Curre nt V O UT = 0V to V DDQ , De vice De se le cted ___5μA V O L Outp ut Low Vo ltag e I O L = +6m A, V DD = M in.___
0.4
V V OH
Outp ut Hig h Vo ltag e
I OH = -6m A, V DD = M in.
2.0
___
V
4877 tb l 08
Symbol Parameter
Test Conditions
7.5ns
8ns 8.5ns Unit Com'l Only
Com'l Ind Com'l Ind I DD Operating Power Supply Current Device Selected, Outputs Open, V DD = Max.,V DDQ = Max., V IN > V IH or < V IL , f = f MAX (2)255200210180190mA I SB1CMOS Standby Power Supply Current
Device Deselected, Outputs Open, V DD = Max.,V DDQ = Max., V IN > V HD or < V LD , f = 0(2,3)3030353035mA I SB2Clock Running Power Supply Current
Device Deselected, Outputs Open, V DD = Max.,V DDQ = Max., V IN > V HD or < V LD , f = f MAX (2,3)9085958090mA I ZZ
Full Sleep Mode Supply Current
ZZ > V HD, V DD = Max.
30
30
35
30
35
mA
4877 tbl 09
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Timing Reference Levels AC T est Load
0 to 2.5V 2ns (V DDQ /2)(V DDQ /2)See Figure 1
4877 tbl 10
203050
100
200
?tCD (Typical,ns)
Capacitance (pF)
804877d05
Synchronous Truth Table (1,3)
NOTES:
1.L = V IL , H = V IH , X = Don’t Care.Operation
Address Used CE CS 0CS 1ADSP ADSC ADV GW BWE BW x OE (2)CLK I/O Deselected Cycle, Power Down None H X X X L X X X X X ↑HI-Z Deselected Cycle, Power Down None L X H L X X X X X X ↑HI-Z Deselected Cycle, Power Down None L L X L X X X X X X ↑HI-Z Deselected Cycle, Power Down None L X H X L X X X X X ↑HI-Z Deselected Cycle, Power Down None L L X X L X X X X X ↑HI-Z Read Cycle, Begin Burst External L H L L X X X X X L ↑D OUT Read Cycle, Begin Burst External L H L L X X X X X H ↑HI-Z Read Cycle, Begin Burst External L H L H L X H H X L ↑D OUT Read Cycle, Begin Burst External L H L H L X H L H L ↑D OUT Read Cycle, Begin Burst External L H L H L X H L H H ↑HI-Z Write Cycle, Begin Burst External L H L H L X H L L X ↑D IN Write Cycle, Begin Burst External L H L H L X L X X X ↑D IN Read Cycle, Continue Burst Next X X X H H L H H X L ↑D OUT Read Cycle, Continue Burst Next X X X H H L H H X H ↑HI-Z Read Cycle, Continue Burst Next X X X H H L H X H L ↑D OUT Read Cycle, Continue Burst Next X X X H H L H X H H ↑HI-Z Read Cycle, Continue Burst Next H X X X H L H H X L ↑D OUT Read Cycle, Continue Burst Next H X X X H L H H X H ↑HI-Z Read Cycle, Continue Burst Next H X X X H L H X H L ↑D OUT Read Cycle, Continue Burst Next H X X X H L H X H H ↑HI-Z Write Cycle, Continue Burst Next X X X H H L H L L X ↑D IN Write Cycle, Continue Burst Next X X X H H L L X X X ↑D IN Write Cycle, Continue Burst Next H X X X H L H L L X ↑D IN Write Cycle, Continue Burst Next H X X X H L L X X X ↑D IN Read Cycle, Suspend Burst Current X X X H H H H H X L ↑D OUT Read Cycle, Suspend Burst Current X X X H H H H H X H ↑HI-Z Read Cycle, Suspend Burst Current X X X H H H H X H L ↑D OUT Read Cycle, Suspend Burst Current X X X H H H H X H H ↑HI-Z Read Cycle, Suspend Burst Current H X X X H H H H X L ↑D OUT Read Cycle, Suspend Burst Current H X X X H H H H X H ↑HI-Z Read Cycle, Suspend Burst Current H X X X H H H X H L ↑D OUT Read Cycle, Suspend Burst Current H X X X H H H X H H ↑HI-Z Write Cycle, Suspend Burst Current X X X H H H H L L X ↑D IN Write Cycle, Suspend Burst Current X X X H H H L X X X ↑D IN Write Cycle, Suspend Burst Current H X X X H H H L L X ↑D IN Write Cycle, Suspend Burst Current
H
X
X
X
H
H
L
X
X
X
↑
D IN
4877 tbl 11
Linear Burst Sequence Table (LBO =V SS )
Synchronous Write Function Truth Table (1, 2)
Asynchronous Truth Table (1)
Interleaved Burst Sequence Table (LBO =V DD )
NOTES:
1.L = V IL , H = V IH , X = Don’t Care.
2.BW 3 and BW 4 are not applicable for the IDT71V2579.
3.Multiple bytes may be selected during the same cycle.
NOTES:
1.L = V IL , H = V IH , X = Don’t Care.
2.Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1.Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
Operation GW BWE BW 1BW 2BW 3BW 4Read H H X X X X Read H L H H H H Write all Bytes L X X X X X Write all Bytes H L L L L L Write Byte 1(3)H L L H H H Write Byte 2(3)H L H L H H Write Byte 3(3)H L H H L H Write Byte 4(3)
H
L
H
H
H
L
4877 tbl 12
Operation (2)
OE ZZ I/O Status Power Read L L Data Out Active Read H L High-Z Active Write
X L High-Z – Data In
Active Deselected
X L High-Z Standby Sleep Mode
X
H
High-Z
Sleep
4877 tbl 13
Sequence 1Sequence 2Sequence 3Sequence 4A1
A0A1A0A1A0A1A0First Address 00011011Second Address 01001110Third Address 10110001Fourth Address (1)
1
1
1
1
4877 tbl 14
Sequence 1Sequence 2Sequence 3Sequence 4A1
A0A1A0A1A0A1A0First Address 00011011Second Address 01101100Third Address 10110001Fourth Address (1)
1
1
1
1
4877 tbl 15
AC Electrical Characteristics
(V DD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
7.5ns(5)8ns8.5ns
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit Clock Parameter
t CYC Clock Cycle Time8.5____10____11.5____ns t CH(1)Clock High Pulse Width3____4____ 4.5____ns t CL(1)Clock Low Pulse Width3____4____ 4.5____ns Output Parameters
t CD Clock High to Valid Data____7.5____8____8.5ns t CDC Clock High to Data Change2____2____2____ns t CLZ(2)Clock High to Output Active0____0____0____ns t CHZ(2)Clock High to Data High-Z2 3.52 3.52 3.5ns t OE Output Enable Access Time____ 3.5____ 3.5____ 3.5ns t OLZ(2)Output Enable Low to Output Active0____0____0____ns t OHZ(2)Output Enable High to Output High-Z____ 3.5____ 3.5____ 3.5ns Set Up Times
t SA Address Setup Time 1.5____2____2____ns t SS Address Status Setup Time 1.5____2____2____ns t SD Data In Setup Time 1.5____2____2____ns t SW Write Setup Time 1.5____2____2____ns t SAV Address Advance Setup Time 1.5____2____2____ns t SC Chip Enable/Select Setup Time 1.5____2____2____ns Hold Times
t HA Address Hold Time0.5____0.5____0.5____ns t HS Address Status Hold Time0.5____0.5____0.5____ns t HD Data In Hold Time0.5____0.5____0.5____ns t HW Write Hold Time0.5____0.5____0.5____ns t HAV Address Advance Hold Time0.5____0.5____0.5____ns t HC Chip Enable/Select Hold Time0.5____0.5____0.5____ns Sleep Mode and Configuration Parameters
t ZZPW ZZ Pulse Width100____100____100____ns t ZZR(3)ZZ Recovery Time100____100____100____ns t CFG(4)Configuration Set-up Time34____40____50____ns
4877 tbl 16 NOTES:
1.Measured as HIGH above V IH and LOW below V IL.
2.Transition is measured ±200mV from steady-state.
3.Device must be deselected when powered-up from sleep mode.
4.t CFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
Timing Waveform of Flow-Through Read Cycle (1,2)
B W E ,B W x
C L K A
D S P
A D S C
A D D R E S S O E
D A T A O U T
A D V
C E ,C S 1
(N o t e 3)
R e a d
4877d r w 06
N O T E S :1.O 1 (A x ) r e p r e s e n t s t h e f i r s t o u t p u t f r o m t h e e x t e r n a l a d d r e s s A x . O 1 (A y ) r e p r e s e n t s t h e f i r s t o u t p u t f r o m t h e e x t e r n a l a d d r e s s A y ; O 2 (A y ) r e p r e s e n t s t h e n e x t o u t p u t d a t a i n t h e b u r s t s e q u e n c e o f t h e b a s e a d d r e s s A y , e t c . w h e r e A 0 a n d A 1 a r e a d v a n c i n g f o r t h e f o u r w o r d b u r s t i n t h e s e q u e n c e d e f i n e d b y t h e s t a t e o f t h e L B O i n p u t.2.Z Z i n p u t i s L O W a n d L B O i s D o n 't C a r e f o r t h i s c y c l e .3.C S 0 t i m i n g t r a n s i t i o n s a r e i d e n t i c a l b u t i n v e r t e d t o t h e C E a n d C S 1 s i g n a l s . F o r e x a m p l e , w h e n C E a n d C S 1 a r e L O W o n t h i s w a v e f o r m , C S 0 i s H I G H .
Timing Waveform of Combined Flow-Through Read and Write Cycles (1,2,3)
C L K A
D S P
D D R
E S S
G W
A D V
O E D A T A O U T
D A T A I N
N O T E S :
1.D e v i c e i s s e l e c t e d t h r o u g h e n t i r e c y c l e ; C E a n d C S 1 a r e L O W , C S 0 i s H I G H .
2.Z Z i n p u t i s L O W a n d L B O i s D o n 't C a r e f o r t h i s c y c l e .
3.O 1 (A x ) r e p r e s e n t s t h e f i r s t o u t p u t f r o m t h e e x t e r n a l a d d r e s s A x . I 1 (A y ) r e p r e s e n t s t h e f i r s t i n p u t f r o m t h e e x t e r n a l a d d r e s s A y ; O 1 (A z ) r e p r e s e n t s t h e f i r s t o u t p u t f r o m t h e e x t e r n a l a d d r e s s A z ; O 2 (A z ) r e p r e s e n t s t h e n e x t o u t p u t d a t a i n t h e b u r s t s e q u e n c e o f t h e b a s e a d d r e s s A z , e t c . w h e r e A 0 a n d A 1 a r e a d v a n c i n g f o r t h e f o u r w o r d b u r s t i n t h e s e q u e n c e d e f i n e d b y t h e s t a t e o f t h e L B O i n p u t.
Timing Waveform of Write Cycle No. 1 - GW Controlled (1,2,3)
D D R
E S S
C L K
A D S P
A D S C
A D V
D A T A O U T O E
D A T A I N
C E ,C S 1
G W
(N o t e 3)
N O T E S :
1.Z Z i n p u t i s L O W , B W E i s H I G H a n d L B O i s D o n 't C a r e f o r t h i s c y c l e .
2.O 4 (A w ) r e p r e s e n t s t h e f i n a l o u t p u t d a t a i n t h e b u r s t s e q u e n c e o f t h e b a s e a d d r e s s A w . I 1 (A x ) r e p r e s e n t s t h e f i r s t i n p u t f r o m t h e e x t e r n a l a d d r e s s A x . I 1 (A y ) r e p r e s e n t s t h e f i r s t i n p u t f r o m t h e e x t e r n a l a d d r e s s A y ; I 2 (A y ) r e p r e s e n t s t h e n e x t i n p u t d a t a i n t h e b u r s t s e q u e n c e o f t h e b a s e a d d r e s s A y , e t c . w h e r e A 0 a n d A 1 a r e a d v a n c i n g f o r t h e f o u r w o r d b u r s t i n t h e s e q u e n c e d e f i n e d b y t h e s t a t e o f t h e L B O i n p u t. I n t h e c a s e o f i n p u t I 2 (A y ) t h i s d a t a i s v a l i d f o r t w o c y c l e s b e c a u s e A D V i s h i g h a n d h a s s u s p e n d e d t h e b u r s t.
3.C S 0 t i m i n g t r a n s i t i o n s a r e i d e n t i c a l b u t i n v e r t e d t o t h e C E a n d C S 1 s i g n a l s . F o r e x a m p l e , w h e n C E a n d C S 1 a r e L O W o n t h i s w a v e f o r m , C S 0 i s H I G H .
Timing Waveform of Write Cycle No. 2 - Byte Controlled (1,2,3)
D D R
E S S C L K A D S P
A D S C
B W x
A D V
D A T A O U T
O E
D A T A I N C
E ,C S 1
B W E
(N o t e 3)
4877d r w 09
N O T E S :1.Z Z i n p u t i s L O W , G W i s H I G H a n d L B O i s D o n 't C a r e f o r t h i s c y c l e .2.O 4 (A w ) r e p r e s e n t s t h e f i n a l o u t p u t d a t a i n t h e b u r s t s e q u e n c e o f t h e b a s e a d d r e s s A w . I 1 (A x ) r e p r e s e n t s t h e f i r s t i n p u t f r o m t h e e x t e r n a l a d d r e s s A x . I 1 (A y ) r e p r e s e n t s t h e f i r s t i n p u t f r o m t h e e x t e r n a l a d d r e s s A y ; I 2 (A y ) r e p r e s e n t s t h e n e x t i n p u t d a t a i n t h e b u r s t s e q u e n c e o f t h e b a s e a d d r e s s A y , e t c . w h e r e A 0 a n d A 1 a r e a d v a n c i n g f o r t h e f o u r w o r d b u r s t i n t h e s e q u e n c e d e f i n e d b y t h e s t a t e o f t h e L B O i n p u t. I n t h e c a s e o f i n p u t I 2 (A y ) t h i s d a t a i s v a l i d f o r t w o c y c l e s b e c a u s e A D V i s h i g h a n d h a s s u s p e n d e d t h e b u r s t.3.C S 0 t i m i n g t r a n s i t i o n s a r e i d e n t i c a l b u t i n v e r t e d t o t h e C E a n d C S 1 s i g n a l s . F o r e x a m p l e , w h e n C E a n d C S 1 a r e L O W o n t h i s w a v e f o r m , C S 0 i s H I G H .
C L K A
D S P
A D S C
D D R
E S S G W
C E ,C S 1
A D V
D A T A O U T
O E
Z Z
4877d r w 13
(N o t e 4)
N O T E S :
1. D e v i c e m u s t p o w e r u p i n d e s e l e c t e d M o d e
2. L B O i s D o n 't C a r e f o r t h i s c y c l e .
3. I t i s n o t n e c e s s a r y t o r e t a i n t h e s t a t e o f t h e i n p u t r e g i s t e r s t h r o u g h o u t t h e P o w e r -d o w n c y c l e .
4. C S t i m i n g t r a n s i t i o n s a r e i d e n t i c a l b u t i n v e r t e d t o t h e C E a n d C S 1 s i g n a a l s . F o r e x a m p l e , w h e n C E a n d C S 1 a r e L O W o n t h i s w a v e f o r m , C S 0 i s H I G H .
Timing Waveform of Sleep (ZZ) and Power-Down Modes (1,2,3)
N on-Burst Write Cycle Timing Waveform
CLK
ADSP
GW
CE,CS 1
CS 0
ADDRESS
ADSC
DATA IN
4877drw 11
NOTES:
1.ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
CLK
ADSP
GW,BWE,BWx
CE,CS 1
CS 0
ADDRESS
ADSC
DATA OUT
OE
4877drw 10
NOTES:
1.ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2.(Ax) represents the data for address Ax, etc.
3.For read cycles, ADSP and ADSC function identically and are therefore interchangable.
JTAG Interface Specification (SA Version only)
TCK
Device Inputs (1)/
TDI/TMS
Device Outputs (2)/
TDO
Symbol Parameter Min.Max.
Units t JCYC JT AG Clock Input Period 100____ns t JCH JT AG Clock HIGH 40____ns t JCL JT AG Clock Low 40
____
ns t JR JT AG Clock Rise Time ____5(1)ns t JF JT AG Clock Fall Time
____
5(1)
ns t JRST JT AG Reset 50____ns t JRSR JT AG Reset Recovery 50
____
ns t JCD JT AG Data Output ____
20
ns t JDC JT AG Data Output Hold
0____ns t JS JT AG Setup 25____ns t JH
JT AG Hold
25
____
ns
I4877 tbl 01
Register Name
Bit Size Instruction (IR)4Bypass (BYR)
1JT AG Identification (JIDR)32Boundary Scan (BSR)
Note (1)
I4877 tbl 03
NOTES:
1.Device inputs = All device inputs except TDI, TMS and TRST .
2.Device outputs = All device outputs except TDO.
3.During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
NOTE:
1.The Boundary Scan Descriptive Language (BSDL) file for this device is available by contacting your local IDT sales representative.
JTAG AC Electrical Characteristics (1,2,3,4)
Scan Register Sizes
NOTES:
1.Guaranteed by design.
2.AC Test Load (Fig. 1) on external output signals.
3.Refer to AC Test Conditions stated earlier in this document.
4.JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
NOTES:
1.Device outputs = All device outputs except TDO.
2.Device inputs = All device inputs except TDI, TMS, and TRST .
Instruction Field
Value Description
Revision Number (31:28)0x2Reserved for version number.
IDT Device ID (27:12)0x22D, 0x22F
Defines IDT part number 71V2577SA and 71V2579SA, respectively.IDT JEDEC ID (11:1)0x33Allows unique identification of device vendor as IDT .ID Register Indicator Bit (Bit 0)
1
Indicates the presence of an ID register.
I4877 tbl 02
JTAG Identification Register Definitions (SA Version only)
Instruction
Description
OPCODE EXTEST
Forces contents of the boundary scan cells onto the device outputs (1).Places the boundary scan register (BSR) between TDI and TDO.0000
SAMPLE/PRELOAD Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs (2) and outputs (1) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI.0001
DEVICE_ID Loads the JTAG ID register (JIDR) with the vendor ID code and places the register between TDI and TDO.
0010HIGHZ Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state.
0011RESERVED Several combinations are reserved. Do not use codes other than those identified for EXTEST , SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,VALIDATE and BYPASS instructions.
0100
RESERVED 0101RESERVED 0110RESERVED 0111
CLAMP Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the bypass register (BYR) between TDI and TDO.
1000RESERVED Same as above.
1001
RESERVED 1010RESERVED 1011RESERVED 1100
VALIDATE Automatically loaded into the instruction register whenever the T AP
controller passes through the CAPTURE-IR state. The lower two bits '01'are mandated by the IEEE std. 1149.1 specification.1101RESERVED Same as above.
1110BYPASS
The BYPASS instruction is used to truncate the boundary scan register as a single bit in length.
1111
I4877 tbl 04
Available JTAG Instructions