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MSM511666CL-60TS-K中文资料

DESCRIPTION

The MSM511666C/CL is a 65,536-word ￥ 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM511666C/CL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM511666C/CL is available in a 40-pin plastic SOJ or 44/40-pin plastic TSOP. The MSM511666CL (the low-power version) is specially designed for lower-power applications.

FEATURES

?65,536-word ￥ 16-bit configuration

?Single 5 V power supply, ±10% tolerance ?Input : TTL compatible, low input capacitance ?Output : TTL compatible, 3-state

?Refresh : 256 cycles/4 ms, 256 cycles/32 ms (L-version)

?Byte write and fast page mode with EDO, read modify write capability ?CAS before RAS refresh, hidden refresh, RAS -only refresh capability ?Package options:

40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27)(Product : MSM511666C/CL-xxJS)44/40-pin 400 mil plastic TSOP (TSOPII44/40-P-400-0.80-K)(Product : MSM511666C/CL-xxTS-K)

xx indicates speed rank.

PRODUCT FAMILY

MSM511666C/CL

65,536-Word ￥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO (BYTE WRITE)

MSM511666C/CL-70

70 ns 120 ns

110 ns 495 mW

550 mW Family

Access Time (Max.)Cycle Time (Min.)Standby (Max.)Power Dissipation MSM511666C/CL-60t RAC

60 ns 35 ns t AA

30 ns 20 ns t CAC

20 ns 20 ns

t OEA

20 ns Operating (Max.) 5.5 mW/

1.1 mW (L-version)

E2G0015-17-41

? Semiconductor MSM511666C/CL

PIN CONFIGURATION (TOP VIEW)

1234567891011121314151617181920

4039383736353433323130292827262524232221V CC DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8NC V CC UWE LWE RAS A0A1A2A3A4V CC V SS DQ16DQ15DQ14DQ13DQ12DQ11DQ10DQ9NC V SS CAS OE NC NC NC A7A6A5V SS

1V CC 40-Pin Plastic SOJ

44/40-Pin Plastic TSOP

(K Type)

V CC

2DQ13DQ24DQ35DQ46DQ57DQ68DQ79DQ810

13V CC 14UWE 15LWE 16RAS 17A018A119A220A321A444V SS 23

V SS

43DQ1642DQ1541DQ1440DQ1339DQ1238DQ1137DQ1036DQ935

32V SS 31CAS 30OE 29NC 28NC 27NC 26A725A624A5Note :

The same power supply voltage must be provided to every V CC pin, and the same GND voltage level must be provided to every V SS pin.

Pin Name Function

A0 - A7Address Input RAS Row Address Strobe CAS Column Address Strobe DQ1 - DQ16

Data Input/Data Output OE Output Enable

LWE Lower Byte Write Enable V CC Power Supply (5 V)NC

No Connection

UWE Upper Byte Write Enable V SS Ground (0 V)

? Semiconductor MSM511666C/CL

BLOCK DIAGRAM

A0 - A7

V CC

V SS

DQ1 - DQ16

FUNCTION TABLE

Function Mode

RAS H L Input Pin

CAS *H UWE LWE H L H OE L H L L L L L L H H L *****H Word Read Refresh Standby Lower Byte Write DQ Pin

DQ1 - DQ8

High-Z High-Z D IN DQ9 - DQ16

High-Z High-Z D OUT Don't Care D OUT Don't Care D IN

Upper Byte Write L L L L H D IN D IN Word Write

High-Z

—

**: "H" or "L"

? Semiconductor MSM511666C/CL

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Recommended Operating Conditions

Capacitance

*: Ta = 25°C

Voltage on Any Pin Relative to V SS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature

V T Symbol I OS P D *T opr T stg

–1.0 to 7.0

5010 to 70–55 to 150

Rating mA W °C °C

Parameter

V Unit Power Supply Voltage Input High Voltage Input Low Voltage

V CC Symbol V SS V IH V IL

5.00——

Typ.Parameter

4.502.4–1.0

Min. 5.506.50.8

Max.(Ta = 0°C to 70°C)

V Unit V V V

Input Capacitance (A0 - A7)Input Capacitance Output Capacitance (DQ1 - DQ16)

C IN1Symbol C IN2C I/O

777

Max.pF Unit pF pF

Parameter

(V CC = 5 V ±10%, Ta = 25°C, f = 1 MHz)

———

Typ.(RAS , CAS , UWE , LWE , OE )

? Semiconductor MSM511666C/CL

DC Characteristics

Parameter Symbol

Condition

MSM511666C/CL-70MSM511666C/CL-60(V CC = 5 V ±10%, Ta = 0°C to 70°C)

I OH = –2.5 mA Output High Voltage I OL = 2.1 mA

Output Low Voltage 0 V ￡ V I ￡ 6.5 V;All other pins not Input Leakage Current

under test = 0 V DQ disable Output Leakage Current 0 V ￡ V O ￡ 5.5 V RAS , CAS cycling,Average Power t RC = Min.Supply Current (Operating)RAS , CAS = V IH

Power Supply RAS , CAS

Current (Standby)RAS cycling,Average Power CAS = V IH ,

Supply Current t RC = Min.(RAS -only Refresh)RAS = V IH ,Power Supply CAS = V IL ,

Current (Standby)DQ = enable Average Power CAS before RAS Supply Current (CAS before RAS Refresh)RAS = V IL ,Average Power CAS cycling,

Supply Current t HPC = Min.(Fast Page Mode)t RC = 125 m s,Average Power V OH V OL I LI

I LO I CC1I CC2I CC3I CC5I CC6

I CC7I CC10CAS before RAS ,

Supply Current t RAS ￡ 1 m s

(Battery Backup)

≥ V CC –0.2 V Min.2.40

–10

–10————

—

Max.V CC 0.4

10902190

300

200

Min.

2.40

–10

–10————

—

Max.V CC 0.4

1010021100

100

300

200

Unit V V m A

m A

mA mA mA mA

mA mA m A

m A

Note

1, 2

11, 2

1, 2

1, 3

1, 4,5

1, 5

RAS cycling,Notes : 1.

I CC Max. is specified as I CC for output open condition.2.The address can be changed once or less while RAS = V IL .3.The address can be changed once or less while CAS = V IH .4.V CC – 0.2 V ￡ V IH ￡ 6.5 V, –1.0 V ￡ V IL ￡ 0.2 V.5.L-version.

? Semiconductor MSM511666C/CL

AC Characteristics (1/2)

Parameter

(V CC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3

Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time

Access Time from RAS Access Time from CAS

Access Time from Column Address Access Time from CAS Precharge RAS to Data Output Buffer Turn-off Delay Time Transition Time RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode with EDO)RAS Hold Time

CAS Pulse Width CAS Hold Time

RAS to CAS Delay Time

RAS to Column Address Delay Time CAS to RAS Precharge Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time

Column Address Hold Time from RAS Column Address to RAS Lead Time

Access Time from OE

OE to Data Output Buffer Turn-off Delay Time Refresh Period

RAS Hold Time referenced to OE

Unit RAS Hold Time from CAS Precharge Note Output Low Impedance Time from CAS CAS Precharge Time (Fast Page Mode with EDO)Refresh Period (L-version)Symbol

t RC t RWC t HPC t HPRWC t RAC t CAC t AA t CPA t REZ t T t RP t RAS t RASP

t RSH t CAS t CSH t RCD t RAD t CRP t ASR t RAH t ASC t CAH t RAL

t OEA t OEZ t REF t ROH t RHCP t CLZ t CP t AR t REF MSM511666C/CL-70MSM511666C/CL-60ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

ns ns ms ms ns 4, 5, 64, 54, 647, 856474

3CAS to Data Output Buffer Turn-off Delay Time t CEZ ns 7, 8Data Output Hold After CAS Low

t DOH

ns WE to Data Output Buffer Turn-off Delay Time t WEZ ns 7OE Hold Time from CAS (DQ Disable)t CHO ns RAS to Second CAS Delay Time t RSCD ns Min.

1101552565————00140606020101050201550100104530

—0——1505056035Max.————60203035—1550—10,000

100,000

——10,000—4030———————

2015432—15—15———ns Min.1201703070————00140707020101055201550100105535

—0——1505057040Max.————70203540—1550—10,000

100,000

——10,000—5035———————

2015432—15—15———

? Semiconductor MSM511666C/CL

AC Characteristics (2/2)

Write Command Pulse Width Write Command to CAS Lead Time Write Command to RAS Lead Time Data-in Set-up Time Data-in Hold Time from RAS CAS to WE Delay Time

RAS to WE Delay Time Column Address to WE Delay Time RAS to CAS Hold Time (CAS before RAS )

CAS Active Delay Time from RAS Precharge Data-in Hold Time

Write Command Hold Time

Write Command Hold Time from RAS OE Command Hold Time OE to Data-in Delay Time (V CC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3

Write Command Set-up Time Parameter

RAS to CAS Set-up Time (CAS before RAS )CAS Precharge WE Delay Time

MSM511666C/CL-70MSM511666C/CL-60Read Command Set-up Time Read Command Hold Time

Read Command Hold Time referenced to RAS WE Pulse Width (DQ Disable)OE Command Hold Time

OE Precharge Time Symbol

t WP t CWL t RWL t DS t DHR t CWD t RWD t AWD t CHR

t RPC t DH t WCH t WCR t OEH t OED t WCS t CSR t CPWD t RCS t RCH t RRH t WPE t OCH t OEP 000Min.

102020040408050510

0101040101505571010———Max.——————————

———————————Unit ns ns ns ns ns ns ns ns ns ns

ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 111010101110

99000Min.102020045459560510

0101045101506571010———Max.——————————

———————————

? Semiconductor MSM511666C/CL Notes: 1. A start-up delay of 100 μs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device

operation is achieved.

2.The AC characteristics assume t T = 5 ns.

3.V IH (Min.) and V IL (Max.) are reference levels for measuring input timing signals.

Transition times (t T) are measured between V IH and V IL.

4.This parameter is measured with a load circuit equivalent to 1 TTL load and 50 pF.

The output timing reference levels are V OH = 2.0 V (I OH = –2 mA) and V OL = 0.8 V (I OL

= 2 mA).

5.Operation within the t RCD (Max.) limit ensures that t RAC (Max.) can be met.

t RCD (Max.) is specified as a reference point only. If t RCD is greater than the specified

t RCD (Max.) limit, then the access time is controlled by t CAC.

6.Operation within the t RAD (Max.) limit ensures that t RAC (Max.) can be met.

t RAD (Max.) is specified as a reference point only. If t RAD is greater than the specified

t RAD (Max.) limit, then the access time is controlled by t AA.

7.t CEZ (Max.), t REZ (Max.), t WEZ (Max.) and t OEZ (Max.) define the time at which the

output achieves the open circuit condition and are not referenced to output voltage

levels.

8.t CEZ and t REZ must be satisfied for open circuit condition.

9.t RCH or t RRH must be satisfied for a read cycle.

10.t WCS, t CWD, t RWD, t AWD and t CPWD are not restrictive operating parameters. They are

included in the data sheet as electrical characteristics only. If t WCS ≥ t WCS (Min.), then

the cycle is an early write cycle and the data out will remain open circuit (high

impedance) throughout the entire cycle. If t CWD ≥ t CWD (Min.) , t RWD ≥ t RWD (Min.),

t AWD ≥ t AWD (Min.) and t CPWD ≥ t CPWD (Min.), then the cycle is a read modify write

cycle and data out will contain data read from the selected cell; if neither of the above

sets of conditions is satisfied, then the condition of the data out (at access time) is

indeterminate.

11.These parameters are referenced to the CAS leading edge in an early write cycle, and

to the WE leading edge in an OE control write cycle, or a read modify write cycle.

? Semiconductor

MSM511666C/CL

TIMING WAVEFORM

Read Cycle

Write Cycle (Early Write)

RAS

CAS

V IH V IL ––

IH V IL ––

V OH V OL ––

Address

V IH V IL ––WE

V IH V IL ––OE

V IH V IL ––

"H" or "L"

RAS

CAS

V IH V IL ––

Address

V IH V IL ––WE

V IH V IL ––

E2G0095-17-41H

? Semiconductor MSM511666C/CL

Read Modify Write Cycle

RAS

CAS

V IH V IL ––

V I/OH V I/OL ––

Address

V IH V IL ––WE V IH V IL ––OE

V IH V IL ––

? Semiconductor

MSM511666C/CL

Fast Page Mode Read Cycle (Part-1)

Fast Page Mode Read Cycle (Part-2)

––

––––V IH RAS

Address

CAS

––

V IL V IH V IL V IH V IL V IH V IL V IH V IL V OH V OL

"H" or "L"

* : Same Data,––

––

––––V IH RAS

Address

CAS

––––

V IL V IH V IL V IH V IL V IH V IL V

IH V IL V OH V OL

? Semiconductor

MSM511666C/CL

Fast Page Mode Write Cycle (Early Write)

Fast Page Mode Read Modify Write Cycle

–

––

V IH RAS

Address

CAS

––

V IL V IH V IL V IH V IL V IH V IL V IH V IL V I/OH V I/OL

––

––––––V IH RAS

Address

CAS

––

V IL V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL "H" or "L"

? Semiconductor MSM511666C/CL

RAS -Only Refresh Cycle

CAS before RAS Refresh Cycle

RAS

CAS

V IH V IL ––V IH V IL ––

Address

V IH V IL ––

"H" or "L"

V OH V OL ––

Note: WE , OE = "H" or "L"

RAS

CAS

V IH V IL ––

Note: WE , OE , Address = "H" or "L"

V OH V OL ––

? Semiconductor MSM511666C/CL

Hidden Refresh Read Cycle

Hidden Refresh Write Cycle

––

––––––V IH RAS

Address

CAS

––––V IL V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL

RAS

CAS

Address

V IH V IL ––V IH V IL ––V IH V IL ––V IH V IL –

–

"H" or "L"

V IH V IL ––

V OH V OL –

–

? Semiconductor MSM511666C/CL

(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

SOJ40-P-400-1.27

Package material Lead frame material Pin treatment

Solder plate thickness Package weight (g)Epoxy resin 42 alloy

Solder plating 5 m m or more 1.70 TYP.

Mirror finish

? Semiconductor MSM511666C/CL

(Unit : mm)

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Package material Lead frame material Pin treatment

Solder plate thickness Package weight (g)Epoxy resin 42 alloy

Solder plating 5 m m or more 0.49 TYP.

TSOP II 44/40-P-400-0.80-K

Mirror finish