SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1316
Advance Information
128 x 39 Dot Matrix OLED/PLED Segment/Common Driver with Controller
This document contains information on a new product. Specifications and information herein are subject to change without notice. https://www.doczj.com/doc/59466562.html, SSD1316 Rev 1.2 P 1/63
Nov 2013
Copyright ? 2013 Solomon Systech Limited
Appendix: IC Revision history of SSD1316 Specification Version 0.10 1.0 Change Items 1st Release Advance Information Release Modify from SSD1316 Product Preview R0.10 Update the Charge Pump 8D Command Update the DC characteristics Update the AC characteristics Advance Information Release Modify from SSD1316 Advance Information R1.0 Revise typo for ADh command for internal IREF selection Update VBAT and the Charge Pump 8Dh command Update the DC characteristics Revise Figure 9.10 and Figure 9.11 for continuous scrolling Add Content Scrolling Setup details Advance Information Release Modify from SSD1316 Advance Information R1.1 Update Contrast Control 81h command Update Typical Frequency in AC characteristics Effective Date 15-Jul-11 10-Oct-11
1.1
16-Apr-12
1.2
08-Nov-13
Solomon Systech
Nov 2013
P 2/63
Rev 1.2
SSD1316
CONTENTS 1 2 3 4 5 6 7 GENERAL DESCRIPTION ........................................................................................................ 7 FEATURES.................................................................................................................................... 7 ORDERING INFORMATION .................................................................................................... 7 BLOCK DIAGRAM ..................................................................................................................... 8 DIE PAD FLOOR PLAN ............................................................................................................. 9 PIN DESCRIPTION ................................................................................................................... 11 FUNCTIONAL BLOCK DESCRIPTIONS ............................................................................. 13
7.1 MCU INTERFACE SELECTION ............................................................................................................................... 13 7.1.1 MCU Parallel 6800-series Interface ........................................................................................................... 13 7.1.2 MCU Parallel 8080-series Interface ........................................................................................................... 14 7.1.3 MCU Serial Interface (4-wire SPI) ............................................................................................................. 15 7.1.4 MCU Serial Interface (3-wire SPI) ............................................................................................................. 16 7.1.5 MCU I2C Interface ...................................................................................................................................... 17 7.2 COMMAND DECODER .......................................................................................................................................... 20 7.3 OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR ...................................................................................... 20 7.4 FR SYNCHRONIZATION ........................................................................................................................................ 21 7.5 RESET CIRCUIT .................................................................................................................................................... 21 7.6 SEGMENT DRIVERS / COMMON DRIVERS ............................................................................................................. 22 7.7 GRAPHIC DISPLAY DATA RAM (GDDRAM) ...................................................................................................... 23 7.8 SEG/COM DRIVING BLOCK ................................................................................................................................ 24 7.9 POWER ON AND OFF SEQUENCE ......................................................................................................................... 25 7.9.1 Power ON and OFF sequence with External VCC ....................................................................................... 25 7.9.2 Power ON and OFF sequence with Charge Pump Application .................................................................. 26 7.10 CHARGE PUMP REGULATOR ................................................................................................................................ 27
8 9
COMMAND TABLE .................................................................................................................. 27
8.1 DATA READ / WRITE ........................................................................................................................................... 37
COMMAND DESCRIPTIONS.................................................................................................. 38
9.1 FUNDAMENTAL COMMAND ................................................................................................................................. 38 9.1.1 Set Lower Column Start Address for Page Addressing Mode (00h~0Fh) .................................................. 38 9.1.2 Set Higher Column Start Address for Page Addressing Mode (10h~17h) .................................................. 38 9.1.3 Set Memory Addressing Mode (20h) ........................................................................................................... 38 9.1.4 Set Column Address (21h)........................................................................................................................... 39 9.1.5 Set Page Address (22h) ............................................................................................................................... 40 9.1.6 Set Display Start Line (40h~66h)................................................................................................................ 40 9.1.7 Set Contrast Control (81h).......................................................................................................................... 40 9.1.8 Set Segment Re-map (A0h/A1h) .................................................................................................................. 40 9.1.9 Entire Display ON (A4h/A5h) ................................................................................................................... 41 9.1.10 Set Normal/Inverse Display (A6h/A7h)....................................................................................................... 41 9.1.11 Set Multiplex Ratio (A8h)............................................................................................................................ 41 9.1.12 External or Internal VCOMH Selection / External or internal IREF Selection (ADh) ............................... 41 9.1.13 Set Display ON/OFF (AEh/AFh) ................................................................................................................ 41 9.1.14 Set Page Start Address for Page Addressing Mode (B0h~B4h).................................................................. 41 9.1.15 Set COM Output Scan Direction (C0h/C8h) ............................................................................................... 42 9.1.16 Set Display Offset (D3h) ............................................................................................................................. 42 9.1.17 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h) .................................................................... 45 9.1.18 Set Pre-charge Period (D9h) ...................................................................................................................... 45 9.1.19 Set COM Pins Hardware Configuration (DAh) .......................................................................................... 45
SSD1316
Rev 1.2
P 3/63
Nov 2013
Solomon Systech
9.1.20 Set VCOMH Deselect Level (DBh) ................................................................................................................. 45 9.1.21 NOP (E3h) .................................................................................................................................................. 45 9.1.22 Status register Read .................................................................................................................................... 45 9.1.23 Charge Pump Setting (8Dh)........................................................................................................................ 45 9.2 GRAPHIC ACCELERATION COMMAND .................................................................................................................. 46 9.2.1 Horizontal Scroll Setup (26h/27h) .............................................................................................................. 46 9.2.2 Continuous Vertical and Horizontal Scroll Setup (29h/2Ah)...................................................................... 47 9.2.3 Deactivate Scroll (2Eh)............................................................................................................................... 47 9.2.4 Activate Scroll (2Fh) ................................................................................................................................... 47 9.2.5 Set Vertical Scroll Area (A3h) .................................................................................................................... 47 9.2.6 Content Scroll Setup (2Ch/2Dh) ................................................................................................................. 48 9.3 ADVANCE GRAPHIC COMMAND........................................................................................................................... 51 9.3.1 Set Fade Out / Fade In and Blinking (23h) ................................................................................................. 51 9.3.2 Set Zoom In (D6h)....................................................................................................................................... 51
10 11 12 13 14
14.1
MAXIMUM RATINGS ........................................................................................................... 52 DC CHARACTERISTICS ...................................................................................................... 53 AC CHARACTERISTICS ...................................................................................................... 54 APPLICATION EXAMPLES ................................................................................................ 60 PACKAGE INFORMATION ................................................................................................. 62
DIE TRAY DIMENSIONS ................................................................................................................................. 62
Solomon Systech
Nov 2013
P 4/63
Rev 1.2
SSD1316
TABLES
TABLE 3-1 : ORDERING INFORMATION .................................................................................................................................. 7 TABLE 5-1 : SSD1316Z BUMP DIE PAD COORDINATES ....................................................................................................... 10 TABLE 6-1 : PIN DESCRIPTION ............................................................................................................................................. 11 TABLE 6-2 : MCU BUS INTERFACE PIN SELECTION ............................................................................................................. 12 TABLE 7-1 : MCU INTERFACE ASSIGNMENT UNDER DIFFERENT BUS INTERFACE MODE ....................................................... 13 TABLE 7-2 : CONTROL PINS OF 6800 INTERFACE.................................................................................................................. 13 TABLE 7-3 : CONTROL PINS OF 8080 INTERFACE.................................................................................................................. 15 TABLE 7-4 : CONTROL PINS OF 4-WIRE SERIAL INTERFACE .................................................................................................. 15 TABLE 7-5 : CONTROL PINS OF 3-WIRE SERIAL INTERFACE .................................................................................................. 16 TABLE 8-1: SSD1316 COMMAND TABLE ............................................................................................................................ 27 TABLE 8-2 : SEG PINS HARDWARE CONFIGURATION .......................................................................................................... 33 TABLE 8-3 : READ COMMAND TABLE .................................................................................................................................. 37 TABLE 8-4 : ADDRESS INCREMENT TABLE (AUTOMATIC) .................................................................................................... 37 TABLE 9-1 : EXAMPLE OF SET DISPLAY OFFSET AND DISPLAY START LINE WITHOUT REMAP ............................................ 43 TABLE 9-2 : EXAMPLE OF SET DISPLAY OFFSET AND DISPLAY START LINE WITH REMAP .................................................. 44 TABLE 9-3 : CONTENT SCROLLING SOFTWARE FLOW EXAMPLE (PAGE ADDRESSING MODE – COMMAND 20H, 02H) ............ 49 TABLE 9-4 : CONTENT SCROLLING SETTING EXAMPLE (VERTICAL ADDRESSING MODE – COMMAND 20H, 01H) .................. 50 TABLE 10-1 : MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS) .................................................................................. 52 TABLE 11-1 : DC CHARACTERISTICS ................................................................................................................................... 53 TABLE 12-1 : AC CHARACTERISTICS ................................................................................................................................... 54 TABLE 12-2 : 6800-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS.......................................................... 54 TABLE 12-3 : 8080-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS.......................................................... 56 TABLE 12-4 : SERIAL INTERFACE TIMING CHARACTERISTICS (4-WIRE SPI) ........................................................................ 57 TABLE 12-5 : SERIAL INTERFACE TIMING CHARACTERISTICS (3-WIRE SPI) ........................................................................ 58 TABLE 12-6 : I2C INTERFACE TIMING CHARACTERISTICS .................................................................................................... 59
SSD1316
Rev 1.2
P 5/63
Nov 2013
Solomon Systech
FIGURES
FIGURE 4-1 : SSD1316 BLOCK DIAGRAM.............................................................................................................................. 8 FIGURE 5-1 : SSD1316Z DIE DRAWING ................................................................................................................................ 9 FIGURE 7-1 : DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ ........................................................................ 14 FIGURE 7-2 : EXAMPLE OF WRITE PROCEDURE IN 8080 PARALLEL INTERFACE MODE.......................................................... 14 FIGURE 7-3 : EXAMPLE OF READ PROCEDURE IN 8080 PARALLEL INTERFACE MODE ........................................................... 14 FIGURE 7-4 : DISPLAY DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ .......................................................... 15 FIGURE 7-5 : WRITE PROCEDURE IN 4-WIRE SERIAL INTERFACE MODE ................................................................................ 16 FIGURE 7-6 : WRITE PROCEDURE IN 3-WIRE SERIAL INTERFACE MODE ................................................................................ 16 FIGURE 7-7 : I2C-BUS DATA FORMAT ................................................................................................................................... 18 FIGURE 7-8 : DEFINITION OF THE START AND STOP CONDITION .......................................................................................... 19 FIGURE 7-9 : DEFINITION OF THE ACKNOWLEDGEMENT CONDITION .................................................................................... 19 FIGURE 7-10 : DEFINITION OF THE DATA TRANSFER CONDITION .......................................................................................... 19 FIGURE 7-11 : OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR ............................................................................... 20 FIGURE 7-12 : SEGMENT OUTPUT WAVEFORM IN THREE PHASES ........................................................................................ 22 FIGURE 7-13 : GDDRAM PAGES STRUCTURE OF SSD1316 ................................................................................................. 23 FIGURE 7-14 : IREF CURRENT SETTING BY RESISTOR VALUE ............................................................................................... 24 FIGURE 7-15 : THE POWER ON SEQUENCE........................................................................................................................... 25 FIGURE 7-16 : THE POWER OFF SEQUENCE ......................................................................................................................... 25 FIGURE 7-17 : THE POWER ON SEQUENCE WITH CHARGE PUMP APPLICATION ................................................................... 26 FIGURE 7-18 : THE POWER OFF SEQUENCE WITH CHARGE PUMP APPLICATION ................................................................. 26 FIGURE 9-1 : ADDRESS POINTER MOVEMENT OF PAGE ADDRESSING MODE ........................................................................ 38 FIGURE 9-2 : EXAMPLE OF GDDRAM ACCESS POINTER SETTING IN PAGE ADDRESSING MODE (NO ROW AND COLUMNREMAPPING) ................................................................................................................................................................ 38 FIGURE 9-3 : ADDRESS POINTER MOVEMENT OF HORIZONTAL ADDRESSING MODE ............................................................ 39 FIGURE 9-4 : ADDRESS POINTER MOVEMENT OF VERTICAL ADDRESSING MODE ................................................................. 39 FIGURE 9-5 : EXAMPLE OF COLUMN AND ROW ADDRESS POINTER MOVEMENT ................................................................. 40 FIGURE 9-6 : TRANSITION BETWEEN DIFFERENT MODES ...................................................................................................... 41 FIGURE 9-7 : EXAMPLE OF ROW ADDRESS MAPPING............................................................................................................. 42 FIGURE 9-8 : HORIZONTAL SCROLL EXAMPLE: SCROLL RIGHT BY 1 COLUMN .................................................................... 46 FIGURE 9-9 : HORIZONTAL SCROLL EXAMPLE: SCROLL LEFT BY 1 COLUMN ...................................................................... 46 FIGURE 9-10 : HORIZONTAL SCROLLING SETUP EXAMPLE.................................................................................................... 46 FIGURE 9-11 : CONTINUOUS VERTICAL AND HORIZONTAL SCROLLING SETUP EXAMPLE ..................................................... 47 FIGURE 9-12 : VERTICAL SCROLL AREA SETUP EXAMPLES ................................................................................................... 48 FIGURE 9-13: CONTENT SCROLLING EXAMPLE (2DH, LEFT HORIZONTAL SCROLL BY ONE COLUMN) ................................. 49 FIGURE 9-14 : EXAMPLE OF FADE OUT MODE...................................................................................................................... 51 FIGURE 9-15 : EXAMPLE OF FADE IN MODE ......................................................................................................................... 51 FIGURE 9-16 : EXAMPLE OF BLINKING MODE ...................................................................................................................... 51 FIGURE 9-17 : EXAMPLE OF ZOOM IN .................................................................................................................................. 51 FIGURE 12-1 : 6800-SERIES MCU PARALLEL INTERFACE CHARACTERISTICS ....................................................................... 55 FIGURE 12-2 : 8080-SERIES PARALLEL INTERFACE CHARACTERISTICS................................................................................. 56 FIGURE 12-3 : SERIAL INTERFACE CHARACTERISTICS (4-WIRE SPI)..................................................................................... 57 FIGURE 12-4 : SERIAL INTERFACE CHARACTERISTICS (3-WIRE SPI)..................................................................................... 58 FIGURE 12-5 : I2C INTERFACE TIMING CHARACTERISTICS ................................................................................................... 59 FIGURE 13-1 : APPLICATION EXAMPLE OF SSD1316Z WITH EXTERNAL VCC AND I2C INTERFACE ..................................... 60 FIGURE 13-2 : APPLICATION EXAMPLE OF SSD1316Z WITH INTERNAL CHARGE PUMP, INTERNAL IREF AND I2C INTERFACE .................................................................................................................................................................................... 61 FIGURE 14-1 : SSD1316Z DIE TRAY INFORMATION ............................................................................................................. 62
Solomon Systech
Nov 2013
P 6/63
Rev 1.2
SSD1316
1
GENERAL DESCRIPTION
SSD1316 is a single-chip CMOS OLED/PLED driver with controller for organic / polymer light emitting diode dot-matrix graphic display system. It consists of 128 segments and 39 commons. This IC is designed for Common Cathode type OLED panel. The SSD1316 embeds with contrast control, display RAM and oscillator, which reduces the number of external components and power consumption. It has 256-step brightness control. Data/Commands are sent from general MCU through the hardware selectable 6800/8080 series compatible Parallel Interface, I2C interface or Serial Peripheral Interface. It is suitable for many compact portable applications, such as mobile phone sub-display, MP3 player and Bluetooth headset and Medical devices, etc.
2
FEATURES
? ? Resolution: 128 x39 dot matrix panel Power supply o VDD = 1.65V ~ 3.3V, < VBAT for IC logic for charge pump regulator circuit o VBAT = 3.0V ~ 4.2V o VCC = 7V~15V for Panel driving For matrix display OLED driving output voltage, 15V maximum Segment maximum source current: 160uA Common maximum sink current: 20mA 256 step contrast brightness current control Embedded 128 x 39 bit SRAM display buffer Pin selectable MCU Interfaces: o 8-bit 6800/8080-series parallel interface o 3 /4 wire Serial Peripheral Interface o I2C Interface Screen saving continuous scrolling function in both horizontal and vertical direction Internal charge pump regulator Internal regulated VCOMH or external VCOMH Internal IREF or external IREF Programmable Frame Rate Programmable Multiplexing Ratio Row Re-mapping and Column Re-mapping On-Chip Oscillator Chip layout for COG , COF Wide range of operating temperature: -40°C to 85°C
? ? ? ? ? ? ?
? ? ? ? ? ? ? ? ? ?
3
ORDERING INFORMATION
Table 3-1 : Ordering Information
Ordering Part Number SSD1316Z
SEG 128
COM 39
Package Form COG
Remark -
SSD1316
Rev 1.2
P 7/63
Nov 2013
Solomon Systech
4
BLOCK DIAGRAM
Figure 4-1 : SSD1316 Block Diagram
Graphic Display Data RAM (GDDRAM)
D7 D6 D5 D4 D3 D2 D1 D0 VDD VCC VSS VLSS
Display Controller
MCU Interface
RES# CS# D/C# E (RD#) R/W#(WR#) BS2 BS1 BS0
SEG 63 SEG 62 : SEG1 SEG0
Segment Driver
COM 0 COM 1 : COM37 COM38
Current Control Voltage Control
Charge pump Regulator
Common Driver
SEG 64 SEG 65 : SEG126 SEG127
Command Decoder
Oscillator
Solomon Systech
BGGND VCC VBAT C1N C1P C2N C2P
VCOMH IREF
CL CLS
FR
Segment Driver
Nov 2013
P 8/63
Rev 1.2
SSD1316
5
DIE PAD FLOOR PLAN
Figure 5-1 : SSD1316Z Die Drawing
Pin 1
Die Size (after sawing) Die Thickness Min I/O pad pitch Min SEG pad pitch Min COM pad pitch Bump Height
6.08mm +/- 0.05mm x 0.79mm +/- 0.05mm 300 um ± 15 um 60 um 30.2 um 40 um Nominal 12 um
Bump Size Pad # 1~25, 34~63, 72~89, 101 26~33, 64~71 90~100 102~107, 293~298 108~178, 222~292 179~221
Alignment mark T shape + shape
25 25 25
X [um] Y [um] 40 95 30 50 15 95 50 25 15.2 94 25 77
Size 75um x 75um 75um x 75um
25 25 25
Position (2890, 19.5) (-2890, 19.5)
SSD1316Z
10
15 15
15
75
Note (1) Diagram showing the Gold bumps face up. (2) Coordinates are referenced to center of the chip. (3) Coordinate units and size of all alignment marks are in um. (4) All alignment keys do not contain gold.
y
SSD1316Z
x
Pad 1, 2, 3 .... -> 101 Gold Bumps face up
SSD1316
Rev 1.2
P 9/63
Nov 2013
Solomon Systech
25
50
Table 5-1 : SSD1316Z Bump Die Pad Coordinates
Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin name NC C2N C2N C2N C2N C2P C2P C2P C2P C1P C1P C1P C1P C1N C1N C1N VBAT VBAT VBAT VCC VCC VCC VCOMH VCOMH VCOMH VLSS VLSS VLSS VLSS VSS VSS VSS VSS VDD VDD FR VSS CS# RES# D/C# VSS R/W#(WR#) E/RD# D0 D1 D2 D3 VSS D4 D5 D6 D7 CL VSS CLS VDD VDD BS0 VSS BS1 VDD BS2 VSS BGGND VSS VSS VSS VLSS VLSS VLSS VLSS VBREF VSS VSS GPIO0 GPIO1 VDD VDD NC IREF X -2987.5 -2927.5 -2867.5 -2807.5 -2747.5 -2687.5 -2627.5 -2567.5 -2507.5 -2447.5 -2387.5 -2327.5 -2267.5 -2207.5 -2147.5 -2087.5 -2027.5 -1967.5 -1907.5 -1847.5 -1787.5 -1727.5 -1667.5 -1607.5 -1547.5 -1427.5 -1365 -1302.5 -1240 -1177.5 -1115 -1052.5 -990 -870 -810 -750 -690 -630 -570 -510 -450 -390 -330 -270 -210 -150 -90 -30 30 90 150 210 270 330 390 450 510 570 630 690 750 810 870 990 1052.5 1115 1177.5 1240 1302.5 1365 1427.5 1547.5 1607.5 1667.5 1727.5 1787.5 1847.5 1907.5 1967.5 2027.5 Y -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -337.5 -337.5 -337.5 -337.5 -337.5 -337.5 -337.5 -337.5 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -337.5 -337.5 -337.5 -337.5 -337.5 -337.5 -337.5 -337.5 -315 -315 -315 -315 -315 -315 -315 -315 -315 Pin number Pin name 81 VCOMH 82 VCOMH 83 VCOMH 84 VCOMH 85 VCC 86 VCC 87 VCC 88 VCC 89 NC 90 TR0 91 TR1 92 TR2 93 TR3 94 TR4 95 VSS 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 TR5 TR6 TR7 TR8 TR9 NC NC NC NC NC NC NC VCC VCC VCC SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 X 2087.5 2147.5 2207.5 2267.5 2327.5 2387.5 2447.5 2507.5 2567.5 2616 2646 2676 2706 2736 2766 2796 2826 2856 2886 2916 2964.5 2986.4 2986.4 2986.4 2986.4 2986.4 2986.4 3003.4 2973.2 2943 2912.8 2882.6 2852.4 2822.2 2792 2761.8 2731.6 2701.4 2671.2 2641 2610.8 2580.6 2550.4 2520.2 2490 2459.8 2429.6 2399.4 2369.2 2339 2308.8 2278.6 2248.4 2218.2 2188 2157.8 2127.6 2097.4 2067.2 2037 2006.8 1976.6 1946.4 1916.2 1886 1855.8 1825.6 1795.4 1765.2 1735 1704.8 1674.6 1644.4 1614.2 1584 1553.8 1523.6 1493.4 1463.2 1433 Y -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -315 -193.425 -153.425 -113.425 -73.425 -33.425 6.575 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 Pin number Pin name 161 SEG13 162 SEG12 163 SEG11 164 SEG10 165 SEG9 166 SEG8 167 SEG7 168 SEG6 169 SEG5 170 SEG4 171 SEG3 172 SEG2 173 SEG1 174 SEG0 175 VCC 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 VCC VCC VCC VCOMH VCOMH COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 VCOMH VCOMH VCC VCC VCC VCC SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 X 1402.8 1372.6 1342.4 1312.2 1282 1251.8 1221.6 1191.4 1161.2 1131 1100.8 1070.6 1040.4 1010.2 980 949.8 919.6 889.4 840 800 760 720 680 640 600 560 520 480 440 400 360 320 280 240 200 160 120 80 40 0 -40 -80 -120 -160 -200 -240 -280 -320 -360 -400 -440 -480 -520 -560 -600 -640 -680 -720 -760 -800 -840 -889.4 -919.6 -949.8 -980 -1010.2 -1040.4 -1070.6 -1100.8 -1131 -1161.2 -1191.4 -1221.6 -1251.8 -1282 -1312.2 -1342.4 -1372.6 -1402.8 -1433 Y 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 300 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 Pin number Pin name 241 SEG79 242 SEG80 243 SEG81 244 SEG82 245 SEG83 246 SEG84 247 SEG85 248 SEG86 249 SEG87 250 SEG88 251 SEG89 252 SEG90 253 SEG91 254 SEG92 255 SEG93 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 VCC VCC VCC NC NC NC NC NC NC X -1463.2 -1493.4 -1523.6 -1553.8 -1584 -1614.2 -1644.4 -1674.6 -1704.8 -1735 -1765.2 -1795.4 -1825.6 -1855.8 -1886 -1916.2 -1946.4 -1976.6 -2006.8 -2037 -2067.2 -2097.4 -2127.6 -2157.8 -2188 -2218.2 -2248.4 -2278.6 -2308.8 -2339 -2369.2 -2399.4 -2429.6 -2459.8 -2490 -2520.2 -2550.4 -2580.6 -2610.8 -2641 -2671.2 -2701.4 -2731.6 -2761.8 -2792 -2822.2 -2852.4 -2882.6 -2912.8 -2943 -2973.2 -3003.4 -2986.4 -2986.4 -2986.4 -2986.4 -2986.4 -2986.4 Y 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 316.5 6.575 -33.425 -73.425 -113.425 -153.425 -193.425
Solomon Systech
Nov 2013 P 10/63
Rev 1.2
SSD1316
6
PIN DESCRIPTION
I = Input O =Output I/O = Bi-directional (input/output) P = Power pin NC = Not Connected Pull LOW= connect to Ground Pull HIGH= connect to VDD
Key:
Table 6-1 : Pin Description
Pin Name VDD VCC VSS VLSS VCOMH
Type P P P P O
Description Power supply pin for core logic operation. Power supply for panel driving voltage. This is also the most positive power voltage supply pin. This is a ground pin. This is an analog ground pin. It should be connected to VSS externally. The pin is for COM signal deselected voltage level. A capacitor should be connected between this pin and VSS. When external VCOMH is selected, this pin must be connected to VCC. Refer to command ADh for details. Power supply for charge pump regulator circuit. Status VBAT VDD Enable charge Connect to external Connect to external pump VBAT source VDD source Disable charge pump Keep float Connect to external VDD source VCC A capacitor should be connected between this pin and VSS Connect to external VCC source
VBAT
P
BGGND C1P/C1N C2P/C2N VBREF BS[2:0] IREF
P O O I I
Reserved pin. It should be connected to VSS externally. C1P/C1N – Pin for charge pump capacitor; Connect to each other with a capacitor. C2P/C2N – Pin for charge pump capacitor; Connect to each other with a capacitor. Reserved pin. It should be kept NC. MCU bus interface selection pins. Please refer to Table 6-2 for the details of setting. This is segment output current reference pin. When external IREF is used, a resistor should be connected between this pin and VSS to maintain the IREF current at 10uA. Please refer to Figure 7-14 for the details of resistor value. When internal IREF is used, this pin should be kept NC. This pin outputs RAM write synchronization signal. Proper timing between MCU data writing and frame display timing can be achieved to prevent tearing effect. It should be kept NC if it is not used. This is external clock input pin. When internal clock is enabled (i.e. HIGH in CLS pin), this pin is not used and should be connected to VSS. When internal clock is disabled (i.e. LOW in CLS pin), this pin is the external clock source input pin.
FR
O
CL
I
SSD1316
Rev 1.2
P 11/63
Nov 2013
Solomon Systech
Pin Name CLS RES# CS# D/C#
Type I I I I
Description This is internal clock enable pin. When it is pulled HIGH (i.e. connect to VDD), internal clock is enabled. When it is pulled LOW, the internal clock is disabled; an external clock source must be connected to the CL pin for normal operation. This pin is reset signal input. When the pin is pulled LOW, initialization of the chip is executed. Keep this pin HIGH (i.e. connect to VDD) during normal operation. This pin is the chip select input. (active LOW) This is Data/Command control pin. When it is pulled HIGH (i.e. connect to VDD), the data at D[7:0] is treated as data. When it is pulled LOW, the data at D[7:0] will be transferred to the command register. In I2C mode, this pin acts as SA0 for slave address selection. When 3-wire serial interface is selected, this pin must be connected to VSS. When interfacing to a 6800-series microprocessor, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled HIGH (i.e. connect to VDD) and the chip is selected. When connecting to an 8080-series microprocessor, this pin receives the Read (RD#) signal. Read operation is initiated when this pin is pulled LOW and the chip is selected. When serial interface is selected, this pin must be connected to VSS. This is read / write control input pin connecting to the MCU interface. When interfacing to a 6800-series microprocessor, this pin will be used as Read/Write (R/W#) selection input. Read mode will be carried out when this pin is pulled HIGH (i.e. connect to VDD) and write mode when LOW. When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data write operation is initiated when this pin is pulled LOW and the chip is selected. When serial or I2C interface is selected, this pin must be connected to VSS. These are 8-bit bi-directional data bus to be connected to the microprocessor’s data bus. When serial interface mode is selected, D0 will be the serial clock input: SCLK; D1 will be the serial data input: SDIN and D2 should be kept NC. When I2C mode is selected, D2, D1 should be tied together and serve as SDAout, SDAin in application and D0 is the serial clock input, SCL. Reserved pin. It should be kept NC. Reserved pin. It should be kept NC. These pins provide Segment switch signals to OLED panel. These pins are VSS state when display is OFF. These pins provide Common switch signals to OLED panel. They are in high impedance state when display is OFF. This is dummy pin. Do not group or short NC pins together.
Table 6-2 : MCU Bus Interface Pin Selection
E (RD#)
I
R/W#(WR#)
I
D[7:0]
IO
GPIO0/GPIO1 TR[9:0] SEG0 ~ SEG127 COM0 ~ COM38 NC
IO IO O O -
SSD1316 Pin Name BS0 BS1 BS2 Note (1) 0 is connected to VSS (2) 1 is connected to VDD
I2C Interface 6800-parallel interface (8 bit) 0 0 1 0 0 1
8080-parallel interface (8 bit) 0 1 1
4-wire Serial interface 0 0 0
3-wire Serial interface 1 0 0
Solomon Systech
Nov 2013 P 12/63
Rev 1.2
SSD1316
7 7.1
FUNCTIONAL BLOCK DESCRIPTIONS MCU Interface selection
SSD1316 MCU interface consist of 8 data pins and 5 control pins. The pin assignment at different interface mode is summarized in Table 7-1. Different MCU mode can be set by hardware selection on BS[2:0] pins (please refer to Table 6-2 for BS[2:0] setting).
Table 7-1 : MCU interface assignment under different bus interface mode Pin Name Bus Interface 8-bit 8080 8-bit 6800 3-wire SPI 4-wire SPI I 2C Data/Command Interface D7 D6 D5 D4 D3 D[7:0] D[7:0] D2 D1 D0 Control Signal E R/W# RD# WR# E R/W# SDIN SCLK Tie LOW SDIN SCLK Tie LOW SDAIN SCL Tie LOW CS# CS# CS# CS# CS# D/C# D/C# D/C# Tie LOW D/C# SA0 RES# RES# RES# RES# RES# RES#
Tie LOW Tie LOW Tie LOW
NC NC SDAOUT
7.1.1 MCU Parallel 6800-series Interface The parallel interface consists of 8 bi-directional data pins (D[7:0]), R/W#, D/C#, E and CS#. A LOW in R/W# indicates WRITE operation and HIGH in R/W# indicates READ operation. A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write. The E input serves as data latch signal while CS# is LOW. Data is latched at the falling edge of E signal.
Table 7-2 : Control pins of 6800 interface Function Write command Read status Write data Read data Note (1) ↓ stands for falling edge of signal H stands for HIGH in signal L stands for LOW in signal E ↓ ↓ ↓ ↓ R/W# L H L H CS# L L L L D/C# L L H H
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 7-1.
SSD1316
Rev 1.2
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Nov 2013
Solomon Systech
Figure 7-1 : Data read back procedure - insertion of dummy read
R/W#
E
Databus
N
Write column address Dummy read
n
Read 1st data
n+1
Read 2nd data
n+2
Read 3rd data
7.1.2 MCU Parallel 8080-series Interface The parallel interface consists of 8 bi-directional data pins (D[7:0]), RD#, WR#, D/C# and CS#. A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write. A rising edge of RD# input serves as a data READ latch signal while CS# is kept LOW. A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept LOW.
Figure 7-2 : Example of Write procedure in 8080 parallel interface mode
CS# WR# D[7:0]
D/C#
high low
RD#
Figure 7-3 : Example of Read procedure in 8080 parallel interface mode
CS# RD# D[7:0]
D/C#
high low
WR#
Solomon Systech
Nov 2013 P 14/63
Rev 1.2
SSD1316
Table 7-3 : Control pins of 8080 interface Function Write command Read status Write data Read data Note (1) ↑ stands for rising edge of signal (2) H stands for HIGH in signal (3) L stands for LOW in signal RD# H WR#
↑
H
↑
H
↑
H
↑
CS# L L L L
D/C# L L H H
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 7-4.
Figure 7-4 : Display data read back procedure - insertion of dummy read
WR#
RD#
Databus
N
Write column address Dummy read
n
Read 1st data
n+1
Read 2nd data
n+2
Read 3rd data
7.1.3
MCU Serial Interface (4-wire SPI)
The 4-wire serial interface consists of serial clock: SCLK, serial data: SDIN, D/C#, CS#. In 4-wire SPI mode, D0 acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. The pins from D3 to D7, E and R/W# (WR#)# can be connected to an external ground.
Table 7-4 : Control pins of 4-wire Serial interface
Function Write command Write data Note (1) H stands for HIGH in signal (2) L stands for LOW in signal (3) ↑ stands for rising edge of signal
E Tie LOW Tie LOW
R/W# Tie LOW Tie LOW
CS# L L
D/C# L H
D0 ↑ ↑
SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Graphic Display Data RAM (GDDRAM) or command register in the same clock. Under serial mode, only write operations are allowed.
SSD1316 Rev 1.2 P 15/63 Nov 2013 Solomon Systech
Figure 7-5 : Write procedure in 4-wire Serial interface mode
CS# D/C#
SDIN/ SCLK
DB1
DB2
DBn
SCLK (D0) SDIN(D1) D7 D6 D5 D4 D3 D2 D1 D0
7.1.4 MCU Serial Interface (3-wire SPI) The 3-wire serial interface consists of serial clock SCLK, serial data SDIN and CS#. In 3-wire SPI mode, D0 acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. The pins from D3 to D7, R/W# (WR#)#, E and D/C# can be connected to an external ground. The operation is similar to 4-wire serial interface while D/C# pin is not used. There are altogether 9-bits will be shifted into the shift register on every ninth clock in sequence: D/C# bit, D7 to D0 bit. The D/C# bit (first bit of the sequential data) will determine the following data byte in the shift register is written to the Display Data RAM (D/C# bit = 1) or the command register (D/C# bit = 0). Under serial mode, only write operations are allowed.
Table 7-5 : Control pins of 3-wire Serial interface
Function Write command
Write data
E(RD#) Tie LOW
Tie LOW
R/W#(WR#) Tie LOW
Tie LOW
CS# L
L
D/C# Tie LOW
Tie LOW
D0 ↑ ↑
Note (1) L stands for LOW in signal (2) ↑ stands for rising edge of signal
Figure 7-6 : Write procedure in 3-wire Serial interface mode
CS# SDIN/ SCLK
DB1
DB2
DBn
SCLK (D0) SDIN(D1) D/C# D7 D6 D5 D4 D3 D2 D1 D0
Solomon Systech
Nov 2013 P 16/63
Rev 1.2
SSD1316
7.1.5
MCU I2C Interface
The I2C communication interface consists of slave address bit SA0, I2C-bus data signal SDA (SDAOUT/D2 for output and SDAIN/D1 for input) and I2C-bus clock signal SCL (D0). Both the data and clock signals must be connected to pull-up resistors. RES# is used for the initialization of device. a) Slave address bit (SA0) SSD1316 has to recognize the slave address before transmitting or receiving any information by the I2C-bus. The device will respond to the slave address following by the slave address bit (“SA0” bit) and the read/write select bit (“R/W#” bit) with the following byte format, b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 1 1 0 SA0 R/W# “SA0” bit provides an extension bit for the slave address. Either “0111100” or “0111101”, can be selected as the slave address of SSD1316. D/C# pin acts as SA0 for slave address selection. “R/W#” bit is used to determine the operation mode of the I2C-bus interface. R/W#=1, it is in read mode. R/W#=0, it is in write mode. b) I2C-bus data signal (SDA) SDA acts as a communication channel between the transmitter and the receiver. The data and the acknowledgement are sent through the SDA. It should be noticed that the ITO track resistance and the pulled-up resistance at “SDA” pin becomes a voltage potential divider. As a result, the acknowledgement would not be possible to attain a valid logic 0 level in “SDA”. “SDAIN” and “SDAOUT” are tied together and serve as SDA. The “SDAIN” pin must be connected to act as SDA. The “SDAOUT” pin may be disconnected. When “SDAOUT” pin is disconnected, the acknowledgement signal will be ignored in the I2C-bus. c) I2C-bus clock signal (SCL) The transmission of information in the I2C-bus is following a clock signal, SCL. Each transmission of data bit is taken place during a single clock period of SCL.
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Rev 1.2
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Nov 2013
Solomon Systech
7.1.5.1 I2C-bus Write data
The I2C-bus interface gives access to write data and command into the device. Please refer to Figure 7-7 for the write mode of I2C-bus in chronological order.
Figure 7-7 : I2C-bus data format
Note: Co – Continuation bit D/C# – Data / Command Selection bit ACK – Acknowledgement SA0 – Slave address bit R/W# – Read / Write Selection bit S – Start Condition / P – Stop Condition
Write mode
D/C# Co ACK R/W# SA0
ACK
D/C# Co ACK
ACK
ACK
P
0 1 1 1 0 0 1 111 1
Control byte
Data byte
Control byte
S
Data byte
Slave Address
m ≥ 0 words
1 byte
n ≥ 0 bytes MSB ……………….LSB
R/W# SA0
011110
SSD1316 Slave Address
D/C Co
ACK
0 0 0 0 0 0 Control byte
7.1.5.2 Write mode for I2C
1) The master device initiates the data communication by a start condition. The definition of the start condition is shown in Figure 7-8. The start condition is established by pulling the SDA from HIGH to LOW while the SCL stays HIGH. 2) The slave address is following the start condition for recognition use. For the SSD1316, the slave address is either “b0111100” or “b0111101” by changing the SA0 to LOW or HIGH (D/C pin acts as SA0). 3) The write mode is established by setting the R/W# bit to logic “0”. 4) An acknowledgement signal will be generated after receiving one byte of data, including the slave address and the R/W# bit. Please refer to the Figure 7-9 for the graphical representation of the acknowledge signal. The acknowledge bit is defined as the SDA line is pulled down during the HIGH period of the acknowledgement related clock pulse. 5) After the transmission of the slave address, either the control byte or the data byte may be sent across the SDA. A control byte mainly consists of Co and D/C# bits following by six “0” ‘s. a. If the Co bit is set as logic “0”, the transmission of the following information will contain data bytes only. b. The D/C# bit determines the next data byte is acted as a command or a data. If the D/C# bit is set to logic “0”, it defines the following data byte as a command. If the D/C# bit is set to logic “1”, it defines the following data byte as a data which will be stored at the GDDRAM. The GDDRAM column address pointer will be increased by one automatically after each data write. 6) Acknowledge bit will be generated after receiving each control byte or data byte. 7) The write mode will be finished when a stop condition is applied. The stop condition is also defined in Figure 7-8. The stop condition is established by pulling the “SDA in” from LOW to HIGH while the “SCL” stays HIGH.
Solomon Systech
Nov 2013 P 18/63
Rev 1.2
SSD1316
Figure 7-8 : Definition of the Start and Stop Condition
tHSTART tSSTOP
SDA
SDA
SCL
S START condition
P STOP condition
SCL
Figure 7-9 : Definition of the acknowledgement condition
DATA OUTPUT BY TRANSMITTER
DATA OUTPUT BY RECEIVER
Non-acknowledge
Acknowledge SCL FROM MASTER S START Condition
1
2
8
9
Clock pulse for acknowledgement
Please be noted that the transmission of the data bit has some limitations. 1. The data bit, which is transmitted during each SCL pulse, must keep at a stable state within the “HIGH” period of the clock pulse. Please refer to the Figure 7-10 for graphical representations. Except in start or stop conditions, the data line can be switched only when the SCL is LOW. 2. Both the data line (SDA) and the clock line (SCL) should be pulled up by external resistors.
Figure 7-10 : Definition of the data transfer condition
SDA
SCL
Data line is stable
Change of data
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Rev 1.2
P 19/63
Nov 2013
Solomon Systech
7.2
Command Decoder
This module determines whether the input data is interpreted as data or command. Data is interpreted based upon the input of the D/C# pin. If D/C# pin is HIGH, D[7:0] is interpreted as display data written to Graphic Display Data RAM (GDDRAM). If it is LOW, the input at D[7:0] is interpreted as a command. Then data input will be decoded and written to the corresponding command register.
7.3
Oscillator Circuit and Display Time Generator
Figure 7-11 : Oscillator Circuit and Display Time Generator
Internal Oscillator Fosc CL
M U X CLK Divider DCLK Display Clock
CLS
This module is an on-chip LOW power RC oscillator circuitry. The operation clock (CLK) can be generated either from internal oscillator or external source CL pin. This selection is done by CLS pin. If CLS pin is pulled HIGH, internal oscillator is chosen and CL should be connected to VSS. Pulling CLS pin LOW disables internal oscillator and external clock must be connected to CL pins for proper operation. When the internal oscillator is selected, its output frequency Fosc can be changed by command D5h A[7:4]. The display clock (DCLK) for the Display Timing Generator is derived from CLK. The division factor “D” can be programmed from 1 to 16 by command D5h DCLK = FOSC / D The frame frequency of display is determined by the following formula.
FFRM =
where ? D stands for clock divide ratio. It is set by command D5h A[3:0]. The divide ratio has the range from 1 to 16. ? K is the number of display clocks per row. The value is derived by K = Phase 1 period + Phase 2 period + Ko = 2 + 2 + 50 = 54 at power on reset (that is Ko is a constant that equals to 50) (Please refer to Section 7.6 for the details of the “Phase”) ? Number of multiplex ratio is set by command A8h. The power on reset value is 38 (i.e. 39MUX). ? FOSC is the oscillator frequency. It can be changed by command D5h A[7:4]. The higher the register setting results in higher frequency.
Fosc D × K × No. of Mux
Solomon Systech
Nov 2013 P 20/63
Rev 1.2
SSD1316