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TAS5731PHPR

TAS5731

https://www.doczj.com/doc/4418333376.html, ZHCS602–DECEMBER2011具有数字信号处理器(DSP)和2.1模式的2x20W数字音频功率放大器

查询样品:TAS5731

特性应用范围

?2通道I2S输入；8kHz至48kHz f S?液晶电视(LCD TV)

?20W立体声，8Ω/18V(总谐波失真(THD)+N=?LED背光源液晶电视(LED TV) 10%)?投音机

?最高90%效率运行

说明

?8V至21V宽电源电压范围；3.3V数字电源

TAS5731一款20W，高效，数字音频立体声功率放大?支持单一器件2.1(2×单端(SE)+1×桥式(BTL))

器，此放大器用于驱动驱动立体声桥接式扬声器。一?可支持2-ΩSE和4ΩBTL模式的70-mΩR DS(导通)器

件个串行数据输入可处理最多两个离散音频通道并能与大–12V/2Ω/8W SE模式多数数字音频处理器和MPEG解码器无缝整合。此器–12V/4Ω/15W BTL模式件可接受的输入数据和数据传输速率范围较宽。一个?扬声器均衡(EQ)（每通道8BQ），2x动态范围压完全可编程数据路径将这些通道路由至内部扬声器驱动缩(DRC)器。

?与TAS5727引脚到引脚(P2P)兼容

TAS5731是用于从外部源接收所有时钟的从属器件。?优势

根据输出采样率的不同，TAS5731运行时带有384kHz –直接连接至数字处理器

开关速率至352KHz开关速率间的的脉宽宽度调–来自标准电源的高输出功率

制(PWM)载波。与四阶噪声整形器结合的过采样可提–无需散热器

供一个真是白噪音基准(flat noise floor)以及从20Hz –高级处理改善了音频体验

至20kHz的出色动态范围。

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

B0264-18

TAS5731

ZHCS602–DECEMBER 2011

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These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

SIMPLIFIED APPLICATION DIAGRAM

MCLK SCLK LRCLK

SDA

SCL

OUT_A

OUT_B

OUT_C

OUT_D

B0262-14 TAS5731

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TAS5731

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B0034-07

Figure1.Power-Stage Functional Block Diagram

B 0321-14

TAS5731

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ZHCS602–DECEMBER 2011

DAP Process Structure

V O S C D A L S T _B

U T _C

G N D _A B

U T _B

G N D _C D

G N D _A B

G N D _C D

S T _C

P0075-15

PHP Package (Top View)

TAS5731

ZHCS602–DECEMBER 2011

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DEVICE INFORMATION

PIN ASSIGNMENT

PIN FUNCTIONS

PIN 5-V

TYPE (1)

TERMINATION (2)

DESCRIPTION

TOLERANT

NAME NO.AGND 30P Local analog ground for power stage

A_SEL 14DIO A value of 0(15-k Ωpulldown)makes the I 2C device address 0x34,and a value of 1(15-k Ωpullup)makes it 0x36.AVDD 13P 3.3-V analog power supply AVSS 9P Analog 3.3-V supply ground

BST_A 4P High-side bootstrap supply for half-bridge A BST_B 43P High-side bootstrap supply for half-bridge B BST_C 42P High-side bootstrap supply for half-bridge C BST_D 33P High-side bootstrap supply for half-bridge D DVDD 27P 3.3-V digital power supply DVSS 28P Digital ground DVSSO 17P Oscillator ground

GND 29

Analog ground for power stage

(1)TYPE:A =analog;D =3.3-V digital;P =power/ground/decoupling;I =input;O =output

(2)All pullups are weak pullups and all pulldowns are weak pulldowns.The pullups and pulldowns are included to assure proper input logic levels if the pins are left unconnected (pullups →logic 1input;pulldowns →logic 0input).

TAS5731 https://www.doczj.com/doc/4418333376.html, ZHCS602–DECEMBER2011

PIN FUNCTIONS(continued)

PIN5-V

TYPE(1)TERMINATION(2)DESCRIPTION

TOLERANT

NAME NO.

GVDD_OUT32P Gate drive internal regulator output

LRCLK20DI5-V Pulldown Input serial audio data left/right clock(sample-rate clock)

MCLK15DI5-V Pulldown Master clock input

NC5,7,–No connect

40,

41,

44,45

OSC_RES16AO Oscillator trim resistor.Connect an18.2-k?,1%resistor to DVSSO. OUT_A1O Output,half-bridge A

OUT_B46O Output,half-bridge B

OUT_C39O Output,half-bridge C

OUT_D36O Output,half-bridge D

PBTL8DI Low means BTL mode;high means PBTL https://www.doczj.com/doc/4418333376.html,rmation goes

directly to power stage.

PDN19DI5-V Pullup Power down,active-low.PDN prepares the device for loss of power

supplies by shutting down the noise shaper and initiating the PWM

stop sequence.

PGND_AB47,48P Power ground for half-bridges A and B

PGND_CD37,38P Power ground for half-bridges C and D

PLL_FLTM10AO PLL negative loop-filter terminal

PLL_FLTP11AO PLL positive loop-filter terminal

PVDD_AB2,3P Power-supply input for half-bridge output A

PVDD_CD34,35P Power-supply input for half-bridge output D

RESET25DI5-V Pullup Reset,active-low.A system reset is generated by applying a logic

low to this pin.RESET is an asynchronous control signal that

restores the DAP to its default conditions and places the PWM in the

hard-mute(high-impedance)state.

SCL24DI5-V I2C serial control clock input

SCLK21DI5-V Pulldown Serial audio-data clock(shift clock).SCLK is the serial-audio-port

input-data bit clock.

SDA23DIO5-V I2C serial control data interface input/output

SDIN22DI5-V Pulldown Serial audio data input.SDIN supports three discrete(stereo)data

formats.

SSTIMER6AI Controls ramp time of OUT_x to minimize pop.Leave this pin

floating for BD mode.Requires capacitor of2.2nF to GND in AD

mode.The capacitor determines the ramp time.

STEST26DI Factory test pin.Connect directly to DVSS.

VR_ANA12P Internally regulated1.8-V analog supply voltage.This pin must not

be used to power external devices.

VR_DIG18P Internally regulated1.8-V digital supply voltage.This pin must not be

used to power external devices.

VREG31P Digital regulator output.Not to be used for powering external

circuitry.

TAS5731

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range(unless otherwise noted)(1)

VALUE UNIT DVDD,AVDD–0.3to3.6V Supply voltage

PVDD_x–0.3to30V

3.3-V digital input–0.5to DVDD+0.5

Input voltage5-V tolerant(2)digital input(except MCLK)–0.5to DVDD+2.5(3)V 5-V tolerant MCLK input–0.5to AVDD+2.5(3)

OUT_x to PGND_x27(4)V

BST_x to PGND_x34(4)V

Input clamp current,I IK±20mA Output clamp current,I OK±20mA Operating free-air temperature0to85°C Operating junction temperature range0to150°C Storage temperature range,T stg–40to125°C (1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied.Exposure to absolute-maximum conditions for extended periods may affect device reliability.

(2)5-V tolerant inputs are PDN,RESET,SCLK,LRCLK,MCLK,SDIN,SDA,and SCL.

(3)Maximum pin voltage should not exceed6V.

(4)DC voltage+peak ac waveform measured at the pin should be below the allowed limit for all conditions.

THERMAL INFORMATION

TAS5731

THERMAL METRIC(1)UNIT

PHP(48PINS)

θJA Junction-to-ambient thermal resistance27.9°C/W

θJB Junction-to-board thermal resistance13°C/W

θJC(bottom)Junction-to-case(bottom)thermal resistance 1.1°C/W

θJC(top)Junction-to-case(top)thermal resistance20.7°C/W

ψJT Junction-to-top characterization parameter0.3°C/W

ψJB Junction-to-board characterization parameter 6.7°C/W (1)有关传统和新的热度量的更多信息，请参阅IC封装热度量应用报告SPRA953。

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT Digital/analog supply voltage DVDD,AVDD3 3.3 3.6V

Half-bridge supply voltage PVDD_x821(1)V

V IH High-level input voltage5-V tolerant2V

V IL Low-level input voltage5-V tolerant0.8V

T A Operating ambient temperature range085°C

T J(2)Operating junction temperature range0125°C

R L(BTL)Load impedance Output filter:L=15μH,C=680nF48?

Output filter:L=15μH,C=680nF,

PVDD_X=12V

R L(SE)Load impedance?

Output filter:L=15μH,C=680nF,

PVDD_X=18V

Minimum output inductance under

L O(BTL)Output-filter inductance10μH

short-circuit condition

(1)For operation at PVDD_x levels greater than18V,the modulation limit must be set to93.8%via the control port register0x10.

(2)Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.

TAS5731 https://www.doczj.com/doc/4418333376.html, ZHCS602–DECEMBER2011

PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS

PARAMETER TEST CONDITIONS VALUE UNIT

11.025/22.05/44.1-kHz data rate±2%352.8

Output PWM switch frequency kHz

48/24/12/8/16/32-kHz data rate±2%384

PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f MCLKI MCLK frequency 2.822424.576MHz

MCLK duty cycle40%50%60%

t r/

Rise/fall time for MCLK5ns

t f(MCLK)

LRCLK allowable drift before LRCLK reset4MCLKs External PLL filter capacitor C1SMD0603X7R47nF

External PLL filter capacitor C2SMD0603X7R 4.7nF

External PLL filter resistor R SMD0603,metal film470?ELECTRICAL CHARACTERISTICS

DC Characteristics

T A=25°,PVCC_x=18V,DVDD=AVDD=3.3V,R L=8?,BTL AD mode,f S=48kHz(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I OH=–4mA

V OH High-level output voltage SDIN and SDA 2.4V

DVDD=3V

I OL=4mA

V OL Low-level output voltage SDIN and SDA0.5V

DVDD=3V

V I

I IL Low-level input current75μA

=3.6V

V I>V IH;DVDD=

I IH High-level input current75(1)μA

AVDD=3.6V

Normal mode4968

3.3V supply voltage(DVDD,

I DD 3.3V supply current mA

Reset(RESET=low,

AVDD)2338

PDN=high)

Normal mode3250

I PVDD Supply current No load(PVDD_x)mA

Reset(RESET=low,

PDN=high)

Drain-to-source resistance,LS T J=25°C,includes metallization resistance75

r DS(on)(2)m?Drain-to-source resistance,HS T J=25°C,includes metallization resistance75

I/O Protection

V uvp Undervoltage protection limit PVDD falling 5.9V

V uvp,hyst Undervoltage protection limit PVDD rising 5.4V OTE(3)Overtemperature error150°C

Extra temperature drop

OTE HYST(3)30°C required to recover from error

I OC Overcurrent limit protection Output to output short in BTL mode 4.5A

I OCT Overcurrent response time150ns

(1)I IH for the PBTL pin has a maximum limit of200μA due to an internal pulldown on the pin.

(2)This does not include bond-wire or pin resistance.

(3)Specified by design

TAS5731

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AC Characteristics(BTL,PBTL)

PVDD_x=18V,BTL AD mode,f S=48KHz,R L=8?,R OCP=22k?,C BST=33nF,audio frequency=1kHz,AES17filter,

f PWM=384kHz,T A=25°C(unless otherwise specified).All performance is in accordance with recommended operatin

g conditions(unless otherwise specified).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

BTL mode,PVDD=18V,10%THD20.9

BTL mode,PVDD=18V,7%THD19.8

BTL mode,PVDD=12V,10%THD9.6

BTL mode,PVDD=12V,7%THD9.1

BTL mode,PVDD=8V,10%THD 4.2

BTL mode,PVDD=8V,7%THD4

PBTL mode,PVDD=12V,R L=4Ω,

18.7

10%THD

PBTL mode,PVDD=12V,R L=4Ω,

17.7

7%THD

P O Power output per channel

PBTL mode,PVDD=18V,R L=4Ω,

41.5

10%THD

PBTL mode,PVDD=18V,R L=4Ω,

7%THD

SE Mode,PVDD=12V,RL=4Ω,10%

4.6

THD

SE Mode,PVDD=12V,RL=4Ω,7%THD 4.3

SE Mode,PVDD=18V,RL=4Ω,10%

17.8

THD

SE Mode,PVDD=18V,RL=4Ω,7%THD16.8

PVDD=18V,P O=1W0.03%

THD+N Total harmonic distortion+noise PVDD=12V,P O=1W0.07%

PVDD=8V,P O=1W0.1%

V n Output integrated noise(rms)A-weighted56μV Cross-talk P O=0.25W,f=1kHz(AD Mode)–69dB

A-weighted,f=1kHz,maximum power at

SNR Signal-to-noise ratio(1)106dB

THD<1%

(1)SNR is calculated relative to0-dBFS input level.

SCLK (Input)

LRCLK (Input)

SDIN

T0026-04

TAS5731

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ZHCS602–DECEMBER 2011

SERIAL AUDIO PORTS SLAVE MODE

over recommended operating conditions (unless otherwise noted)

TEST PARAMETER

MIN TYP MAX UNIT CONDITIONS f SCLKIN Frequency,SCLK 32×f S ,48×f S ,64×f S C L =30pF

1.0241

2.288

MHz t su1Setup time,LRCLK to SCLK rising edge 10ns t h1Hold time,LRCLK from SCLK rising edge 10ns t su2Setup time,SDIN to SCLK rising edge 10ns t h2

Hold time,SDIN from SCLK rising edge 10ns

LRCLK frequency 84848kHz

SCLK duty cycle 40%50%60%LRCLK duty cycle

40%50%

60%SCLK SCLK rising edges between LRCLK rising edges

3264edges t (edge)SCLK LRCLK clock edge with respect to the falling edge of SCLK –1/4

1/4period t r /t f

Rise/fall time for SCLK/LRCLK

Figure 2.Slave-Mode Serial Data-Interface Timing

SCL

SDA

T0027-01 SCL

SDA

Start Condition

Stop

Condition

T0028-01

TAS5731

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I2C SERIAL CONTROL PORT OPERATION

Timing characteristics for I2C Interface signals over recommended operating conditions(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

f SCL Frequency,SCL No wait states400kHz

t w(H)Pulse duration,SCL high0.6μs

t w(L)Pulse duration,SCL low 1.3μs

t r Rise time,SCL and SDA300ns

t f Fall time,SCL and SDA300ns

t su1Setup time,SDA to SCL100ns

t h1Hold time,SCL to SDA0ns

t(buf)Bus free time between stop and start conditions 1.3μs

t su2Setup time,SCL to start condition0.6μs

t h2Hold time,start condition to SCL0.6μs

t su3Setup time,SCL to stop condition0.6μs

C L Load capacitance for each bus line400pF

Figure3.SCL and SDA Timing

Figure4.Start and Stop Conditions Timing

RESET

System Initialization.Enable via I C.

T0421-01

TAS5731

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ZHCS602–DECEMBER 2011

RESET TIMING Control signal parameters over recommended operating conditions (unless otherwise noted).Please refer to Recommended Use Model section on usage of all terminals.

PARAMETER

MIN TYP

MAX

UNIT t w(RESET)Pulse duration,RESET active 100

μs t d(I2C_ready)

Time to enable I 2C

NOTES:On power up,it is recommended that the TAS5731RESET be held LOW for at least 100μs after DVDD has

reached 3V.

If RESET is asserted LOW while PDN is LOW,then RESET must continue to be held LOW for at least 100μs after PDN is deasserted (HIGH).

Figure 5.Reset Timing

0.001

0.010.1

Frequency (Hz)

T H D +N (%)

G021

0.001

0.01

0.1

Frequency (Hz)

T H D +N (%)

G022

Output Power (W)

G024

1020

4050607080

90100

Total Output Power (W)

E f f i c i e n c y (%)

G001

TAS5731

ZHCS602–DECEMBER 2011

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TYPICAL CHARACTERISTICS,SE CONFIGURATION,4Ω

TOTAL HARMONIC DISTORTION +NOISE

FREQUENCY

Figure 6.

Figure 7.

TOTAL HARMONIC DISTORTION +NOISE

EFFICIENCY

OUTPUT POWER

TOTAL OUTPUT POWER

Figure 8.Figure 9.

0.001

0.010.1

Frequency (Hz)

T H D +N (%)

G001

0.001

0.01

0.1

110

Frequency (Hz)

T H D +N (%)

G002

Output Power (W)

T H D +N (%)

G004

Output Power (W)

T H D +N (%)

G005

TAS5731

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ZHCS602–DECEMBER 2011

TYPICAL CHARACTERISTICS,BTL CONFIGURATION,8Ω

TOTAL HARMONIC DISTORTION

FREQUENCY (BTL)

Figure 10.

Figure 11.

TOTAL HARMONIC DISTORTION +NOISE

OUTPUT POWER (BTL)

Figure 12.Figure 13.

?100

?90?80?70?60?50?40?30?20?100

Frequency (Hz)

C r o s s t a l k (d B )

G007

?100

?90?80?70?60?50?40?30?20?100

Frequency (Hz)

C r o s s t a l k (d B )

G008

10203040506070

90100

Total Output Power (W)

E f f i c i e n c y (%)

G010

1015202530

40Supply Voltage (V)

O u t p u t P o w e r (W )

G011

TAS5731

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TYPICAL CHARACTERISTICS,BTL CONFIGURATION,8Ω(continued)

CROSSTALK

FREQUENCY

Figure 14.Figure 15.

EFFICIENCY

OUTPUT POWER

SUPPLY VOLTAGE (BTL)

Figure 16.Figure 17.

TAS5731 https://www.doczj.com/doc/4418333376.html, ZHCS602–DECEMBER2011

DETAILED DESCRIPTION

POWER SUPPLY

To facilitate system design,the TAS5731needs only a3.3-V supply in addition to the(typical)18-V power-stage supply.An internal voltage regulator provides suitable voltage levels for the gate drive circuitry.Additionally,all circuitry requiring a floating voltage supply,e.g.,the high-side gate drive,is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.

In order to provide good electrical and acoustical characteristics,the PWM signal path for the output stage is designed as identical,independent half-bridges.For this reason,each half-bridge has separate bootstrap pins (BST_x),and power-stage supply pins(PVDD_x).The gate-drive voltage(GVDD_OUT)is derived from the PVDD voltage.Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible.Inductance between the power-supply pins and decoupling capacitors must be avoided.

For a properly functioning bootstrap circuit,a small ceramic capacitor must be connected from each bootstrap pin (BST_x)to the power-stage output pin(OUT_x).When the power-stage output is low,the bootstrap capacitor is charged through an internal diode connected between the gate-drive regulator output pin(GVDD_OUT)and the bootstrap pin.When the power-stage output is high,the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver.In an application with PWM switching frequencies in the range from288kHz to384kHz,it is recommended to use33-nF,X7R ceramic capacitors,size0603or0805,for the bootstrap supply.These33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles,to keep the high-side power-stage FET(LDMOS)fully turned on during the remaining part of the PWM cycle.

Special attention should be paid to the power-stage power supply;this includes component selection,PCB placement,and routing.As indicated,each half-bridge has independent power-stage supply pins(PVDD_x).For optimal electrical performance,EMI compliance,and system reliability,it is important that each PVDD_x pin is decoupled with a100-nF,X7R ceramic capacitor placed as close as possible to each supply pin.

The TAS5731is fully protected against erroneous power-stage turnon due to parasitic gate charging.

I2C ADDRESS

I2C address is0x36after reset,but it can be changed using the following procedure.

I2C Device Address Change Procedure

?Write to device address change enable register,0xF8with a value of0xF9A5A5A5.

?Write to device register0xF9with a value of0x000000XX,where XX is the new address.

?Any writes after that should use the new device address XX.

SINGLE-FILTER PBTL MODE

The TAS5731supports parallel BTL(PBTL)mode with OUT_A/OUT_B(and OUT_C/OUT_D)connected before the LC filter.In order to put the part in PBTL configuration,drive PBTL(pin8)HIGH.This synchronizes the turnoff of half-bridges A and B(and similarly C/D)if an overcurrent condition is detected in either half-bridge. There is a pulldown resistor on the PBTL pin that configures the part in BTL mode if the pin is left floating.

PWM output multiplexers should be updated to set the device in PBTL mode.Output Mux Register(0x25)should be written with a value of0x01103245.

DEVICE PROTECTION SYSTEM

Overcurrent(OC)Protection With Current Limiting

The device has independent,fast-reacting current detectors on all high-side and low-side power-stage FETs.The detector outputs are closely monitored by a protection system.If the high-current condition situation persists,i.e.,

TAS5731

ZHCS602–https://www.doczj.com/doc/4418333376.html, the power stage is being overloaded,a protection system triggers a latching shutdown,resulting in the power stage being set in the high-impedance(Hi-Z)state.The device returns to normal operation once the fault condition(i.e.,a short circuit on the output)is removed.Current-limiting and overcurrent protection are not independent for half-bridges.That is,if the bridge-tied load between half-bridges A and B causes an overcurrent fault,half-bridges A,B,C,and D are shut down.

Overtemperature Protection

The TAS5731has an overtemperature-protection system.If the device junction temperature exceeds150°C (nominal),the device is put into thermal shutdown,resulting in all half-bridge outputs being set in the high-impedance(Hi-Z)state.The TAS5731recovers automatically once the temperature drops approximately 30°C.

Undervoltage Protection(UVP)and Power-On Reset(POR)

The UVP and POR circuits of the TAS5731fully protect the device in any power-up/down and brownout situation. While powering up,the POR circuit resets the overload circuit(OLP)and ensures that all circuits are fully operational when the PVDD and AVDD supply voltages reach7.6V and2.7V,respectively.Although PVDD and AVDD are independently monitored,a supply-voltage drop below the UVP threshold on AVDD or either PVDD pin results in all half-bridge outputs immediately being set in the high-impedance(Hi-Z)state.

SSTIMER FUNCTIONALITY

The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when exiting all-channel shutdown.The capacitor on the SSTIMER pin is slowly charged through an internal current source,and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the desired duty cycle.This allows for a smooth transition that minimizes audible pops and clicks.When the part is shut down,the drivers are placed in the high-impedance state and transition slowly down through a3-k?resistor, similarly minimizing pops and clicks.The shutdown transition time is independent of the SSTIMER pin https://www.doczj.com/doc/4418333376.html,rger capacitors increase the start-up time,while capacitors smaller than2.2nF decrease the start-up time.The SSTIMER pin should be left floating for BD modulation.

CLOCK,AUTODETECTION,AND PLL

The TAS5731is an I2S slave device.It accepts MCLK,SCLK,and LRCLK.The digital audio processor(DAP) supports all the sample rates and MCLK rates that are defined in the clock control register.

The TAS5731checks to verify that SCLK is a specific value of32f S,48f S,or64f S.The DAP only supports a1×f S LRCLK.The timing relationship of these clocks to SDIN is shown in subsequent sections.The clock section uses MCLK or the internal oscillator clock(when MCLK is unstable,out of range,or absent)to produce the internal clock(DCLK)running at512times the PWM switching frequency.

The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock rates as defined in the clock-control register.

The TAS5731has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect changes/errors.Once the system detects a clock change/error,it mutes the audio(through a single-step mute) and then forces PLL to limp using the internal oscillator as a reference clock.Once the clocks are stable,the system autodetects the new rate and reverts to normal operation.During this process,the default volume is restored in a single step(also called hard unmute).The ramp process can be programmed to ramp back slowly (also called soft unmute)as defined in volume register(0x0E).

SERIAL DATA INTERFACE

Serial data is input on SDIN.The PWM outputs are derived from SDIN.The TAS5731DAP accepts serial data in 16-,20-,or24-bit left-justified,right-justified,and I2S serial data formats.

PWM SECTION

The TAS5731DAP device uses noise-shaping and customized nonlinear correction algorithms to achieve high power efficiency and high-performance digital audio reproduction.The DAP uses a fourth-order noise shaper to increase dynamic range and SNR in the audio band.The PWM section accepts24-bit PCM data from the DAP and outputs two BTL PWM audio output channels.

2-Channel I S (Philips Format) Stereo Input

T0034-01

TAS5731

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ZHCS602–DECEMBER 2011

The PWM section has individual-channel dc-blocking filters that can be enabled and disabled.The filter cutoff frequency is less than 1Hz.Individual-channel de-emphasis filters for 44.1kHz and 48kHz are included and can be enabled and disabled.

Finally,the PWM section has an adjustable maximum modulation limit of 93.8%to 99.2%.

For a detailed description of using audio processing features like DRC and EQ,see the User's Guide and TAS570X GDE software development tool documentation.

SERIAL INTERFACE CONTROL AND TIMING

I 2S Timing

I 2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel.LRCLK is low for the left channel and high for the right channel.A bit clock running at 32,48,or 64×f S is used to clock in the data.There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines.The data is written MSB-first and is valid on the rising edge of bit clock.The DAP masks unused trailing data bit positions.

NOTE:All data presented in 2s-complement form with MSB first.

Figure 18.I 2S 64-f S Format

2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)

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2-Channel I S (Philips Format) Stereo Input

T0266-01

TAS5731

ZHCS602–DECEMBER 2011

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NOTE:All data presented in 2s-complement form with MSB first.

Figure 19.I 2S 48-f S Format

NOTE:All data presented in 2s-complement form with MSB first.

Figure 20.I 2S 32-f S Format

Left-Justified

Left-justified (LJ)timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel.LRCLK is high for the left channel and low for the right channel.A bit clock running at 32,48,or 64×f S is used to clock in the data.The first bit of data appears on the data lines at the same time LRCLK toggles.The data is written MSB-first and is valid on the rising edge of the bit clock.The DAP masks unused trailing data bit positions.