1
2
3
4
5
6
7
14
13
12
11
10
9
8
1 OUT
1 IN?
1 IN+
V CC?
N/C
REF
N/C
V CC+
2 OUT
2 IN?
2 IN+
N/C
SHUTDOWN
N/C 1
10
100
0.010.1110100
f?Frequency?kHz
VOLTAGE NOISE AND CURRENT NOISE
vs
FREQUENCY
V
V
o
l
t
a
g
e
N
o
i
s
e
n
V
/
I
C
u
r
r
e
n
t
N
o
i
s
e
p
A
/
-
-
-
-
n n
H
z
H
z
??
V
CC+
THS3122
SOIC (D) AND
SOIC PowerPAD(DDA) PACKAGE
(TOP VIEW)
?
THS3125
SOIC (D) AND
TSSOP PowerPAD(PWP) PACKAGE
(TOP VIEW)
?
THS3122
THS3125
https://www.doczj.com/doc/417745230.html, SLOS382D–SEPTEMBER2001–REVISED FEBRUARY2011 LOW-NOISE,HIGH-SPEED,450-mA CURRENT FEEDBACK AMPLIFIERS
Check for Samples:THS3122,THS3125
FEATURES APPLICATIONS
?Video Distribution
?Low Noise:
?Instrumentation
– 2.9-pA/√Hz Noninverting Current Noise
?Line Drivers
–10.8-pA/√Inverting Current Noise
?Motor Drivers
– 2.2-nV/√Hz Voltage Noise
?Piezo Drivers
–128-MHz,–3-dB BW(R L=50?,R F=470?)
–1550-V/μs Slew Rate(G=2,R L=50?)DESCRIPTION
?High Output Current:450mA
The THS3122/5are low-noise,high-speed current ?High Speed:feedback amplifiers,with high output current drive.
–128-MHz,–3-dB BW(R L=50?,R F=470?)This makes them ideal for any application that
requires low distortion over a wide frequency with –1550-V/μs Slew Rate(G=2,R L=50?)
heavy loads.The THS3122/5can drive four –26-V PP Output Voltage,R L=50?serially-terminated video lines while maintaining a
––80dBc(1MHz,2V PP,G=2)differential gain error less than0.03%.
?Wide Output Swing:The high output drive capability of the THS3122/5–26-V PP Output Voltage,R L=50?enables the devices to drive50-?loads with low
distortion over a wide range of output voltages:––80dBc(1MHz,2V PP,G=2)
?–80-dBc THD at2V PP
–370-μA Shutdown Supply Current
?-75-dBc THD at8V PP
?Low Distortion:
The THS3122/5can operate from±5-V to±15-V ––80dBc(1MHz,2V PP,G=2)
supply voltages while drawing as little as7.2mA of –370-μA Shutdown Supply Current supply current per channel.The THS3125offers a
?Low-Power Shutdown Mode(THS3125)low-power shutdown mode,reducing the supply
current to only370μA.The THS3122/5are packaged –370-μA Shutdown Supply Current
in a standard SOIC,SOIC PowerPAD?,and TSSOP ?Standard SOIC,SOIC PowerPAD?,and
PowerPAD packages.
TSSOP PowerPAD Packages
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.?2001–2011,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas
Instruments standard warranty.Production processing does not
necessarily include testing of all parameters.
THS3122
THS3125
SLOS382D–SEPTEMBER2001–REVISED https://www.doczj.com/doc/417745230.html, This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS(1)
PACKAGED DEVICE
EVALUATION T A SOIC-8SOIC-8PowerPAD SOIC-14TSSOP-14
MODULES
(D)(DDA)(D)(PWP)
0°C to+70°C THS3122CD THS3122CDDA THS3125CD THS3125CPWP THS3122EVM
THS3125EVM 40°C to+85°C THS3122ID THS3122IDDA THS3125ID THS3125IPWP
(1)For the most current specification and package information,refer to the Package Option Addendum located at the end of this data sheet
or see the TI web site at https://www.doczj.com/doc/417745230.html,.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature(unless otherwise noted).
UNIT
Supply voltage,V CC+to V CC–33V
Input voltage±V CC
Output current(see(2))550mA
Differential input voltage±4V
Maximum junction temperature+150°C
Total power dissipation at(or below)+25°C free-air temperature See Dissipation Ratings Table
Commercial0°C to+70°C
Operating free-air temperature,T A
Industrial–40°C to+85°C
Commercial–65°C to+125°C
Storage temperature,T stg
Industrial–65°C to+125°C
(1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratings
only,and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)The THS3122and THS3125may incorporate a PowerPAD?on the underside of the chip.This pad acts as a heatsink and must be
connected to a thermally dissipating plane for proper power dissipation.Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device.See TI Technical Brief SLMA002for more information about utilizing the PowerPAD?thermally-enhanced package.
DISSIPATION RATING TABLE
T A=+25°C
PACKAGEθJA
POWER RATING
D-895°C/W(1) 1.32W
DDA67°C/W 1.87W
D-1466.6°C/W(1) 1.88W
PWP37.5°C/W 3.3W
(1)These data were taken using the JEDEC proposed high-K test PCB.
For the JEDEC low-K test PCB,theθJA is168°C/W for the D-8
package and122.3°C/W for the D-14package.
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SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT Dual supply ±5±15Supply voltage,V CC+to V CC –V Single supply 1030C-suffix 0+70Operating free-air temperature,T A
°C
I-suffix
–40
+85
ELECTRICAL CHARACTERISTICS
Over operating free-air temperature range,T A =+25°C,V CC =±15V,R F =750?,and R L =100?(unless otherwise noted).
DYNAMIC PERFORMANCE
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
V CC =±5V 138R L =50?
R F =50?,G =1
V CC =±15V 160Small-signal bandwidth (–3dB)
V CC =±5V 126R F =470?,G =R L =50?
MHz 2
V CC =±15V 128BW
V CC =±5V 20Bandwidth (0.1dB)R F =470?,G =2V CC =±15V 30V O(PP)=4V V CC =±5V 47Full power bandwidth
G =-1
MHz V O(pp)=20V V CC =±15V 64V O =10V PP
V CC =±15V 1550SR
Slew rate (1),G =8
G =2,R F =680?
V CC =±5V 500V/μs V O =5V PP V CC =±15V 1000V O =2V PP V CC =±5V 53t s Settling time to 0.1%G =-1
ns V O =5V PP V CC =±15V
64
(1)
Slew rate is defined from the 25%to the 75%output levels.
NOISE/DISTORTION PERFORMANCE
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
V O(PP)=2V –80G =2,R F =470?,V CC =±15V,f =1MHz
V O(PP)=8V –75THD
Total harmonic distortion
dBc V O(PP)=2V –77G =2,R F =470?,V CC =±5V,f =1MHz
V O(PP)=5V –76V n Input voltage noise V CC =±5V,±15V f =10kHz 2.2nV/√Hz Noninverting Input 2.9I n
Input current noise V CC =±5V,±15V
f =10kHz pA/√Hz Invertin
g Input
10.8V CC =±5V –67Crosstalk
G =2,f =1MHz,V O =2V PP dBc V CC =±15V –67V CC =±5V 0.01G =2,R L =150?Differential gain error %V CC =±15V 0.0140IRE modulation ±100IRE Ramp V CC =±5V 0.011Differential phase error
degrees NTSC and PAL
V CC =±15V
0.011
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ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range,T A =+25°C,V CC =±15V,R F =750?,and R L =100?(unless otherwise noted).
DC PERFORMANCE
PARAMETER TEST CONDITIONS
MIN
TYP MAX UNIT
T A =+25°C 6
10Input offset voltage
T A =full range 13mV V IC =0V,V O =0V,
V IO
T A =+25°C 1
3V CC =±5V,V CC =±15V
Channel offset voltage matching T A =full range 4
Offset drift
T A =full range 10μV/°C T A =+25°C 6
23IN-Input bias current
T A =full range 30V IC =0V,V O =0V,
I IB
μA
V CC =±5V,V CC =±15V T A =+25°C 0.332IN+Input bias current
T A =full range
3T A =+25°C 5.422V IC =0V,V O =0V,
I IO Input offset current μA V CC =±5V,V CC =±15V T A =full range 30
Z OL
Open-loop transimpedance
V CC =±5V,V CC =±15V
R L =1k ?
1M ?INPUT CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
V CC =±5V
±2.5±2.7V ICR
Input common-mode voltage range
T A =full range V
±12.±12.V CC =±15V 57T A =+25°C 5862
V CC =±5V,
V I =-2.5V to 2.5V T A =full range 56CMRR Common-mode rejection ratio
dB T A =+25°C 6367V CC =±15V,
V I =–12.5V to 12.5V
T A =full range
60
IN+ 1.5M ?R I Input resistance IN –
15?C I
Input capacitance
2
pF
OUTPUT CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT G =4,V I =1.06V,V CC =±5V R L =1k ?T A =+25°C 4.1V
T A =+25°C 3.84
G =4,
V I =1.025V,V CC =±5V,R L =50?T A =full 3.7
V
range V O
Output voltage swing
G =4,V I =3.6V,V CC =±15V,
R L =1k ?
T A =+25°C 14.2T A =+25°C
1213.3
G =4,V I =3.325V,V CC =±15V,R L =50?V T A =full 11.5range G =4,
V I =1.025V,V CC =±5V,R L =10?T A =+25°C 200280mA I O Output current drive V I =3.325V,V CC =±15G =4,R L =25?
T A =+25°C 360
440mA V,
r o
Output resistance
Open loop
T A =+25°C
14
?
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THS3125 https://www.doczj.com/doc/417745230.html, SLOS382D–SEPTEMBER2001–REVISED FEBRUARY2011 ELECTRICAL CHARACTERISTICS(continued)
Over operating free-air temperature range,T A=+25°C,V CC=±15V,R F=750?,and R L=100?(unless otherwise noted). POWER SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
T A=+25°C7.29
V CC=±5V
T A=full range10
I CC Quiescent current(per channel)mA
T A=+25°C8.410.5
V CC=±15V
T A=full range11.5
T A=+25°C5360
V CC=±5V±1V
T A=full range50
PSRR Power-supply rejection ratio dB
T A=+25°C6069
V CC=±15V±1V
T A=full range55
SHUTDOWN CHARACTERISTICS(THS3125Only)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Shutdown quiescent current(per
I CC(SHDN)V SHDN=3.3V370500μA
channel)
t DIS Disable time(1)500μs
REF=0V,
t EN Enable time(1)V CC=±5V to±15V200μs
I IL(SHDN)Shutdown pin low level leakage current V SHDN=0V1825μA
I IH(SHDN)Shutdown pin high level leakage current V SHDN=3.3V110130μA
V REF REF pin voltage level V CC–V CC+–4V
Enable REF+0.8
V SHDN SHUTDOWN pin voltage level V
Disable REF+2
(1)Disable/enable time is defined as the time from when the shutdown signal is applied to the SHDN pin to when the supply current has
reached half of its final value.
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE Small-signal closed-loop gain vs Frequency Figure1to Figure10
Small-and large-signal output vs Frequency Figure11,Figure12
vs Frequency Figure13to Figure15 Harmonic distortion
vs Peak-to-peak output voltage Figure16,Figure17
V n,I n Voltage noise and current noise vs Frequency Figure18
CMRR Common-mode rejection ratio vs Frequency Figure19 Crosstalk vs Frequency Figure20
Z o Output impedance vs Frequency Figure21
SR Slew rate vs Output voltage step Figure22
vs Free-air temperature Figure24
V IO Input offset voltage
vs Common-mode input voltage Figure24
I B Input bias current vs Free-air temperature Figure25
V O Output voltage vs Load current Figure26
vs Free-air temperature Figure27 Quiescent current
vs Supply voltage Figure28
I CC Shutdown supply current vs Free-air temperature Figure29
Differential gain and phase error vs75-?serially terminated loads Figure30,Figure31
Shutdown response Figure32
Small-signal pulse response Figure33,Figure34
Large-signal pulse response Figure35,Figure36
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f ? Frequency ? MHz S m a l l S i
g n a l C l o s e d L o o p G a i n ? d B
f ? Frequency ? MHz
S m a l l S i g n a l C l o s e d L o o p G a i n ? d
B
f ? Frequency ? MHz S m a l l S i
g n a l C l o s e d L o o p G a i n ? d
B
f ? Frequency ? MHz
S m a l l S i g n a l C l o s e d L o o p G a i n ? d
B
f ? Frequency ? MHz S m a l l S i
g n a l C l o s e d L o o p G a i n ? d B
f ? Frequency ? MHz S m a l l S i
g n a l C l o s e d L o o p G a i n ? d B
f ? Frequency ? MHz
S m a l l S i g n a l C l o s e d L o o p G a i n ? d
B
f ? Frequency ? MHz S m a l l S i
g n a l C l o s e d L o o p G a i n ? d
B
f ? Frequency ? MHz
S m a l l S i g n a l C l o s e d L o o p G a i n ? d B
THS3122THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
https://www.doczj.com/doc/417745230.html,
TYPICAL CHARACTERISTICS
SMALL-SIGNAL CLOSED-LOOP
SMALL-SIGNAL CLOSED-LOOP
SMALL-SIGNAL CLOSED-LOOP
GAIN GAIN GAIN vs
vs
vs
Figure 1.
Figure 2.
Figure 3.
SMALL-SIGNAL CLOSED-LOOP
SMALL-SIGNAL CLOSED-LOOP
SMALL-SIGNAL CLOSED-LOOP
GAIN GAIN GAIN vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
Figure 4.
Figure 5.
Figure 6.
SMALL-SIGNAL CLOSED-LOOP
SMALL-SIGNAL CLOSED-LOOP
SMALL-SIGNAL CLOSED-LOOP
GAIN GAIN GAIN vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
Figure 7.Figure 8.Figure 9.
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f ? Frequency ? MHz S m a l l S i
g n a l C l o s e d L o o p G a i n ? d B
f ? Frequency ? MHz S m a l l a n d L a r
g e S i g n a l O u t p u t ? d B
f ? Frequency ? MHz
S m a l l a n d L a r g e S i g n a l O u t p u t ? d B
f ? Frequency ? MHz
H a r m o n i c D i s t o r t i o n ? d B
f ? Frequency ? MHz
H a r m o n i c D i s t o r t i o n ? d B
f ? Frequency ? MHz H a r m o n i c D i s t o r t i o n ? d B
V PP ? Peak-to-Peak Output Voltage ? V
H a r m o n i c D i s t o r t i o n ? d B
V PP ? Peak-to-Peak Output Voltage ? V
H a r m o n i c D i s t o r t i o n ? d B
110
1000.01
0.1
1
10
100
f ? Frequency ? kHz
? C u r r e n t N o i s e ?V n I n ? V o l t a g e N o i s e ? p A /H z
n V /
H z THS3122THS3125
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SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
TYPICAL CHARACTERISTICS (continued)
SMALL-AND LARGE-SIGNAL
SMALL-AND LARGE-SIGNAL
SMALL-SIGNAL CLOSED-LOOP
GAIN OUTPUT OUTPUT vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
Figure 10.
Figure 11.
Figure 12.
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
Figure 13.Figure 14.Figure 15.
VOLTAGE NOISE AND CURRENT
HARMONIC DISTORTION
HARMONIC DISTORTION
NOISE vs
vs
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
FREQUENCY
Figure 16.Figure 17.Figure 18.
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Product Folder Link(s):THS3122THS3125
f ? Frequency ? MHz
C r o s s t a l k ? d B c
f ? Frequency ? MHz C M R R ? C o m m o n -M o d e R e j e c t i o n R a t i o ? d B
0.1
1
10
100
1000
f ? Frequency ? MHz
? O u t p u t I m p e d a n c e ??
Z O V O ? Output Voltage Step ? V S R ? S l e w R a t e ? s
μV /10
T A ? Free-Air Temperature ? °C ? I n p u t O f f s e t V o l t a g e ? m V
V I O
V CM ? Common-Mode Input Voltage ? V
? I n p u t O f f s e t V o l t a g e ? m V
V I O
? Q u i e s c e n t C u r r e n t ? m A / P e r C h a n n e l
I C C T A ? Free-Air Temperature ? °C
I L ? Load Current ? mA
? O u t p u t V o l t a g e ? V
V O T A ? Free-Air Temperature ? °C
? I n p u t B i a s C u r r e n t ? I I B A
μTHS3122THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
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TYPICAL CHARACTERISTICS (continued)
COMMON-MODE REJECTION RATIO
CROSSTALK
OUTPUT IMPEDANCE
vs
vs
vs
FREQUENCY
FREQUENCY
Figure 19.
Figure 20.
Figure 21.
SLEW RATE
INPUT OFFSET VOLTAGE
INPUT OFFSET VOLTAGE
vs
vs
vs
OUTPUT VOLTAGE STEP
FREE-AIR TEMPERATURE
COMMON-MODE INPUT VOLTAGE
Figure 22.
Figure 23.Figure 24.
INPUT BIAS CURRENT
OUTPUT VOLTAGE
QUIESCENT CURRENT
vs
vs
vs
FREE-AIR TEMPERATURE
LOAD CURRENT
FREE-AIR TEMPERATURE
Figure 25.Figure 26.Figure 27.
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050100150200250300350400450
T A ? Free-Air Temperature ? °C
S h u t d o w n S u p p l y C u r r e n t ?
A μ0
24681012
? Q u i e s c e n t C u r r e n t ? m A
I C C V CC ? Supply Voltage ? ±V
t ? Time ? ns
? O u t p u t V o l t a g e ? V
V O 00.010.02
0.030.04
0.05
0.060.070.0875 ? Serially Terminated Loads D i f f e r e n r t i a l G a i n E r r o r ? %
D i f f e r e n t i a l P h a s e
E r r o r ? D e g r e e °
t ? Time ? ns
? O u t p u t V o l t a g e ? V
V O
t ? Time ? ns ? O u t p u t V o l t a g e ? V
S h u t d o w n P u l s e ? V
V O THS3122THS3125
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SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
TYPICAL CHARACTERISTICS (continued)
QUIESCENT CURRENT
SHUTDOWN SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
Figure 28.
Figure 29.
DIFFERENTIAL PHASE AND GAIN ERROR
DIFFERENTIAL PHASE AND GAIN ERROR
vs
vs
75-?SERIALLY-TERMINATED LOADS
75-?SERIALLY-TERMINATED LOADS
Figure 30.
Figure 31.
THS3125
THS3125
SHUTDOWN RESPONSE
SHUTDOWN RESPONSE
Figure 32.Figure 33.
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t ? Time ? ns
? O u t p u t V o l t a g e ? V
V O
100
200
300
400
500
600
t ? Time ? ns ? O u t p u t V o l t a g e ? V
V O
100
200
300
400
500
600
t ? Time ? ns ? O u t p u t V o l t a g e ? V
V O THS3122THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
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TYPICAL CHARACTERISTICS (continued)
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
Figure 34.Figure 35.Figure 36.
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+
+
+
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APPLICATION INFORMATION
Current-feedback amplifiers are highly dependent on Maximum Slew Rate for Repetitive Signals
the feedback resistor R F for maximum performance The THS3125and THS3122are recommended for
and stability.Table 1shows the optimal gain setting high slew rate pulsed applications where the internal resistors R F and R G at different gains to give nodes of the amplifier have time to stabilize between maximum bandwidth with minimal peaking in the pulses.It is recommended to have at least 20-ns frequency response.Higher bandwidths can be delay between pulses.
achieved,at the expense of added peaking in the frequency response,by using even lower values for The THS3125and THS3122are not recommended R F .Conversely,increasing R F decreases the for applications with repetitive signals (sine,square,bandwidth,but stability is improved.
sawtooth,or other)that exceed 900V/μhttps://www.doczj.com/doc/417745230.html,ing the part in these applications results in excessive current Table 1.Recommended Resistor Values for
draw from the power supply and possible device Optimum Frequency Response
damage.
THS3125and THS3122R F and R G VALUES FOR MINIMAL For applications with high slew rate,repetitive signals,PEAKING WITH R L =50Ω,±5-V to ±15-V POWER SUPPLY the THS3091and THS3095(single versions),or GAIN (V/V)
R G (Ω)R F (Ω)THS3092and THS3096(dual versions)are 1—560recommended.
24704704
66.5
200
Wideband,Noninverting Operation
The THS3125and THS3122are unity gain stable Wideband,Inverting Operation
130-MHz current-feedback operational amplifiers,designed to operate from a ±5-V to ±15-V power Figure 38shows the THS3125in a typical inverting supply.
gain configuration where the input and output impedances from Figure 37are retained in an Figure 37shows the THS3125in a noninverting gain inverting circuit configuration.
of 2-V/V configuration used to generate the typical characteristic curves.Most of the curves were characterized using signal sources with 50-Ωsource impedance and with measurement equipment that presents a 50-Ωload impedance.
Figure 38.Wideband,Inverting Gain
Configuration
Figure 37.Wideband,Noninverting Gain
Configuration
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Single-Supply Operation
The THS3125and THS3122have the capability to operate from a single supply voltage ranging from 10V to 30V.When operating from a single power supply,biasing the input and output at mid-supply allows for the maximum output voltage swing.The circuits in Figure 39show inverting and noninverting amplifiers configured for single-supply operation.
Figure 40.Video Distribution Amplifier
Application Driving Capacitive Loads
Applications such as FET drivers and line drivers can be highly capacitive and cause stability problems for high-speed amplifiers.
Figure 41through Figure 47show recommended methods for driving capacitive loads.The basic idea is to use a resistor or ferrite chip to isolate the phase shift at high frequency caused by the capacitive load from the amplifier feedback path.See Figure 41for recommended resistor values versus capacitive load.
Figure 39.DC-Coupled,Single-Supply Operation Video Distribution
The wide bandwidth,high slew rate,and high output drive current of the THS3125and THS3122match the demands for video distribution to deliver video signals down multiple cables.To ensure high signal quality with minimal degradation of performance,a 0.1-dB gain flatness should be at least 7x the passband frequency to minimize group delay Figure 41.Recommended R ISO vs Capacitive
variations from the amplifier.A high slew rate Load
minimizes distortion of the video signal,and supports component video and RGB video signals that require fast transition times and fast settling times for high signal quality.Figure 40illustrates a typical video distribution amplifier application configuration.
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Placing a small series resistor,R ISO,between the Figure44shows another method used to maintain amplifier output and the capacitive load,as shown in the low-frequency load independence of the amplifier Figure42,is an easy way of isolating the load while isolating the phase shift caused by the capacitance.capacitance at high frequency.At low frequency,
feedback is mainly from the load side of R ISO.At high
frequency,the feedback is mainly via the27-pF
capacitor.The resistor R IN in series with the negative
input is used to stabilize the amplifier and should be
equal to the recommended value of R F at unity gain.
Replacing R IN with a ferrite of similar impedance at
about100MHz as shown in Figure45gives similar
results with reduced dc offset and low frequency
noise.
Figure42.Resistor to Isolate Capacitive Load
Using a ferrite chip in place of R ISO,as Figure43
shows,is another approach of isolating the output of
the amplifier.The ferrite impedance characteristic
versus frequency is useful to maintain the low
frequency load independence of the amplifier while
isolating the phase shift caused by the capacitance at
high https://www.doczj.com/doc/417745230.html,e a ferrite with similar impedance
to R ISO,20Ωto50Ω,at100MHz and low Figure44.Feedback Technique with Input impedance at dc.Resistor for Capacitive Load
Figure43.Ferrite Bead to Isolate Capacitive Load
Figure45.Feedback Technique with Input Ferrite
Bead for Capacitive Load
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Figure 46shows a configuration that uses two Saving Power with Shutdown Functionality amplifiers in parallel to double the output drive current and Setting Threshold Levels with the to larger capacitive loads.This technique is used Reference Pin
when more output current is needed to charge and The THS3125features a shutdown pin discharge the load faster as when driving large FET (SHUTDOWN)that lowers the quiescent current from transistors.
8.4mA/amp down to 370μA/amp,ideal for reducing system power.
The shutdown pin of the amplifier defaults to the REF pin voltage in the absence of an applied voltage,putting the amplifier in the normal on mode of operation.To turn off the amplifier in an effort to conserve power,the shutdown pin can be driven towards the positive rail.The threshold voltages for power-on and power-down (or shutdown)are relative to the supply rails and are given in the Shutdown Characteristics (THS3125Only)table.Below the Enable threshold voltage,the device is on.Above the Disable threshold voltage,the device is off.Behavior between these threshold voltages is not specified.Note that this shutdown functionality is self-defining:the amplifier consumes less power in shutdown mode.The shutdown mode is not intended to provide a high-impedance output.In other words,the shutdown functionality is not intended to allow use as Figure 46.Parallel Amplifiers for Higher Output
a 3-state bus driver.When in shutdown mode,the Drive impedance looking back into the output of the amplifier is dominated by the feedback and gain setting resistors,but the output impedance of the Figure 47shows a push-pull FET driver circuit typical device itself varies depending on the voltage applied of ultrasound applications with isolation resistors to to the outputs.
isolate the gate capacitance from the amplifier.
As with most current feedback amplifiers,the internal architecture places some limitations on the system when in shutdown mode.Most notably is the fact that the amplifier actually turns on if there is a ±0.7V or greater difference between the two input nodes (IN+and IN –)of the amplifier.If this difference exceeds ±0.7V,the output of the amplifier creates an output voltage equal to approximately [(IN+–IN –)–0.7V]×Gain.Also,if a voltage is applied to the output while in shutdown mode,the IN –node voltage is equal to V O(applied)×R G /(R F +R G ).For low gain configurations and a large applied voltage at the output,the amplifier may actually turn on because of the behavior described here.
The time delays associated with turning the device on and off are specified as the time it takes for the amplifier to reach either 10%or 90%of the final output voltage.The time delays are in the order of microseconds because the amplifier moves in and out Figure 47.PowerFET Drive Circuit
of the linear mode of operation in these transitions.
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Power-Down Reference Pin Operation Printed-Circuit Board Layout Techniques for
Optimal Performance
In addition to the shutdown pin,the THS3125
features a reference pin(REF)which allows the user Achieving optimum performance with high-frequency to control the enable or disable power-down voltage amplifiers such as the THS3125and THS3122 levels applied to the SHUTDOWN pin.In most requires careful attention to board layout parasitic and split-supply applications,the reference pin is external component types.Recommendations that connected to ground.In either case,the user must be optimize performance include:
aware of voltage-level thresholds that apply to the?Minimize parasitic capacitance to any ac ground shutdown pin.Table2shows examples and illustrate for all of the signal I/O pins.Parasitic capacitance the relationship between the reference voltage and on the output and input pins can cause instability. the power-down thresholds.In the table,the threshold To reduce unwanted capacitance,a window levels are derived by the following equations:around the signal I/O pins should be opened in all
of the ground and power planes around those SHUTDOWN≤REF+0.8V for enable
pins.Otherwise,ground and power planes should SHUTDOWN≥REF+2V for disable be unbroken elsewhere on the board.
Where the usable range at the REF pin is:?Minimize the distance[0.25inch,(6,4mm)]from
the power-supply pins to high-frequency0.1-μF V CC–≤V REF≤(V CC+–4V)
and100-pF decoupling capacitors.At the device The recommended mode of operation is to tie the pins,the ground and power plane layout should REF pin to midrail,therefore setting the not be in close proximity to the signal I/O pins. enable/disable thresholds to V(midrail)+0.8V and Avoid narrow power and ground traces to V(midrail)=2V,respectively.minimize inductance between the pins and the
decoupling capacitors.The power-supply Table2.Shutdown Threshold Voltage Levels connections should always be decoupled with
these https://www.doczj.com/doc/417745230.html,rger(6.8μF or more) REFERENCE
tantalum decoupling capacitors,effective at lower SUPPLY PIN ENABLE DISABLE
frequencies,should also be used on the main VOLTAGE(V)VOLTAGE(V)LEVEL(V)LEVEL(V)
supply pins.These capacitors may be placed ±15,±500.8 2.0
somewhat farther from the device and may be ±15 2.0 2.8 4.0
shared among several devices in the same area ±15–2.0–1.20of the printed circuit board(PCB).
±5 1.0 1.8 3.0?Careful selection and placement of external ±5–1.0–0.2 1.0components preserve the high-frequency +3015.015.817performance of the THS3125and THS3122.
Resistors should be a very low reactance type.
+10 5.0 5.87.0
Surface-mount resistors work best and allow a
tighter overall layout.Again,keep the leads and Note that if the REF pin is left unterminated,it floats
PCB trace length as short as possible.Never use to the positive rail and falls outside of the
wirebound type resistors in a high-frequency recommended operating range given above V CC–≤
application.Because the output pin and inverting V REF≤(V CC+–4V).As a result,it no longer serves as
input pins are the most sensitive to parasitic a reliable reference for the SHUTDOWN pin,and the
capacitance,always position the feedback and enable/disable thresholds given above no longer
series output resistors,if any,as close as possible apply.If the SHUTDOWN pin is also left
to the inverting input pins and output pins.Other unterminated,it floats to the positive rail and the
network components,such as input termination device is disabled.If balanced,split supplies are used
resistors,should be placed close to the (±V S)and the REF and SHUTDOWN pins are
gain-setting resistors.Even with a low parasitic grounded,the device is enabled.
capacitance that shunts the external resistors,
excessively high resistor values can create
significant time constants that can degrade
performance.Good axial metal-film or
surface-mount resistors have approximately0.2
pF in shunt with the resistor.For resistor values
greater than2.0kΩ,this parasitic capacitance can
add a pole and/or a zero that can affect circuit
operation.Keep resistor values as low as
possible,consistent with load driving
considerations.
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?
Connections to other wideband devices on the ?
Socketing a high-speed device such as the board may be made with short direct traces or THS3125and THS3122is not recommended.The through onboard transmission lines.For short additional lead length and pin-to-pin capacitance connections,consider the trace and the input to introduced by the socket can create an extremely the next device as a lumped capacitive load.troublesome parasitic network which can make it Relatively wide traces [0.05inch (1,3mm)to 0.1almost impossible to achieve a smooth,stable inch (2,54mm)]should be used,preferably with frequency response.Best results are obtained by ground and power planes opened up around soldering the THS3125/THS3122amplifiers them.Estimate the total capacitive load and directly onto the board.
determine if isolation resistors on the outputs are necessary.Low parasitic capacitive loads (less PowerPAD ?Design Considerations
than 4pF)may not need an R S because the The THS3125and THS3122are available in a THS3125and THS3122are nominally thermally-enhanced PowerPAD family of https://www.doczj.com/doc/417745230.html,pensated to operate with a 2-pF parasitic These packages are constructed using a downset load.Higher parasitic capacitive loads without an leadframe upon which the die is mounted [see R S are allowed as the signal gain increases (thus Figure 48(a)and Figure 48(b)].This arrangement increasing the unloaded phase margin).If a long results in the lead frame being exposed as a thermal trace is required,and the 6-dB signal loss intrinsic pad on the underside of the package [see to a doubly-terminated transmission line is Figure 48(c)].Because this thermal pad has direct acceptable,implement a matched-impedance thermal contact with the die,excellent thermal transmission line using microstrip or stripline performance can be achieved by providing a good techniques (consult an ECL design handbook for thermal path away from the thermal pad.Note that microstrip and stripline layout techniques).A 50-Ωdevices such as the THS312x have no electrical environment is not necessary onboard,and in connection between the PowerPAD and the die.
fact,a higher impedance environment improves distortion as shown in the distortion versus load plots.With a characteristic board trace impedance based on board material and trace dimensions,a matching series resistor into the trace from the output of the THS3125/THS3122is used as well as a terminating shunt resistor at the input of the destination device.Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of Figure 48.Views of Thermally-Enhanced Package the destination device:this total effective impedance should be set to match the trace impedance.If the 6-dB attenuation of a The PowerPAD package allows for both assembly doubly-terminated transmission line is and thermal management in one manufacturing unacceptable,a long trace can be operation.During the surface-mount solder operation series-terminated at the source end only.Treat (when the leads are being soldered),the thermal pad the trace as a capacitive load in this case.This can also be soldered to a copper area underneath the configuration does not preserve signal integrity as package.Through the use of thermal paths within this well as a doubly-terminated line.If the input copper area,heat can be conducted away from the impedance of the destination device is low,there package into either a ground plane or other heat is some signal attenuation as a result of the dissipating device.
voltage divider formed by the series output into The PowerPAD package represents a breakthrough the terminating impedance.
in combining the small area and ease of assembly of surface mount with the,heretofore,awkward mechanical methods of heatsinking.
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P= DMax T T
-
max A
q
JA
THS3122
THS3125
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THS3125/THS3122PowerPAD package should
make the connection to the internal ground plane
with a complete connection around the entire
circumference of the plated-through hole.
6.The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its five holes exposed.The bottom-side
solder mask should cover the five holes of the
thermal pad area.This configuration prevents
solder from being pulled away from the thermal
pad area during the reflow process.
7.Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8.With these preparatory steps in place,the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component.This procedure results Dimensions are in inches(millimeters).in a part that is properly installed.
Figure49.DGN PowerPAD PCB Etch and Via
Power Dissipation and Thermal
Pattern
Considerations
Although there are many ways to properly heatsink The THS3125and THS3122incorporate automatic the PowerPAD package,the following steps illustrate thermal shutoff protection.This protection circuitry the recommended approach.shuts down the amplifier if the junction temperature
exceeds approximately+160°C.When the junction 1.PCB with a top side etch pattern as shown in
temperature reduces to approximately+140°C,the Figure49.
amplifier turns on again.However,for maximum 2.Place five holes in the area of the thermal pad.performance and reliability,the designer must take
These holes should be0.01inch(0,254mm)in care to ensure that the design does not exceed a diameter.Keep them small so that solder wicking junction temperature of+125°C.Between+125°C through the holes is not a problem during reflow.and+150°C,damage does not occur,but the 3.Additional vias may be placed anywhere along performance of the amplifier begins to degrade and
the thermal plane outside of the thermal pad long-term reliability suffers.The thermal area.These vias help dissipate the heat characteristics of the device are dictated by the generated by the THS3125/THS3122IC.These package and the PCB.Maximum power dissipation additional vias may be larger than the0.01-inch for a given package can be calculated using the (0,254-mm)diameter vias directly under the following formula.
thermal pad.They can be larger because they
are not in the thermal pad area to be soldered so
that wicking is not a problem.
4.Connect all holes to the internal ground plane.where:
Note that the PowerPAD is electrically isolated?P
DMax is the maximum power dissipation in the
from the silicon and all leads.Connecting the amplifier(W)
PowerPAD to any potential voltage,such as V S–,
?T max is the absolute maximum junction is acceptable as there is no electrical connection temperature(°C)
to the silicon.
?T A is the ambient temperature(°C) 5.When connecting these holes to the ground
θJA=θJC+θCA
plane,do not use the typical web or spoke via
connection methodology.Web connections have where:
a high thermal resistance connection that is?θ
JC is the thermal coefficient from the silicon
useful for slowing the heat transfer during junctions to the case(°C/W)
soldering operations.This resistance makes the?θ
CA is the thermal coefficient from the case to
soldering of vias that have plane connections ambient air(°C/W)
easier.In this application;however,low thermal
resistance is desired for the most efficient heat
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For systems where heat dissipation is more critical,the THS3125and THS3122are also available in an 8-pin MSOP with PowerPAD package that offers even better thermal performance.The thermal coefficient for the PowerPAD packages are substantially improved over the traditional SOIC.Maximum power dissipation levels are depicted in Figure 50for the available packages.The data for the PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines discussed above and detailed in the PowerPAD application note (literature number SLMA002).Figure 50also illustrates the effect of not soldering the PowerPAD to a PCB.The thermal impedance increases substantially,which may cause serious heat and performance issues.Always solder the PowerPAD to Results shown are with no air flow and PCB size of 3in ×3in the PCB for optimum performance.
(76,2mm ×76,2mm).When determining whether or not the device satisfies ?θJA =58.4°C/W for 8-pin MSOP with PowerPAD (DGN the maximum power dissipation requirement,it is package)
important to not only consider quiescent power ?θJA =95°C/W for 8-pin SOIC High-K test PCB (D package)dissipation,but also dynamic power dissipation.Often ?
θJA =158°C/W for 8-pin MSOP with PowerPAD without solder
times,this type of dissipation is difficult to quantify Figure 50.Maximum Power Dissipation vs
because the signal pattern is inconsistent,but an Ambient Temperature
estimate of the RMS power dissipation can provide visibility into a possible problem.
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REVISION HISTORY
NOTE:Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C(July,2010)to Revision D Page ?Changed output current(absolute maximum)from275mA to550mA (2)
Changes from Revision B(October,2009)to Revision C Page ?Corrected REF pin name for THS3125shown in front-page figure (1)
?Deleted Shutdown pin input levels parameters and specifications from Recommended Operating Conditions table (3)
?Updated Shutdown Characteristics table test conditions;changed GND to REF,corrected V SHDN notations (5)
?Added V REF and V SHDN parameters and speciifications to Shutdown Characteristics table (5)
?Revised second and fourth paragraphs of Saving Power with Shutdown Functionality section (14)
?Updated equation in Power-Down Reference Pin Operation section that describes usable range at the REF pin (15)
?Revised paragraph in Power-Down Reference Pin Operation that discusses behavior of unterminated REF pin (15)
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
Samples (Requires Login)
THS3122CD ACTIVE SOIC D 875Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM THS3122CDDA ACTIVE SO PowerPAD DDA 875Green (RoHS & no Sb/Br)CU SN Level-1-260C-UNLIM THS3122CDDAG3ACTIVE SO PowerPAD
DDA 875Green (RoHS & no Sb/Br)CU SN
Level-1-260C-UNLIM
THS3122CDG4ACTIVE SOIC D 875Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM THS3122CDR ACTIVE SOIC D 82500Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM THS3122CDRG4ACTIVE SOIC D 82500Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM THS3122ID ACTIVE SOIC D 875Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM THS3122IDDA ACTIVE SO PowerPAD DDA 875Green (RoHS & no Sb/Br)CU SN Level-1-260C-UNLIM THS3122IDDAG3ACTIVE SO PowerPAD
DDA 875Green (RoHS & no Sb/Br)CU SN
Level-1-260C-UNLIM
THS3122IDG4ACTIVE SOIC D 875Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM THS3125CPWP ACTIVE HTSSOP PWP 1490Green (RoHS & no Sb/Br)CU NIPDAU Level-2-260C-1 YEAR THS3125CPWPG4
ACTIVE HTSSOP PWP 1490Green (RoHS & no Sb/Br)CU NIPDAU Level-2-260C-1 YEAR THS3125ID ACTIVE SOIC D 1450Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM THS3125IDG4ACTIVE SOIC D 1450Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM THS3125IPWP ACTIVE HTSSOP PWP 1490Green (RoHS & no Sb/Br)CU NIPDAU Level-2-260C-1 YEAR THS3125IPWPG4ACTIVE HTSSOP PWP 1490Green (RoHS & no Sb/Br)CU NIPDAU Level-2-260C-1 YEAR THS3125IPWPR
ACTIVE
HTSSOP
PWP
14
2000
Green (RoHS & no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
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