TMS320F2809,TMS320F2808,TMS320F2806 TMS320F2802,TMS320F2801,TMS320C2802 TMS320C2801,TMS320F28016,TMS320F28015 Digital Signal Processors
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty.Production processing does not
necessarily include testing of all parameters.
Literature Number:SPRS230N
October2003–Revised May2012
TMS320F2809,TMS320F2808,TMS320F2806
TMS320F2802,TMS320F2801,TMS320C2802
TMS320C2801,TMS320F28016,TMS320F28015
https://www.doczj.com/doc/318356689.html, SPRS230N–OCTOBER2003–REVISED MAY2012
Contents
1F280x,F2801x,C280x DSPs (8)
1.1Features (8)
1.2Getting Started (9)
2Introduction (10)
2.1Pin Assignments (13)
2.2Signal Descriptions (18)
3Functional Overview (24)
3.1Memory Maps (25)
3.2Brief Descriptions (33)
3.2.1C28x CPU (33)
3.2.2Memory Bus(Harvard Bus Architecture) (33)
3.2.3Peripheral Bus (33)
3.2.4Real-Time JTAG and Analysis (34)
3.2.5Flash (34)
3.2.6ROM (34)
3.2.7M0,M1SARAMs (34)
3.2.8L0,L1,H0SARAMs (35)
3.2.9Boot ROM (35)
3.2.10Security (36)
3.2.11Peripheral Interrupt Expansion(PIE)Block (37)
3.2.12External Interrupts(XINT1,XINT2,XNMI) (37)
3.2.13Oscillator and PLL (37)
3.2.14Watchdog (37)
3.2.15Peripheral Clocking (37)
3.2.16Low-Power Modes (37)
3.2.17Peripheral Frames0,1,2(PFn) (38)
3.2.18General-Purpose Input/Output(GPIO)Multiplexer (38)
3.2.1932-Bit CPU-Timers(0,1,2) (38)
3.2.20Control Peripherals (38)
3.2.21Serial Port Peripherals (39)
3.3Register Map (39)
3.4Device Emulation Registers (41)
3.5Interrupts (41)
3.5.1External Interrupts (44)
3.6System Control (45)
3.6.1OSC and PLL Block (46)
3.6.1.1External Reference Oscillator Clock Option (47)
3.6.1.2PLL-Based Clock Module (48)
3.6.1.3Loss of Input Clock (49)
3.6.2Watchdog Block (50)
3.7Low-Power Modes Block (51)
4Peripherals (52)
4.132-Bit CPU-Timers0/1/2 (52)
4.2Enhanced PWM Modules(ePWM1/2/3/4/5/6) (54)
4.3Hi-Resolution PWM(HRPWM) (57)
4.4Enhanced CAP Modules(eCAP1/2/3/4) (57)
4.5Enhanced QEP Modules(eQEP1/2) (60)
4.6Enhanced Analog-to-Digital Converter(ADC)Module (62)
4.6.1ADC Connections if the ADC Is Not Used (65)
4.6.2ADC Registers (66)
4.7Enhanced Controller Area Network(eCAN)Modules(eCAN-A and eCAN-B) (67)
TMS320F2809,TMS320F2808,TMS320F2806
TMS320F2802,TMS320F2801,TMS320C2802
TMS320C2801,TMS320F28016,TMS320F28015 https://www.doczj.com/doc/318356689.html, SPRS230N–OCTOBER2003–REVISED MAY2012
4.8Serial Communications Interface(SCI)Modules(SCI-A,SCI-B) (72)
4.9Serial Peripheral Interface(SPI)Modules(SPI-A,SPI-B,SPI-C,SPI-D) (75)
4.10Inter-Integrated Circuit(I2C) (79)
4.11GPIO MUX (81)
5Device Support (85)
5.1Device and Development Support Tool Nomenclature (85)
5.2Documentation Support (87)
5.3Community Resources (92)
6Electrical Specifications (93)
6.1Absolute Maximum Ratings (93)
6.2Recommended Operating Conditions (94)
6.3Electrical Characteristics (94)
6.4Current Consumption (95)
6.4.1Reducing Current Consumption (99)
6.4.2Current Consumption Graphs (100)
6.5Emulator Connection Without Signal Buffering for the DSP (102)
6.6Timing Parameter Symbology (103)
6.6.1General Notes on Timing Parameters (103)
6.6.2Test Load Circuit (103)
6.6.3Device Clock Table (104)
6.7Clock Requirements and Characteristics (105)
6.8Power Sequencing (106)
6.8.1Power Management and Supervisory Circuit Solutions (106)
6.9General-Purpose Input/Output(GPIO) (109)
6.9.1GPIO-Output Timing (109)
6.9.2GPIO-Input Timing (110)
6.9.3Sampling Window Width for Input Signals (111)
6.9.4Low-Power Mode Wakeup Timing (112)
6.10Enhanced Control Peripherals (115)
6.10.1Enhanced Pulse Width Modulator(ePWM)Timing (115)
6.10.2Trip-Zone Input Timing (115)
6.10.3External Interrupt Timing (117)
6.10.4I2C Electrical Specification and Timing (118)
6.10.5Serial Peripheral Interface(SPI)Master Mode Timing (118)
6.10.6SPI Slave Mode Timing (123)
6.10.7On-Chip Analog-to-Digital Converter (125)
6.10.7.1ADC Power-Up Control Bit Timing (126)
6.10.7.2Definitions (127)
6.10.7.3Sequential Sampling Mode(Single-Channel)(SMODE=0) (128)
6.10.7.4Simultaneous Sampling Mode(Dual-Channel)(SMODE=1) (129)
6.11Detailed Descriptions (130)
6.12Flash Timing (131)
6.13ROM Timing(C280x only) (133)
7Migrating From F280x Devices to C280x Devices (134)
7.1Migration Issues (134)
8Revision History (135)
9Mechanical Data (136)
TMS320F2809,TMS320F2808,TMS320F2806
TMS320F2802,TMS320F2801,TMS320C2802
TMS320C2801,TMS320F28016,TMS320F28015
SPRS230N–OCTOBER2003–REVISED https://www.doczj.com/doc/318356689.html,
List of Figures
2-1TMS320F2809,TMS320F2808100-Pin PZ LQFP(Top View) (14)
2-2TMS320F2806100-Pin PZ LQFP(Top View) (15)
2-3TMS320F2802,TMS320F2801,TMS320C2802,TMS320C2801100-Pin PZ LQFP(Top View) (16)
2-4TMS320F2801x100-Pin PZ LQFP(Top View) (17)
2-5TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801,
TMS320F28016,TMS320F28015,TMS320C2802,TMS320C2801
100-Ball GGM and ZGM MicroStar BGA?(Bottom View) (17)
3-1Functional Block Diagram (25)
3-2F2809Memory Map (26)
3-3F2808Memory Map (27)
3-4F2806Memory Map (28)
3-5F2802,C2802Memory Map (29)
3-6F2801,F28015,F28016,C2801Memory Map (29)
3-7External and PIE Interrupt Sources (43)
3-8Multiplexing of Interrupts Using the PIE Block (43)
3-9Clock and Reset Domains (45)
3-10OSC and PLL Block Diagram (46)
3-11Using a3.3-V External Oscillator (47)
3-12Using a1.8-V External Oscillator (47)
3-13Using the Internal Oscillator (47)
3-14Watchdog Module (50)
4-1CPU-Timers (52)
4-2CPU-Timer Interrupt Signals and Output Signal (53)
4-3Multiple PWM Modules in a280x System (54)
4-4ePWM Sub-Modules Showing Critical Internal Signal Interconnections (56)
4-5eCAP Functional Block Diagram (58)
4-6eQEP Functional Block Diagram (60)
4-7Block Diagram of the ADC Module (63)
4-8ADC Pin Connections With Internal Reference (64)
4-9ADC Pin Connections With External Reference (65)
4-10eCAN Block Diagram and Interface Circuit (68)
4-11eCAN-A Memory Map (69)
4-12eCAN-B Memory Map (70)
4-13Serial Communications Interface(SCI)Module Block Diagram (74)
4-14SPI Module Block Diagram(Slave Mode) (78)
4-15I2C Peripheral Module Interfaces (80)
4-16GPIO MUX Block Diagram (81)
4-17Qualification Using Sampling Window (84)
5-1Example of TMS320x280x/2801x Device Nomenclature (86)
6-1Typical Operational Current Versus Frequency(F2808) (100)
6-2Typical Operational Power Versus Frequency(F2808) (100)
6-3Typical Operational Current Versus Frequency(C280x) (101)
6-4Typical Operational Power Versus Frequency(C280x) (101)
6-5Emulator Connection Without Signal Buffering for the DSP (102)
6-6 3.3-V Test Load Circuit (103)
6-7Clock Timing (106)
6-8Power-on Reset (107)
TMS320F2809,TMS320F2808,TMS320F2806
TMS320F2802,TMS320F2801,TMS320C2802
TMS320C2801,TMS320F28016,TMS320F28015 https://www.doczj.com/doc/318356689.html, SPRS230N–OCTOBER2003–REVISED MAY2012 6-9Warm Reset (108)
6-10Example of Effect of Writing Into PLLCR Register (109)
6-11General-Purpose Output Timing (110)
6-12Sampling Mode (110)
6-13General-Purpose Input Timing (111)
6-14IDLE Entry and Exit Timing (112)
6-15STANDBY Entry and Exit Timing Diagram (113)
6-16HALT Wake-Up Using GPIOn (114)
6-17PWM Hi-Z Characteristics (115)
6-18ADCSOCAO or ADCSOCBO Timing (117)
6-19External Interrupt Timing (117)
6-20SPI Master Mode External Timing(Clock Phase=0) (120)
6-21SPI Master Mode External Timing(Clock Phase=1) (122)
6-22SPI Slave Mode External Timing(Clock Phase=0) (124)
6-23SPI Slave Mode External Timing(Clock Phase=1) (125)
6-24ADC Power-Up Control Bit Timing (126)
6-25ADC Analog Input Impedance Model (127)
6-26Sequential Sampling Mode(Single-Channel)Timing (128)
6-27Simultaneous Sampling Mode Timing (129)
TMS320F2809,TMS320F2808,TMS320F2806
TMS320F2802,TMS320F2801,TMS320C2802
TMS320C2801,TMS320F28016,TMS320F28015
SPRS230N–OCTOBER2003–REVISED https://www.doczj.com/doc/318356689.html,
List of Tables
2-1Hardware Features(100-MHz Devices) (11)
2-2Hardware Features(60-MHz Devices) (12)
2-3Signal Descriptions (18)
3-1Addresses of Flash Sectors in F2809 (30)
3-2Addresses of Flash Sectors in F2808 (30)
3-3Addresses of Flash Sectors in F2806,F2802 (30)
3-4Addresses of Flash Sectors in F2801,F28015,F28016 (31)
3-5Impact of Using the Code Security Module (31)
3-6Wait-states (32)
3-7Boot Mode Selection (35)
3-8Peripheral Frame0Registers (40)
3-9Peripheral Frame1Registers (40)
3-10Peripheral Frame2Registers (41)
3-11Device Emulation Registers (41)
3-12PIE Peripheral Interrupts (43)
3-13PIE Configuration and Control Registers (44)
3-14External Interrupt Registers (44)
3-15PLL,Clocking,Watchdog,and Low-Power Mode Registers (46)
3-16PLLCR Register Bit Definitions (48)
3-17Possible PLL Configuration Modes (49)
3-18Low-Power Modes (51)
4-1CPU-Timers0,1,2Configuration and Control Registers (53)
4-2ePWM Control and Status Registers (55)
4-3eCAP Control and Status Registers (59)
4-4eQEP Control and Status Registers (61)
4-5ADC Registers (66)
4-6 3.3-V eCAN Transceivers (68)
4-7CAN Register Map (71)
4-8SCI-A Registers (73)
4-9SCI-B Registers (73)
4-10SPI-A Registers (76)
4-11SPI-B Registers (76)
4-12SPI-C Registers (77)
4-13SPI-D Registers (77)
4-14I2C-A Registers (80)
4-15GPIO Registers (82)
4-16F2808GPIO MUX Table (83)
5-1TMS320x280x,2801x Peripheral Selection Guide (87)
6-1TMS320F2809,TMS320F2808Current Consumption by Power-Supply Pins at100-MHz SYSCLKOUT (95)
6-2TMS320F2806Current Consumption by Power-Supply Pins at100-MHz SYSCLKOUT (96)
6-3TMS320F2802,TMS320F2801Current Consumption by Power-Supply Pins at100-MHz SYSCLKOUT (97)
6-4TMS320C2802,TMS320C2801Current Consumption by Power-Supply Pins at100-MHz SYSCLKOUT (98)
6-5Typical Current Consumption by Various Peripherals(at100MHz) (99)
6-6TMS320x280x Clock Table and Nomenclature(100-MHz Devices) (104)
6-7TMS320x280x/2801x Clock Table and Nomenclature(60-MHz Devices) (104)
6-8Input Clock Frequency (105)
6-9XCLKIN Timing Requirements-PLL Enabled (105)
TMS320F2809,TMS320F2808,TMS320F2806
TMS320F2802,TMS320F2801,TMS320C2802
TMS320C2801,TMS320F28016,TMS320F28015 https://www.doczj.com/doc/318356689.html, SPRS230N–OCTOBER2003–REVISED MAY2012 6-10XCLKIN Timing Requirements-PLL Disabled (105)
6-11XCLKOUT Switching Characteristics(PLL Bypassed or Enabled) (105)
6-12Power Management and Supervisory Circuit Solutions (106)
6-13Reset Timing Requirements (108)
6-14General-Purpose Output Switching Characteristics (109)
6-15General-Purpose Input Timing Requirements (110)
6-16IDLE Mode Timing Requirements (112)
6-17IDLE Mode Switching Characteristics (112)
6-18STANDBY Mode Timing Requirements (113)
6-19STANDBY Mode Switching Characteristics (113)
6-20HALT Mode Timing Requirements (114)
6-21HALT Mode Switching Characteristics (114)
6-22ePWM Timing Requirements (115)
6-23ePWM Switching Characteristics (115)
6-24Trip-Zone input Timing Requirements (115)
6-25High-Resolution PWM Characteristics at SYSCLKOUT=60–100MHz (116)
6-26Enhanced Capture(eCAP)Timing Requirement (116)
6-27eCAP Switching Characteristics (116)
6-28Enhanced Quadrature Encoder Pulse(eQEP)Timing Requirements (116)
6-29eQEP Switching Characteristics (116)
6-30External ADC Start-of-Conversion Switching Characteristics (117)
6-31External Interrupt Timing Requirements (117)
6-32External Interrupt Switching Characteristics (117)
6-33I2C Timing (118)
6-34SPI Master Mode External Timing(Clock Phase=0) (119)
6-35SPI Master Mode External Timing(Clock Phase=1) (121)
6-36SPI Slave Mode External Timing(Clock Phase=0) (123)
6-37SPI Slave Mode External Timing(Clock Phase=1) (124)
6-38ADC Electrical Characteristics(over recommended operating conditions) (125)
6-39ADC Power-Up Delays (126)
6-40Current Consumption for Different ADC Configurations(at12.5-MHz ADCCLK) (126)
6-41Sequential Sampling Mode Timing (128)
6-42Simultaneous Sampling Mode Timing (129)
6-43Flash Endurance for A and S Temperature Material (131)
6-44Flash Endurance for Q Temperature Material (131)
6-45Flash Parameters at100-MHz SYSCLKOUT (131)
6-46Flash/OTP Access Timing (132)
6-47Minimum Required Flash/OTP Wait-States at Different Frequencies (132)
6-48ROM/OTP Access Timing (133)
6-49ROM/ROM(OTP area)Minimum Required Wait-States at Different Frequencies (133)
9-1F280x Thermal Model100-pin GGM Results (136)
9-2F280x Thermal Model100-pin PZ Results (136)
9-3C280x Thermal Model100-pin GGM Results (136)
9-4C280x Thermal Model100-pin PZ Results (136)
9-5F2809Thermal Model100-pin GGM Results (136)
9-6F2809Thermal Model100-pin PZ Results (137)
TMS320F2809,TMS320F2808,TMS320F2806
TMS320F2802,TMS320F2801,TMS320C2802
TMS320C2801,TMS320F28016,TMS320F28015
SPRS230N–OCTOBER2003–REVISED https://www.doczj.com/doc/318356689.html,
Digital Signal Processors
Check for Samples:TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801,TMS320C2802,
TMS320C2801,TMS320F28016,TMS320F28015
1F280x,F2801x,C280x DSPs
1.1Features
?High-Performance Static CMOS Technology?128-Bit Security Key/Lock –100MHz(10-ns Cycle Time)–Protects Flash/OTP/L0/L1Blocks
–60MHz(16.67-ns Cycle Time)–Prevents Firmware Reverse Engineering –Low-Power(1.8-V Core,3.3-V I/O)Design?Three32-Bit CPU Timers
?JTAG Boundary Scan Support(1)?Enhanced Control Peripherals
?High-Performance32-Bit CPU(TMS320C28x?)–Up to16PWM Outputs –16x16and32x32MAC Operations–Up to6HRPWM Outputs With150-ps MEP
Resolution
–16x16Dual MAC
–Up to Four Capture Inputs –Harvard Bus Architecture
–Up to Two Quadrature Encoder Interfaces –Atomic Operations
–Up to Six32-bit/Six16-bit Timers –Fast Interrupt Response and Processing
?Serial Port Peripherals
–Unified Memory Programming Model
–Up to4SPI Modules
–Code-Efficient(in C/C++and Assembly)
–Up to2SCI(UART)Modules
?On-Chip Memory
–Up to2CAN Modules –F2809:128K x16Flash,18K x16SARAM
F2808:64K x16Flash,18K x16SARAM–One Inter-Integrated-Circuit(I2C)Bus
F2806:32K x16Flash,10K x16SARAM?12-Bit ADC,16Channels
F2802:32K x16Flash,6K x16SARAM–2x8Channel Input Multiplexer
F2801:16K x16Flash,6K x16SARAM
–Two Sample-and-Hold
F2801x:16K x16Flash,6K x16SARAM
–Single/Simultaneous Conversions –1K x16OTP ROM(Flash Devices Only)
–Fast Conversion Rate:–C2802:32K x16ROM,6K x16SARAM
80ns-12.5MSPS(F2809only) C2801:16K x16ROM,6K x16SARAM
160ns-6.25MSPS(280x)
?Boot ROM(4K x16)267ns-3.75MSPS(F2801x)–With Software Boot Modes(via SCI,SPI,–Internal or External Reference
CAN,I2C,and Parallel I/O)
?Up to35Individually Programmable,–Standard Math Tables Multiplexed GPIO Pins With Input Filtering ?Clock and System Control?Advanced Emulation Features –Dynamic PLL Ratio Changes Supported–Analysis and Breakpoint Functions
–On-Chip Oscillator–Real-Time Debug via Hardware
–Watchdog Timer Module?Development Support Includes
?Any GPIO A Pin Can Be Connected to One of–ANSI C/C++Compiler/Assembler/Linker
the Three External Core Interrupts
–Code Composer Studio?IDE
?Peripheral Interrupt Expansion(PIE)Block That
–DSP/BIOS?
Supports All43Peripheral Interrupts
–Digital Motor Control and Digital Power ?Endianness:Little Endian
Software Libraries
?Low-Power Modes and Power Savings
–IDLE,STANDBY,HALT Modes Supported
–Disable Individual Peripheral Clocks
(1)IEEE Standard1149.1-1990Standard Test Access Port and
Scan Architecture
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio,DSP/BIOS,MicroStar BGA,C28x,TI,TMS320C2000are trademarks of Texas
Instruments.
eZdsp is a trademark of Spectrum Digital.
All other trademarks are the property of their respective owners.
TMS320F2809,TMS320F2808,TMS320F2806
TMS320F2802,TMS320F2801,TMS320C2802
TMS320C2801,TMS320F28016,TMS320F28015 https://www.doczj.com/doc/318356689.html, SPRS230N–OCTOBER2003–REVISED MAY2012?Package Options?Temperature Options
–Thin Quad Flatpack(PZ)–A:–40°C to85°C(PZ,GGM,ZGM)
–MicroStar BGA?(GGM,ZGM)–S:–40°C to125°C(PZ,GGM,ZGM)
–Q:–40°C to125°C(PZ)
1.2Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x?device.For more detail on each of these steps,see the following:
?Getting Started With TMS320C28x Digital Signal Controllers(literature number SPRAAM0).
?C2000Getting Started Website(https://www.doczj.com/doc/318356689.html,/c2000getstarted)
Step1.Acquire the appropriate development tools
The quickest way to begin working with a C28x device is to acquire an eZdsp?kit for initial
development,which,in one package,includes:
?On-board JTAG emulation via USB or parallel port
?Appropriate emulation driver
?Code Composer Studio?IDE for eZdsp
Once you have become familiar with the device and begin developing on your own
hardware,purchase Code Composer Studio?IDE separately for software development and
a JTAG emulation tool to get started on your project.
Step2.Download starter software
To simplify programming for C28x devices,it is recommended that users download and use
the C/C++Header Files and Example(s)to begin developing software for the C28x devices
and their various peripherals.
After downloading the appropriate header file package for your device,refer to the following
resources for step-by-step instructions on how to run the peripheral examples and use the
header file structure for your own software
?The Quick Start Readme in the/doc directory to run your first application.
?Programming TMS320x28xx and28xxx Peripherals in C/C++Application Report (literature number SPRAA85)
Step3.Download flash programming software
Many C28x devices include on-chip flash memory and tools that allow you to program the
flash with your software IP.
?Flash Tools:C28x Flash Tools
?TMS320F281x?Flash Programming Solutions(literature number SPRB169)
?Running an Application from Internal Flash Memory on the TMS320F28xxx DSP (literature number SPRA958)
Step4.Move on to more advanced topics
For more application software and other advanced topics,visit the TI?website at
https://www.doczj.com/doc/318356689.html, or https://www.doczj.com/doc/318356689.html,/c2000getstarted.
Copyright?2003–2012,Texas Instruments Incorporated F280x,F2801x,C280x DSPs9
TMS320F2809,TMS320F2808,TMS320F2806
TMS320F2802,TMS320F2801,TMS320C2802
TMS320C2801,TMS320F28016,TMS320F28015
SPRS230N–OCTOBER2003–REVISED https://www.doczj.com/doc/318356689.html, 2Introduction
The TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801,TMS320F28015, TMS320F28016,TMS320C2802,and TMS320C2801devices,members of the TMS320C28x?DSP generation,are highly integrated,high-performance solutions for demanding control applications.
Throughout this document,TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802, TMS320F2801,TMS320C2802,TMS320C2801,TMS320F28015,and TMS320F28016are abbreviated as F2809,F2808,F2806,F2802,F2801,C2802,C2801,F28015,and F28016,respectively.TMS320F28015 and TMS320F28016are abbreviated as F2801x.Table2-1provides a summary of features for each device.
10Introduction Copyright?2003–2012,Texas Instruments Incorporated
GPIO0/EPWM1A V DD2A18V SS2AGND V DDAIO
GPIO13//CANRXB/SPISOMIB
TZ2V DD V DDIO
V SS V SS
T C K
G P I O 12//C A N T X B /S P I S I M O B T Z 1G P I O 14/S C I T X D B /S P I C L K B
T Z 3G P I O 15/S C I R X D B /S P I S T E B T Z 4G P I O 30/C A N R X A
A D C I N A 3
A D C I N A 7
A D C I N A 6
A D C I N A 5
A D C I N A 4
A D C I N A 2
A D C I N A 1
A D C I N A 0
A D C L O G P I O 31/C A N T X A
G P I O 29/S C I T X D A //T Z 6
G P I O 33/S C L A /E P W M S Y N C O A D C S O C B O G P I O 4/E P W M 3A G P I O 17/S P I S O M I A /C A N R X B T Z 6G P I O 5/E P W M 3B /S P I C L K D /E C A P 1G P I O 18/S P I C L K A /S C I T X D B
G P I O 6/E P W M 4A /E P W M S Y N C I /E P W M S Y N C O G P I O 19/S P I S T E A /S C I R X D B
G P I O 7/E P W M 4B /S P I S T E D /E C A P 2
G P I O 9/E P W M 5B /S C I T X D B /E C A P 3
G P I O 20/E Q E P 1A /S P I S I M O C /C A N T X B G P I O 10/E P W M 6A /C A N R X B /A D C S O C B O G P I O 8/E P W M 5A /C A N T X B /A D C S O C A O X C L K O U T G P I O 21/E Q E P 1B /S P I S O M I C /C A N R X B
V S S
V S S
V S S
V S S
V S S
V S S 1A G N D
V S S A 2
V S S A I O
V D D
V D D A 2
V D D 1A 18
V D D I O
V D D
V D D
V D D I O
G P I O 11/E P W M 6B /S C I R X D B /E C A P 4G P I O 22/E Q E P 1S /S P I C L K C /S C I T X D B
T M S
T D I G P I O 23/E Q E P 1I /S P I S T E C /S C I R X D B
ADCINB0ADCINB1ADCINB2ADCINB3ADCINB7ADCINB6ADCINB5ADCINB4ADCREFIN ADCREFM ADCREFP ADCRESEXT GPIO34GPIO1/EPWM1B/SPISIMOD GPIO2/EPWM2A
GPIO3/EPWM2B/SPISOMID GPIO16/SPISIMOA/CANTXB/TZ5TMS320F2809,TMS320F2808,TMS320F2806TMS320F2802,TMS320F2801,TMS320C2802TMS320C2801,TMS320F28016,TMS320F28015
https://www.doczj.com/doc/318356689.html,
SPRS230N –OCTOBER 2003–REVISED MAY 2012
2.1Pin Assignments
The TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801,TMS320C2802,TMS320C2801,TMS320F28015,and TMS320F28016100-pin PZ low-profile quad flatpack (LQFP)pin assignments are shown in Figure 2-1,Figure 2-2,Figure 2-3,and Figure 2-4.The 100-ball GGM and ZGM ball grid array (BGA)terminal assignments are shown in Figure 2-5.Table 2-3describes the function(s)of each pin.
Figure 2-1.TMS320F2809,TMS320F2808100-Pin PZ LQFP (Top View)
50494847464544434241403938373635343332313029282726
76
75
74
5153
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
52
7778798081828384858687888990919293949596979899100
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
222324
251
GPIO0/EPWM1A XRS
TRST V DD2A18V SS2AGND V DDAIO
GPIO13//SPISOMIB
TZ2V DD3VFL
V DD V DD V DDIO
V DD
V SS
V SS V SS V SS
V SS
V SS
V DDIO
GPIO26/ECAP3/EQEP2I/SPICLKB
TEST2
TEST1
GPIO25/ECAP2/EQEP2B/SPISOMIB
XCLKIN
X1X2EMU1EMU0GPIO24/ECAP1/EQEP2A/SPISIMOB
GPIO27/ECAP4/EQEP2S/SPISTEB
TDO T C K
G P I O 12/S P I S I M O B T Z 1G P I O 14//S C I T X D B /S P I C L K B
T Z 3G P I O 15//S C I R X D B /S P I S T E B T Z 4G P I O 30/C A N R X A
A D C I N A 3
A D C I N A 7
A D C I N A 6
A D C I N A 5
A D C I N A 4
A D C I N A 2
A D C I N A 1
A D C I N A 0
A D C L O G P I O 31/C A N T X A
G P I O 29/S C I T X D A /T Z 6
G P I O 33/S C L A /E P W M S Y N C O /A D C S O C B O G P I O 4/E P W M 3A G P I O 17/S P I S O M I A /T Z 6G P I O 5/E P W M 3B /S P I C L K D /E C A P 1G P I O 18/S P I C L K A /S C I T X D B
G P I O 6/E P W M 4A /E P W M S Y N C I /E P W M S Y N C O G P I O 19/S P I S T E A /S C I R X D B
G P I O 7/E P W M 4B /S P I S T E D /E C A P 2
G P I O 9/E P W M 5B /S C I T X D B /E C A P 3
G P I O 20/E Q E P 1A /S P I S I M O C G P I O 10/E P W M 6A A D C S O C B O G P I O 8/E P W M 5A A D C S O C A O X C L K O U T G P I O 21/E Q E P 1B /S P I S O M I C
V S S
V S S
V S S
V S S
V S S
V S S 1A G N D
V S S A 2
V S S A I O
V D D
V D D A 2
V D D 1A 18
V D D I O
V D D
V D D
V D D I O
G P I O 11/E P W M 6B /S C I R X D B /E C A P 4G P I O 22/E Q E P 1S /S P I C L K C /S C I T X D B
T M S
T D I G P I O 23/E Q E P 1I /S P I S T E C /S C I R X D B
ADCINB0ADCINB1ADCINB2ADCINB3ADCINB7ADCINB6ADCINB5ADCINB4ADCREFIN ADCREFM ADCREFP ADCRESEXT GPIO34GPIO1/EPWM1B/SPISIMOD GPIO2/EPWM2A
GPIO3/EPWM2B/SPISOMID GPIO16/SPISIMOA/TZ5GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO28/SCIRXDA/TZ5
TMS320F2809,TMS320F2808,TMS320F2806TMS320F2802,TMS320F2801,TMS320C2802TMS320C2801,TMS320F28016,TMS320F28015
SPRS230N –OCTOBER 2003–REVISED MAY 2012
https://www.doczj.com/doc/318356689.html,
Figure 2-2.TMS320F2806100-Pin PZ LQFP (Top View)
50494847464544434241403938373635343332313029282726
76
75
74
5153
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
52
7778798081828384858687888990919293949596979899100
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
222324
251
GPIO0/EPWM1A XRS
TRST V DD2A18V SS2AGND V DDAIO
SPISOMIB/GPIO13/TZ2
V DD3VFL
(A)
V DD V DD V DDIO
V DD
V SS
V SS V SS V SS
V SS
V SS
V DDIO
SPICLKB/GPIO26
TEST2
TEST1
GPIO25/ECAP2/SPISOMIB
XCLKIN
X1X2EMU1EMU0SPISIMOB/GPIO24/ECAP1
SPISTEB/GPIO27
TDO T C K
S P I S I M O B /G P I O 12T Z 1S P I C L K B /G P I O 14T Z 3
S P I S T E B /G P I O 15T Z 4G P I O 30/C A N R X A
A D C I N A 3
A D C I N A 7
A D C I N A 6
A D C I N A 5
A D C I N A 4
A D C I N A 2
A D C I N A 1
A D C I N A 0
A D C L O G P I O 31/C A N T X A
G P I O 29/S C I T X D A /T Z 6
G P I O 33/S C L A /E P W M S Y N C O /A D C S O C B O G P I O 4/E P W M 3A G P I O 17/S P I S O M I A /T Z 6G P I O 5/E P W M 3B /E C A P 1G P I O 18/S P I C L K A
G P I O 6/E P W M S Y N C I /E P W M S Y N C O G P I O 19/S P I S T E A
G P I O 7/E C A P 2
G P I O 9
G P I O 20/E Q E P 1A G P I O 10A D C S O C B O G P I O 8A D C S O C A O X C L K O U T G P I O 21/E Q E P 1B
V S S
V S S
V S S
V S S
V S S
V S S 1A G N D
V S S A 2
V S S A I O
V D D
V D D A 2
V D D 1A 18
V D D I O
V D D
V D D
V D D I O
G P I O 11G P I O 22/E Q E P 1S
T M S
T D I G P I O 23/E Q E P 1I
ADCINB0ADCINB1ADCINB2ADCINB3ADCINB7ADCINB6ADCINB5ADCINB4ADCREFIN ADCREFM ADCREFP ADCRESEXT GPIO34GPIO1/EPWM1B GPIO2/EPWM2A GPIO3/EPWM2B GPIO16/SPISIMOA/TZ5GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO28/SCIRXDA/TZ5
TMS320F2809,TMS320F2808,TMS320F2806TMS320F2802,TMS320F2801,TMS320C2802TMS320C2801,TMS320F28016,TMS320F28015
https://www.doczj.com/doc/318356689.html,
SPRS230N –OCTOBER 2003–REVISED MAY 2012
A.
On the C280x devices,the V DD3VFL pin is V DDIO .
Figure 2-3.TMS320F2802,TMS320F2801,TMS320C2802,TMS320C2801100-Pin PZ LQFP (Top View)
Copyright ?2003–2012,Texas Instruments Incorporated Introduction 15
50494847464544434241403938373635343332313029282726
76
75
74
5153
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
52
7778798081828384858687888990919293949596979899100
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
222324
251
GPIO0/EPWM1A XRS TRST V DD2A18V SS2AGND V DDAIO
GPIO13/TZ2
V DD3VFL V DD V DD V DDIO
V DD
V SS V SS V SS V SS
V SS
V SS
V DDIO
GPIO26
TEST2TEST1GPIO25/ECAP2
XCLKIN
X1X2EMU1EMU0GPIO24/ECAP1
GPIO27TDO T C K
G P I O 12T Z 1G P I O 14T Z 3
G P I O 15T Z 4G P I O 30/C A N R X A
(A )
A D C I N A 3
A D C I N A 7
A D C I N A 6
A D C I N A 5
A D C I N A 4
A D C I N A 2
A D C I N A 1
A D C I N A 0
A D C L O G P I O 31/C A N T X A (A )
G P I O 29/S C I T X D A /T Z 6
G P I O 33/S C L A /E P W M S Y N C O /A D C S O C B O
G P I O 4/E P W M 3A G P I O 17/S P I S O M I A /T Z 6G P I O 5/E P W M 3B /E C A P 1G P I O 18/S P I C L K A
G P I O 6/E P W M 4A /E P W M S Y N C I /E P W M S Y N C O G P I O 19/S P I S T E A
G P I O 7/E P W M 4B /E C A P 2
G P I O 9
G P I O 20G P I O 10A D C S O C B O G P I O 8A D C S O C A O X C L K O U T G P I O 21
V S S
V S S
V S S
V S S
V S S
V S S 1A G N D
V S S A 2
V S S A I O
V D D
V D D A 2
V D D 1A 18
V D D I O
V D D
V D D
V D D I O
G P I O 11G P I O 22
T M S
T D I G P I O 23
ADCINB0ADCINB1ADCINB2ADCINB3ADCINB7ADCINB6ADCINB5ADCINB4ADCREFIN ADCREFM ADCREFP ADCRESEXT GPIO34GPIO1/EPWM1B GPIO2/EPWM2A GPIO3/EPWM2B GPIO16/SPISIMOA/TZ5GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO28/SCIRXDA/TZ5
TMS320F2809,TMS320F2808,TMS320F2806TMS320F2802,TMS320F2801,TMS320C2802TMS320C2801,TMS320F28016,TMS320F28015
SPRS230N –OCTOBER 2003–REVISED MAY 2012
https://www.doczj.com/doc/318356689.html,
A.CANTXA (pin 7)and CANRXA (pin 6)pins are not applicable for the TMS320F28015.
Figure 2-4.TMS320F2801x 100-Pin PZ LQFP (Top View)
16Introduction
Copyright ?2003–2012,Texas Instruments Incorporated
4C
B A
D
E
213K F G
H
J
5769810
Bottom View
TMS320F2809,TMS320F2808,TMS320F2806TMS320F2802,TMS320F2801,TMS320C2802TMS320C2801,TMS320F28016,TMS320F28015
https://www.doczj.com/doc/318356689.html,
SPRS230N –OCTOBER 2003–REVISED MAY 2012
Figure 2-5.TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801,
TMS320F28016,TMS320F28015,TMS320C2802,TMS320C2801100-Ball GGM and ZGM MicroStar BGA?(Bottom View)
Copyright ?2003–2012,Texas Instruments Incorporated Introduction 17
TMS320F2809,TMS320F2808,TMS320F2806
TMS320F2802,TMS320F2801,TMS320C2802
TMS320C2801,TMS320F28016,TMS320F28015
SPRS230N–OCTOBER2003–REVISED https://www.doczj.com/doc/318356689.html, 2.2Signal Descriptions
Table2-3describes the signals on the280x devices.All digital inputs are TTL-compatible.All outputs are
3.3V with CMOS levels.Inputs are not5-V tolerant.
Table2-3.Signal Descriptions
PIN NO.
GGM/
NAME DESCRIPTION(1)
PZ
ZGM
PIN#
BALL#
JTAG
JTAG test reset with internal pulldown.TRST,when driven high,gives the scan system control of
the operations of the device.If this signal is not connected or driven low,the device operates in its
functional mode,and the test reset signals are ignored.
NOTE:Do not use pullup resistors on TRST;it has an internal pull-down device.TRST is an active TRST84A6high test pin and must be maintained low at all times during normal device operation.An external
pulldown resistor is required on this pin.The value of this resistor should be based on drive strength
of the debugger pods applicable to the design.A2.2-k?resistor generally offers adequate
protection.Since this is application-specific,it is recommended that each target board be validated
for proper operation of the debugger and the application.(I,↓)
TCK75A10JTAG test clock with internal pullup(I,↑)
JTAG test-mode select(TMS)with internal pullup.This serial control input is clocked into the TAP TMS74B10
controller on the rising edge of TCK.(I,↑)
JTAG test data input(TDI)with internal pullup.TDI is clocked into the selected register(instruction TDI73C9
or data)on a rising edge of TCK.(I,↑)
JTAG scan out,test data output(TDO).The contents of the selected register(instruction or data) TDO76B9
are shifted out of TDO on the falling edge of TCK.(O/Z8mA drive)
Emulator pin0.When TRST is driven high,this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan.This pin is also used to put the
device into boundary-scan mode.With the EMU0pin at a logic-high state and the EMU1pin at a
logic-low state,a rising edge on the TRST pin would latch the device into boundary-scan mode. EMU080A8(I/O/Z,8mA drive↑)
NOTE:An external pullup resistor is recommended on this pin.The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design.A2.2-k?to4.7-k?
resistor is generally adequate.Since this is application-specific,it is recommended that each target
board be validated for proper operation of the debugger and the application.
Emulator pin1.When TRST is driven high,this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan.This pin is also used to put the
device into boundary-scan mode.With the EMU0pin at a logic-high state and the EMU1pin at a
logic-low state,a rising edge on the TRST pin would latch the device into boundary-scan mode. EMU181B7(I/O/Z,8mA drive↑)
NOTE:An external pullup resistor is recommended on this pin.The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design.A2.2-k?to4.7-k?
resistor is generally adequate.Since this is application-specific,it is recommended that each target
board be validated for proper operation of the debugger and the application.
FLASH
3.3-V Flash Core Power Pin.This pin should be connected to3.3V at all times.On the ROM
V DD3VFL96C4
parts(C280x),this pin should be connected to V DDIO.
TEST197A3Test Pin.Reserved for TI.Must be left unconnected.(I/O)
TEST298B3Test Pin.Reserved for TI.Must be left unconnected.(I/O)
CLOCK
Output clock derived from SYSCLKOUT.XCLKOUT is either the same frequency,one-half the
frequency,or one-fourth the frequency of SYSCLKOUT.This is controlled by the bits1,0 XCLKOUT66E8(XCLKOUTDIV)in the XCLK register.At reset,XCLKOUT=SYSCLKOUT/4.The XCLKOUT signal
can be turned off by setting XCLKOUTDIV to3.Unlike other GPIO pins,the XCLKOUT pin is not
placed in high-impedance state during a reset.(O/Z,8mA drive).
External Oscillator Input.This pin is used to feed a clock from an external3.3-V oscillator.In this XCLKIN90B5case,tie the X1pin to GND.Alternately,when a crystal/resonator is used(or if an external1.8-V
oscillator is fed into the X1pin),tie the XCLKIN pin to GND.(I)
(1)I=Input,O=Output,Z=High impedance,OD=Open drain,↑=Pullup,↓=Pulldown
18Introduction Copyright?2003–2012,Texas Instruments Incorporated
TMS320F2809,TMS320F2808,TMS320F2806
TMS320F2802,TMS320F2801,TMS320C2802
TMS320C2801,TMS320F28016,TMS320F28015 https://www.doczj.com/doc/318356689.html, SPRS230N–OCTOBER2003–REVISED MAY2012
Table2-3.Signal Descriptions(continued)
PIN NO.
GGM/
NAME DESCRIPTION(1)
PZ
ZGM
PIN#
BALL#
Internal/External Oscillator Input.To use the internal oscillator,a quartz crystal or a ceramic
resonator may be connected across X1and X2.The X1pin is referenced to the1.8-V core digital
X188E6power supply.A1.8-V external oscillator may be connected to the X1pin.In this case,the XCLKIN
pin must be connected to ground.If a3.3-V external oscillator is used with the XCLKIN pin,X1must
be tied to GND.(I)
Internal Oscillator Output.A quartz crystal or a ceramic resonator may be connected across X1and X286C6
X2.If X2is not used it must be left unconnected.(O)
RESET
Device Reset(in)and Watchdog Reset(out).
Device reset.XRS causes the device to terminate execution.The PC will point to the address
contained at the location0x3FFFC0.When XRS is brought to a high level,execution begins at the
location pointed to by the PC.This pin is driven low by the DSP when a watchdog reset occurs.
XRS78B8
During watchdog reset,the XRS pin is driven low for the watchdog reset duration of512OSCCLK
cycles.(I/OD,↑)
The output buffer of this pin is an open-drain with an internal pullup.It is recommended that this pin
be driven by an open-drain device.
ADC SIGNALS
ADCINA716F3ADC Group A,Channel7input(I)
ADCINA617F4ADC Group A,Channel6input(I)
ADCINA518G4ADC Group A,Channel5input(I)
ADCINA419G1ADC Group A,Channel4input(I)
ADCINA320G2ADC Group A,Channel3input(I)
ADCINA221G3ADC Group A,Channel2input(I)
ADCINA122H1ADC Group A,Channel1input(I)
ADCINA023H2ADC Group A,Channel0input(I)
ADCINB734K5ADC Group B,Channel7input(I)
ADCINB633H4ADC Group B,Channel6input(I)
ADCINB532K4ADC Group B,Channel5input(I)
ADCINB431J4ADC Group B,Channel4input(I)
ADCINB330K3ADC Group B,Channel3input(I)
ADCINB229H3ADC Group B,Channel2input(I)
ADCINB128J3ADC Group B,Channel1input(I)
ADCINB027K2ADC Group B,Channel0input(I)
ADCLO24J1Low Reference(connect to analog ground)(I)
ADCRESEXT38F5ADC External Current Bias Resistor.Connect a22-k?resistor to analog ground.
ADCREFIN35J5External reference input(I)
Internal Reference Positive Output.Requires a low ESR(under1.5?)ceramic bypass capacitor of
2.2μF to analog ground.(O)
ADCREFP37G5
NOTE:Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is
used in the system.
Internal Reference Medium Output.Requires a low ESR(under1.5?)ceramic bypass capacitor of
2.2μF to analog ground.(O)
ADCREFM36H5
NOTE:Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is
used in the system.
Copyright?2003–2012,Texas Instruments Incorporated Introduction19
TMS320F2809,TMS320F2808,TMS320F2806
TMS320F2802,TMS320F2801,TMS320C2802
TMS320C2801,TMS320F28016,TMS320F28015
SPRS230N–OCTOBER2003–REVISED https://www.doczj.com/doc/318356689.html,
Table2-3.Signal Descriptions(continued)
PIN NO.
GGM/
NAME DESCRIPTION(1)
PZ
ZGM
PIN#
BALL#
CPU AND I/O POWER PINS
V DDA215F2ADC Analog Power Pin(3.3V)
V SSA214F1ADC Analog Ground Pin
V DDAIO26J2ADC Analog I/O Power Pin(3.3V)
V SSAIO25K1ADC Analog I/O Ground Pin
V DD1A1812E4ADC Analog Power Pin(1.8V)
V SS1AGND13E5ADC Analog Ground Pin
V DD2A1840J6ADC Analog Power Pin(1.8V)
V SS2AGND39K6ADC Analog Ground Pin
V DD10E2
V DD42G6
V DD59F10
CPU and Logic Digital Power Pins(1.8V)
V DD68D7
V DD85B6
V DD93D4
V DDIO3C2
V DDIO46H7
Digital I/O Power Pin(3.3V)
V DDIO65E9
V DDIO82A7
V SS2B1
V SS11E3
V SS41H6
V SS49K9
V SS55H10
V SS62F7Digital Ground Pins
V SS69D10
V SS77A9
V SS87D6
V SS89A5
V SS94A4
GPIOA AND PERIPHERAL SIGNALS(1)(2)
GPIO0General-purpose input/output0(I/O/Z)(3)
EPWM1A Enhanced PWM1Output A and HRPWM channel(O)
47K8
--
--
GPIO1General-purpose input/output1(I/O/Z)(3)
EPWM1B Enhanced PWM1Output B(O)
44K7
SPISIMOD SPI-D slave in,master out(I/O)(not available on2801,2802)
--
GPIO2General-purpose input/output2(I/O/Z)(3)
EPWM2A Enhanced PWM2Output A and HRPWM channel(O)
45J7
--
--
(1)Some peripheral functions may not be available in TMS320F2801x devices.See Table2-2for details.
(2)All GPIO pins are I/O/Z,4-mA drive typical(unless otherwise indicated),and have an internal pullup,which can be selectively
enabled/disabled on a per-pin basis.This feature only applies to the GPIO pins.The GPIO function(shown in Italics)is the default at reset.The peripheral signals that are listed under them are alternate functions.
(3)The pullups on GPIO0-GPIO11pins are not enabled at reset.
20Introduction Copyright?2003–2012,Texas Instruments Incorporated