MOTOROLA
MC68360
QUad Integrated
Communications Controller
User’s Manual
ii MC68360 USER’S MANUAL MOTOROLA
PREFACE
The complete documentation package for the MC68360 consists of the MC68360UM/AD, MC68360 QUad Integrated Communications Controller User’s Manual, M68000PM/AD, MC68000 Family Programmer’s Reference Manual, and the MC68360/D, MC68360 QUad Integrated Communications Controller Product Brief.
The MC68360 QUad Integrated Communications Controller User’s Manual describes the programming, capabilities, registers, and operation of the MC68360 and the MC68EN360; the MC68000 Family Programmer’s Reference Manual provides instruction details for the MC68360; and the MC68360 QUad Integrated Communications Controller Product Brief provides a brief description of the MC68360 capabilities.
This user’s manual is organized as follows:
Section 1Introduction
Section 2Signal Descriptions
Section 3Memory Map
Section 4Bus Operation
Section 5CPU32+
Section 6System Integration Module (SIM60)
Section 7Communication Processor Module (CPM)
Section 8IEEE 1149.1 Test Access Port
Section 9Applications
Section 10Electrical Characteristics
Section 11Ordering Information and Mechanical Data
Appendix A Serial Performance
Appendix B Development Tools and Support
Appendix C RISC Microcode from RAM
Appendix D MC68MH360 Product Brief
MOTOROLA MC68360 USER’S MANUAL iii
iv MC68360 USER’S MANUAL MOTOROLA
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Table of Contents Paragraph Title Page
Number Number
Section 1
Introduction
1.1QUICC Key Features..............................................................................1-1
1.2QUICC Architecture Overview.................................................................1-4
1.2.1CPU32+ Core..........................................................................................1-5
1.2.2System Integration Module (SIM60)........................................................1-5
1.2.3Communications Processor Module (CPM)............................................1-6
1.3Upgrading Designs from the MC6830
2...................................................1-6
1.3.1Architectural Approach............................................................................1-6
1.3.2Hardware Compatibility Issues................................................................1-7
1.3.3Software Compatibility Issues.................................................................1-7
1.4QUICC Glueless System Design.............................................................1-8
1.5QUICC Serial Configurations..................................................................1-9
1.6QUICC Serial Configuration Examples.................................................1-16
1.7QUICC System Bus Configurations......................................................1-17
Section 2
Signal Descriptions
2.1System Bus Signal Index........................................................................2-1
2.1.1Address Bus............................................................................................2-1
2.1.1.1Address Bus (A27–A0)............................................................................2-1
2.1.1.2Address Bus (A31–A28)..........................................................................2-1
2.1.2Function Codes (FC3–FC0)....................................................................2-5
2.1.3Data Bus..................................................................................................2-5
2.1.
3.1Data Bus (D31–D16)...............................................................................2-5
2.1.
3.2Data Bus (D15–D0).................................................................................2-6
2.1.4Parity.......................................................................................................2-6
2.1.4.1Parity (PRTY0)........................................................................................2-6
2.1.4.2Parity (PRTY1)........................................................................................2-6
2.1.4.3Parity (PRTY2)........................................................................................2-6
2.1.4.4Parity (PRTY3)........................................................................................2-6
2.1.5Memory Controller...................................................................................2-6
2.1.5.1Chip Select/Row Address Select (CS6–CS0/RAS6–RAS0)...................2-6
2.1.5.2Chip Select/Row Address Select/Interrupt Acknowledge (CS7/RAS7/IACK7).
2-6
2.1.5.3Column Address Select/Interrupt Acknowledge (CAS3–CAS0/IACK6, 3, 2,
1).2-7
2.1.5.4Address Multiplex (AMUX)......................................................................2-7
2.1.6Interrupt Request Level (IRQ7–IRQ1).....................................................2-7
2.1.7Bus Control Signals.................................................................................2-7
2.1.7.1Data and Size Acknowledge (DSACK1–DSACK0).................................2-8
2.1.7.2Autovector/Interrupt Acknowledge (AVEC/IACK5)..................................2-8
2.1.7.3Address Strobe (AS)...............................................................................2-8
2.1.7.4Data Strobe (DS).....................................................................................2-8
MOTOROLA MC68360 USER’S MANUAL i
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2.1.7.5Transfer Size (SIZ1, SIZ0).......................................................................2-8
2.1.7.6Read/Write (R/W).....................................................................................2-8
2.1.7.7Output Enable/Address Multiplex (OE/AMUX).........................................2-9
2.1.7.8Byte Write Enable (WE3–WE0)...............................................................2-9
2.1.8Bus Arbitration Signals.............................................................................2-9
2.1.8.1Bus Request (BR)....................................................................................2-9
2.1.8.2Bus Grant (BG)........................................................................................2-9
2.1.8.3Bus Grant Acknowledge (BGACK)..........................................................2-9
2.1.8.4Read-Modify-Write Cycle/Initial Configuration (RMC/CONFIG0).............2-9
2.1.8.5Bus Clear Out/Initial Configuration/Row Address Select Double-Drive (BCL-
RO/CONFIG1/RAS2DD).2-9
2.1.9System Control Signals..........................................................................2-10
2.1.9.1Soft Reset (RESETS)............................................................................2-10
2.1.9.2Hard Reset (RESETH)...........................................................................2-10
2.1.9.3Halt (HALT)............................................................................................2-10
2.1.9.4Bus Error (BERR)..................................................................................2-10
2.1.10Clock Signals.........................................................................................2-10
2.1.10.1System Clock Outputs (CLKO2–CLKO1)..............................................2-10
2.1.10.2Crystal Oscillator (EXTAL, XTAL)..........................................................2-11
2.1.10.3External Filter Capacitor (XFC)..............................................................2-11
2.1.10.4Clock Mode Select (MODCK1–MODCK0).............................................2-11
2.1.11Instrumentation and Emulation Signals.................................................2-11
2.1.11.1Instruction Fetch/Development Serial Input (IFETCH/DSI)....................2-11
2.1.11.2Instruction Pipe/Development Serial Output (IPIPE0/DSO)...................2-11
2.1.11.3Instruction Pipe/Row Address Select Double-Drive (IPIPE1/RAS1DD).2-11
2.1.11.4Breakpoint/Development Serial clock (BKPT/DSCLK)..........................2-11
2.1.11.5Freeze/Initial Configuration (FREEZE/CONFIG2).................................2-12
2.1.12Test Signals...........................................................................................2-12
2.1.12.1TRI-State Signal (TRIS).........................................................................2-12
2.1.12.2Test Reset (TRST).................................................................................2-12
2.1.12.3Test Clock (TCK)...................................................................................2-12
2.1.12.4Test Mode Select (TMS)........................................................................2-12
2.1.12.5Test Data In (TDI)..................................................................................2-12
2.1.12.6Test Data Out (TDO)..............................................................................2-12
2.1.13Initial Configuration Pins (CONFIG).......................................................2-12
2.1.14Power Signals........................................................................................2-13
2.1.14.1VCCSYN and GNDSYN.........................................................................2-13
2.1.14.2VCCCLK and GNDCLK.........................................................................2-13
2.1.14.3GNDS1 and GNDS2..............................................................................2-13
2.1.14.4VCC and GND.......................................................................................2-13
2.1.14.5NC4–NC1...............................................................................................2-13
2.2System Bus Signal Index in Slave Mode...............................................2-14
2.3On-Chip Peripherals Signal Index..........................................................2-15
Section 3
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QUICC Memory Map
3.1Dual-Port RAM Memory Map..................................................................3-2
3.2CPM Sub-Module Base Addresses.........................................................3-3
3.3Internal Registers Memory Map..............................................................3-4
3.3.1SIM Registers Memory Map....................................................................3-4
3.3.2CPM Registers Memory Map..................................................................3-6
Section 4
Bus Operation
4.1Bus Transfer Signals...............................................................................4-2
4.1.1Bus Control Signals.................................................................................4-3
4.1.2Function Codes (FC3–FC0)....................................................................4-3
4.1.3Address Bus (A31–A0)............................................................................4-4
4.1.4Address Strobe (AS)...............................................................................4-4
4.1.5Data Bus (D31-D0)..................................................................................4-4
4.1.6Data Strobe (DS).....................................................................................4-4
4.1.7Output Enable (OE).................................................................................4-4
4.1.8Byte Write Enable (WE0, WE1, WE2, WE3)...........................................4-4
4.1.9Bus Cycle Termination Signals...............................................................4-5
4.1.9.1Data transfer and size acknowledge (DSACK1 and DSACK0)...............4-5
4.1.9.2Bus Error (BERR)....................................................................................4-5
4.1.9.3Autovector (AVEC)..................................................................................4-6
4.2Data Transfer Mechanism.......................................................................4-6
4.2.1Dynamic Bus Sizing................................................................................4-6
4.2.2Misaligned Operands............................................................................4-11
4.2.3Effects of Dynamic Bus Sizing and Operand Misalignment..................4-19
4.2.4Bus Operation.......................................................................................4-20
4.2.5Synchronous Operation with DSACKx..................................................4-21
4.2.6Fast Termination Cycles........................................................................4-21
4.3Data Transfer Cycles.............................................................................4-22
4.3.1Read Cycle............................................................................................4-23
4.3.2Write Cycle............................................................................................4-26
4.3.3Read-Modify-Write Cycle......................................................................4-28
4.4CPU Space Cycles................................................................................4-31
4.4.1Breakpoint Acknowledge Cycle.............................................................4-31
4.4.2LPSTOP Broadcast Cycle.....................................................................4-35
4.4.3Module Base Address Register (MBAR) Access..................................4-36
4.4.4Interrupt Acknowledge Bus Cycles........................................................4-36
4.4.4.1Interrupt Acknowledge Cycle—Terminated Normally............................4-36
4.4.4.2Autovector Interrupt Acknowledge Cycle..............................................4-38
4.4.4.3Spurious Interrupt Cycle........................................................................4-40
4.5Bus Exception Control Cycles...............................................................4-41
4.5.1Bus Errors.............................................................................................4-42
4.5.2Retry Operation.....................................................................................4-44
4.5.3Halt Operation.......................................................................................4-46
4.5.4Double Bus Fault...................................................................................4-48
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4.6Bus Arbitration.......................................................................................4-49
4.6.1Bus Request..........................................................................................4-52
4.6.2Bus Grant...............................................................................................4-53
4.6.3Bus Grant Acknowledge........................................................................4-53
4.6.4Bus Arbitration Control...........................................................................4-54
4.6.5Slave (Disable CPU32+) Mode Bus Arbitration.....................................4-55
4.6.6Slave (Disable CPU32+) Mode Bus Exceptions....................................4-59
4.6.6.1HALT......................................................................................................4-59
4.6.6.2RETRY...................................................................................................4-59
4.6.7Internal Accesses...................................................................................4-59
4.6.8Show Cycles..........................................................................................4-62
4.7Reset Operation.....................................................................................4-63
Section 5
CPU32+
5.1Overview..................................................................................................5-1
5.1.1Features...................................................................................................5-2
5.1.2Loop Mode Instruction Execution.............................................................5-3
5.1.3Vector Base Register...............................................................................5-4
5.1.4Exception Handling..................................................................................5-4
5.1.5Addressing Modes...................................................................................5-5
5.2Architecture Summary.............................................................................5-5
5.2.1Programming Model.................................................................................5-6
5.2.2Registers..................................................................................................5-7
5.3Instruction Set..........................................................................................5-8
5.3.1M68000 Family Compatibility.................................................................5-10
5.3.1.1New Instructions....................................................................................5-10
5.3.1.2Low-Power Stop (LPSTOP)...................................................................5-10
5.3.1.3Table Lookup and Interpolate (TBL)......................................................5-10
5.3.1.4Unimplemented Instructions..................................................................5-10
5.3.2Instruction Format and Notation.............................................................5-10
5.3.3Instruction Summary..............................................................................5-13
5.3.3.1Condition Code Register........................................................................5-17
5.3.3.2Data Movement Instructions..................................................................5-19
5.3.3.3Integer Arithmetic Operations................................................................5-19
5.3.3.4Logic Instructions...................................................................................5-21
5.3.3.5Shift and Rotate Instructions..................................................................5-22
5.3.3.6Bit Manipulation Instructions..................................................................5-23
5.3.3.7Binary-Coded Decimal (BCD) Instructions.............................................5-24
5.3.3.8Program Control Instructions.................................................................5-24
5.3.3.9System Control Instructions...................................................................5-25
5.3.3.10Condition Tests......................................................................................5-26
5.3.4Using the TBL Instructions.....................................................................5-27
5.3.4.1Table Example 1: Standard Usage........................................................5-28
5.3.4.2Table Example 2: Compressed Table....................................................5-29
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5.3.4.3Table Example 3: 8-Bit Independent Variable.......................................5-30
5.3.4.4Table Example 4: Maintaining Precision...............................................5-32
5.3.4.5Table Example 5: Surface Interpolations..............................................5-33
5.3.5Nested Subroutine Calls........................................................................5-33
5.3.6Pipeline Synchronization with the NOP Instruction...............................5-34
5.4Processing States.................................................................................5-34
5.4.1State Transitions...................................................................................5-34
5.4.2Privilege Levels.....................................................................................5-34
5.4.2.1Supervisor Privilege Level.....................................................................5-35
5.4.2.2User Privilege Level..............................................................................5-35
5.4.2.3Changing Privilege Level.......................................................................5-35
5.5Exception Processing............................................................................5-36
5.5.1Exception Vectors.................................................................................5-36
5.5.1.1Types of Exceptions..............................................................................5-36
5.5.1.2Exception Processing Sequence...........................................................5-38
5.5.1.3Exception Stack Frame.........................................................................5-38
5.5.1.4Multiple Exceptions...............................................................................5-39
5.5.2Processing of Specific Exceptions........................................................5-40
5.5.2.1Reset.....................................................................................................5-40
5.5.2.2Bus Error...............................................................................................5-40
5.5.2.3Address Error........................................................................................5-42
5.5.2.4Instruction Traps....................................................................................5-42
5.5.2.5Software Breakpoints............................................................................5-43
5.5.2.6Hardware Breakpoints...........................................................................5-43
5.5.2.7Format Error..........................................................................................5-43
5.5.2.8Illegal or Unimplemented Instructions...................................................5-44
5.5.2.9Privilege Violations................................................................................5-44
5.5.2.10Tracing..................................................................................................5-45
5.5.2.11Interrupts...............................................................................................5-46
5.5.2.12Return from Exception...........................................................................5-47
5.5.3Fault Recovery......................................................................................5-48
5.5.3.1Types of Faults......................................................................................5-51
5.5.3.1.1Type I—Released Write Faults.............................................................5-51
5.5.3.1.2Type II—Prefetch, Operand, RMW, and MOVEP Faults.......................5-51
5.5.3.1.3Type III—Faults During MOVEM Operand Transfer.............................5-52
5.5.3.1.4Type IV—Faults During Exception Processing.....................................5-52
5.5.3.2Correcting a Fault..................................................................................5-53
5.5.3.2.1Type I—Completing Released Writes via Software..............................5-53
5.5.3.2.2Type I—Completing Released Writes via RTE.....................................5-53
5.5.3.2.3Type II—Correcting Faults via RTE.......................................................5-54
5.5.3.2.4Type III—Correcting Faults via Software...............................................5-54
5.5.3.2.5Type III—Correcting Faults by Conversion and Restart........................5-55
5.5.3.2.6Type III—Correcting Faults via RTE......................................................5-55
5.5.3.2.7Type IV—Correcting Faults via Software..............................................5-55
5.5.4CPU32+ Stack Frames.........................................................................5-56
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5.5.4.1Four-Word Stack Frame........................................................................5-56
5.5.4.2Six-Word Stack Frame...........................................................................5-56
5.5.4.3Bus Error Stack Frame..........................................................................5-56
5.6Development Support............................................................................5-59
5.6.1CPU32+ Integrated Development Support............................................5-59
5.6.1.1Background Debug Mode (BDM) Overview...........................................5-59
5.6.1.2Deterministic Opcode Tracking Overview..............................................5-60
5.6.1.3On-Chip Hardware Breakpoint Overview...............................................5-60
5.6.2Background Debug Mode......................................................................5-60
5.6.2.1Enabling BDM........................................................................................5-60
5.6.2.2BDM Sources.........................................................................................5-61
5.6.2.2.1External BKPT Signal............................................................................5-62
5.6.2.2.2BGND Instruction...................................................................................5-62
5.6.2.2.3Double Bus Fault...................................................................................5-62
5.6.2.3Entering BDM.........................................................................................5-62
5.6.2.4Command Execution..............................................................................5-62
5.6.2.5BDM Registers.......................................................................................5-63
5.6.2.5.1Fault Address Register (FAR)................................................................5-63
5.6.2.5.2Return Program Counter (RPC).............................................................5-63
5.6.2.5.3Current Instruction Program Counter (PCC)..........................................5-63
5.6.2.6Returning from BDM..............................................................................5-63
5.6.2.7Serial Interface.......................................................................................5-63
5.6.2.7.1CPU Serial Logic....................................................................................5-65
5.6.2.7.2Development System Serial Logic.........................................................5-66
5.6.2.8Command Set........................................................................................5-68
5.6.2.8.1Command Format..................................................................................5-68
5.6.2.8.2Command Sequence Diagram...............................................................5-69
5.6.2.8.3Command Set Summary........................................................................5-69
5.6.2.8.4Read A/D Register (RAREG/RDREG)...................................................5-71
5.6.2.8.5Write A/D Register (WAREG/WDREG).................................................5-71
5.6.2.8.6Read System Register (RSREG)...........................................................5-71
5.6.2.8.7Write System Register (WSREG)..........................................................5-72
5.6.2.8.8Read Memory Location (READ)............................................................5-73
5.6.2.8.9Write Memory Location (WRITE)...........................................................5-74
5.6.2.8.10Dump Memory Block (DUMP)................................................................5-75
5.6.2.8.11Fill Memory Block (FILL)........................................................................5-76
5.6.2.8.12Resume Execution (GO)........................................................................5-77
5.6.2.8.13Call User Code (CALL)..........................................................................5-77
5.6.2.8.14Reset Peripherals (RST)........................................................................5-79
5.6.2.8.15No Operation (NOP)..............................................................................5-79
5.6.2.8.16Future Commands.................................................................................5-80
5.6.3Deterministic Opcode Tracking..............................................................5-80
5.6.3.1Instruction Fetch (IFETCH)....................................................................5-80
5.6.3.2Instruction Pipe (IPIPE1–IPIPE0)..........................................................5-80
5.6.3.3Opcode Tracking during Loop Mode......................................................5-82
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5.7Instruction Execution Timing.................................................................5-82
5.7.1Resource Scheduling............................................................................5-83
5.7.1.1Microsequencer.....................................................................................5-83
5.7.1.2Instruction Pipeline................................................................................5-83
5.7.1.3Bus Controller Resources.....................................................................5-83
5.7.1.3.1Prefetch Controller................................................................................5-84
5.7.1.3.2Write-Pending Buffer.............................................................................5-84
5.7.1.3.3Microbus Controller...............................................................................5-85
5.7.1.4Instruction Execution Overlap...............................................................5-85
5.7.1.5Effects of Wait States............................................................................5-86
5.7.1.6Instruction Execution Time Calculation.................................................5-86
5.7.1.7Effects of Negative Tails........................................................................5-87
5.7.2Instruction Timing Tables......................................................................5-88
5.7.2.1Fetch Effective Address........................................................................5-90
5.7.2.2Calculate Effective Address..................................................................5-91
5.7.2.3MOVE Instruction..................................................................................5-92
5.7.2.4Special-Purpose MOVE Instruction.......................................................5-92
5.7.2.5Arithmetic/Logic Instructions.................................................................5-93
5.7.2.6Immediate Arithmetic/Logic Instructions................................................5-95
5.7.2.7Binary-Coded Decimal and Extended Instructions................................5-95
5.7.2.8Single Operand Instructions..................................................................5-96
5.7.2.9Shift/Rotate Instructions........................................................................5-96
5.7.2.10Bit Manipulation Instructions.................................................................5-97
5.7.2.11Conditional Branch Instructions.............................................................5-98
5.7.2.12Control Instructions...............................................................................5-99
5.7.2.13Exception-Related Instructions and Operations..................................5-100
5.7.2.14Save and Restore Operations.............................................................5-101
Section 6
System Integration Module (SIM60)
6.1Module Overview.....................................................................................6-1
6.2Module Base Address Register (MBAR).................................................6-3
6.3System Configuration and Protection......................................................6-3
6.3.1System Configuration..............................................................................6-5
6.3.1.1SIM60 Interrupt Generation.....................................................................6-6
6.3.1.2Simultaneous SIM60 Interrupt Sources...................................................6-8
6.3.1.2.1Bus Monitor.............................................................................................6-8
6.3.1.2.2Spurious Interrupt Monitor.......................................................................6-8
6.3.1.2.3Double Bus Fault Monitor........................................................................6-9
6.3.1.2.4Software Watchdog Timer (SWT)...........................................................6-9
6.3.2Periodic Interrupt Timer (PIT)................................................................6-10
6.3.2.1PIT Period Calculation...........................................................................6-10
6.3.2.2Using the PIT as a Real-Time Clock.....................................................6-11
6.3.3Freeze Support......................................................................................6-11
6.3.4Low-Power Stop Support......................................................................6-11
6.4Low Power in Normal Operation...........................................................6-12
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6.5SIM60 System Clock Generation...........................................................6-12
6.5.1Clock Generation Methods....................................................................6-12
6.5.2Oscillator Prescaler (Divide by 128).......................................................6-13
6.5.3Phase-Locked Loop (PLL).....................................................................6-14
6.5.3.1Frequency Multiplication........................................................................6-14
6.5.3.2Skew Elimination....................................................................................6-15
6.5.4Low-Power Divider.................................................................................6-15
6.5.5QUICC Internal Clock Signals................................................................6-15
6.5.5.1SPCLK...................................................................................................6-16
6.5.5.2General System Clock...........................................................................6-16
6.5.5.3BRGCLK................................................................................................6-17
6.5.5.4SyncCLK................................................................................................6-17
6.5.5.5SIMCLK..................................................................................................6-18
6.5.5.6CLKO1...................................................................................................6-18
6.5.5.7CLKO2...................................................................................................6-18
6.5.6PLL Power Pins.....................................................................................6-19
6.5.6.1VCCSYN................................................................................................6-19
6.5.6.2GNDSYN................................................................................................6-19
6.5.6.3XFC........................................................................................................6-19
6.5.7CLKO Power Pins..................................................................................6-19
6.5.
7.1VCCCLK................................................................................................6-19
6.5.
7.2GNDCLK................................................................................................6-19
6.5.8Configuration Pins (MODCK1–MODCK0).............................................6-19
6.6Breakpoint Logic....................................................................................6-20
6.7External Bus Interface Control...............................................................6-21
6.7.1Initial Configuration................................................................................6-22
6.7.2Port D.....................................................................................................6-22
6.7.3Port E.....................................................................................................6-23
6.8Slave (Disable CPU32+) Mode..............................................................6-23
6.8.1MBAR in a Multiple QUICC System.......................................................6-24
6.8.2Global Chip Select (CS0) in Slave Mode...............................................6-25
6.8.3Bus Clear in Slave Mode.......................................................................6-25
6.8.4Interrupts in Slave Mode........................................................................6-26
6.8.5Pin Differences in Slave Mode...............................................................6-26
6.8.6Other Functionality in Slave Mode.........................................................6-27
6.9Programmer’s Model..............................................................................6-27
6.9.1Module Base Address Register (MBAR)................................................6-27
6.9.2Module Base Address Register Enable (MBARE).................................6-29
6.9.3System Configuration and Protection Registers....................................6-29
6.9.3.1Module Configuration Register (MCR)...................................................6-29
6.9.3.2Autovector Register (AVR).....................................................................6-34
6.9.3.3Reset Status Register (RSR).................................................................6-34
6.9.3.4Software Watchdog Interrupt Vector Register (SWIV)...........................6-35
6.9.3.5System Protection Control Register (SYPCR).......................................6-35
6.9.3.6Periodic Interrupt Control Register (PICR).............................................6-37
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6.9.3.7Periodic Interrupt Timer Register (PITR)...............................................6-38
6.9.3.8Software Service Register (SWSR).......................................................6-39
6.9.3.9CLKO Control Register (CLKOCR).......................................................6-39
6.9.3.10PLL Control Register (PLLCR)..............................................................6-40
6.9.3.11Clock Divider Control Register (CDVCR)..............................................6-42
6.9.3.12Breakpoint Address Register (BKAR)...................................................6-44
6.9.3.13Breakpoint Control Register (BKCR).....................................................6-44
6.9.4Port E Pin Assignment Register (PEPAR)............................................6-48
6.10Memory Controller.................................................................................6-50
6.10.1Memory Controller Key Features..........................................................6-50
6.10.2Memory Controller Overview.................................................................6-51
6.11General-Purpose Chip-Select Overview (SRAM Banks).......................6-56
6.11.1Associated Registers.............................................................................6-56
6.11.28-, 16-, and 32-Bit Port Size Configuration............................................6-56
6.11.3Write Protect Configuration...................................................................6-56
6.11.4Programmable Wait State Configuration...............................................6-56
6.11.5Address and Address Space Checking.................................................6-57
6.11.6SRAM Bank Parity.................................................................................6-57
6.11.7External Master Support........................................................................6-57
6.11.8Global (Boot) Chip-Select Operation.....................................................6-58
6.11.9SRAM Bus Error....................................................................................6-58
6.12DRAM Controller Overview (DRAM Banks)..........................................6-58
6.12.1DRAM Normal Access Support.............................................................6-60
6.12.2DRAM Page Mode Support...................................................................6-60
6.12.3DRAM Burst Access Support................................................................6-61
6.12.4DRAM Bank Parity................................................................................6-62
6.12.5Refresh Operation.................................................................................6-62
6.12.6DRAM Bank External Master Support...................................................6-63
6.12.7Double-Drive RAS Lines.......................................................................6-63
6.12.8DRAM Bus Error....................................................................................6-63
6.13Programming Model..............................................................................6-64
6.13.1Global Memory Register (GMR)............................................................6-64
6.13.2Memory Controller Status Register (MSTAT)........................................6-69
6.13.3Base Register (BR)...............................................................................6-70
6.13.4Option Register (OR).............................................................................6-74
6.13.5DRAM-SRAM Performance Summary;.................................................6-78
Section 7
Communication Processor Module (CPM)
Introduction..............................................................................................7-1
7.1RISC Controller.......................................................................................7-3
7.1.1 RISC Controller Configuration Register (RCCR)....................................7-4
7.1.2 RISC Microcode Revision Number.........................................................7-5
7.2 Command Set........................................................................................7-5
7.2.1Command Register Examples.................................................................7-8
7.2.2Command Execution Latency.................................................................7-8
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7.3Dual-Port RAM.........................................................................................7-8
7.3.1Buffer Descriptors..................................................................................7-10
7.3.2Parameter RAM.....................................................................................7-10
7.4RISC Timer Tables................................................................................7-11
7.4.1RISC Timer Table Parameter RAM.......................................................7-12
7.4.2RISC Timer Table Entries......................................................................7-14
7.4.3RISC Timer Event Register (RTER)......................................................7-14
7.4.4RISC Timer Mask Register (RTMR)......................................................7-14
7.4.5SET TIMER Command..........................................................................7-14
7.4.6RISC Timer Initialization Sequence.......................................................7-14
7.4.7RISC Timer Initialization Example.........................................................7-15
7.4.8 RISC Timer Interrupt Handling..............................................................7-16
7.4.9 RISC Timer Table Algorithm.................................................................7-16
7.4.10RISC Timer Table Application: Track the RISC Loading.......................7-16
7.5 Timers...................................................................................................7-17
7.5.1Timer Key Features...............................................................................7-17
7.5.2 General-Purpose Timer Units...............................................................7-18
7.5.2.1Cascaded Mode.....................................................................................7-19
7.5.2.2Timer Global Configuration Register (TGCR)........................................7-20
7.5.2.3Timer Mode Register (TMR1, TMR2, TMR3, TMR4).............................7-21
7.5.2.4Timer Reference Registers (TRR1, TRR2, TRR3, TRR4).....................7-22
7.5.2.5Timer Capture Registers (TCR1, TCR2, TCR3, TCR4).........................7-22
7.5.2.6Timer Counter (TCN1, TCN2, TCN3, TCN4).........................................7-22
7.5.2.7Timer Event Registers (TER1, TER2, TER3, TER4).............................7-22
7.5.3Timer Examples.....................................................................................7-23
7.6IDMA Channels......................................................................................7-24
7.6.1 IDMA Key Features;..............................................................................7-25
7.6.2 IDMA Registers.....................................................................................7-26
7.6.2.1IDMA Channel Configuration Register (ICCR).......................................7-26
7.6.2.2Channel Mode Register (CMR)..............................................................7-28
7.6.2.3Source Address Pointer Register (SAPR).............................................7-30
7.6.2.4Destination Address Pointer Register (DAPR).......................................7-31
7.6.2.5Function Code Register (FCR)..............................................................7-31
7.6.2.6Byte Count Register (BCR)....................................................................7-31
7.6.2.7Channel Status Register (CSR).............................................................7-32
7.6.2.8Channel Mask Register (CMAR)............................................................7-33
7.6.2.9Data Holding Register (DHR).................................................................7-33
7.6.3 Interface Signals...................................................................................7-33
7.6.3.1DREQ and DACK...................................................................................7-33
7.6.3.2DONEx...................................................................................................7-33
7.6.4 IDMA Operation....................................................................................7-34
7.6.4.1Single Buffer..........................................................................................7-34
7.6.4.2Auto Buffer and Buffer Chaining............................................................7-34
7.6.4.2.1IDMA Parameter RAM...........................................................................7-35
7.6.4.2.2IDMA Buffer Descriptors (BDs)..............................................................7-36
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7.6.4.2.3IDMA Commands (INIT_IDMA).............................................................7-38
7.6.4.3Starting the IDMA..................................................................................7-38
7.6.4.4Requesting IDMA Transfers..................................................................7-39
7.6.4.4.1Internal Maximum Rate.........................................................................7-39
7.6.4.4.2Internal Limited Rate.............................................................................7-39
7.6.4.4.3External Burst Mode..............................................................................7-40
7.6.4.4.4External Cycle Steal..............................................................................7-42
7.6.4.5IDMA Bus Arbitration.............................................................................7-43
7.6.4.6IDMA Operand Transfers......................................................................7-45
7.6.4.6.1Dual Address Mode...............................................................................7-45
7.6.4.6.2Single Address Mode (Flyby Transfers)................................................7-48
7.6.4.6.3Fast-Termination Option........................................................................7-50
7.6.4.6.4Externally Recognizing IDMA Operand Transfers.................................7-51
7.6.4.7Bus Exceptions......................................................................................7-51
7.6.4.7.1Reset.....................................................................................................7-51
7.6.4.7.2Bus Error...............................................................................................7-51
7.6.4.7.3Retry......................................................................................................7-51
7.6.4.8Ending the IDMA Transfer.....................................................................7-52
7.6.4.8.1Single Buffer Mode Termination............................................................7-52
7.6.4.8.2Auto Buffer Mode Termination..............................................................7-53
7.6.4.8.3Buffer Chaining Mode Termination........................................................7-54
7.6.5 IDMA Examples....................................................................................7-55
7.6.5.1Single Buffer Examples.........................................................................7-55
7.6.5.2Buffer Chaining Example.......................................................................7-55
7.6.5.3Auto Buffer Example.............................................................................7-56
7.7SDMA Channels....................................................................................7-57
7.7.1SDMA Bus Arbitration and Bus Transfers.............................................7-57
7.7.2SDMA Registers....................................................................................7-59
7.7.2.1SDMA Configuration Register (SDCR)..................................................7-59
7.7.2.2SDMA Status Register (SDSR).............................................................7-61
7.7.2.3SDMA Address Register (SDAR)..........................................................7-61
7.8Serial Interface with Time Slot Assigner................................................7-62
7.8.1 SI Key Features....................................................................................7-62
7.8.2 TSA Overview......................................................................................7-64
7.8.3 Enabling Connections to the TSA........................................................7-67
7.8.4 SI RAM.................................................................................................7-68
7.8.4.1One Multiplexed Channel with Static Frames.......................................7-69
7.8.4.2One Multiplexed Channel with Dynamic Frames..................................7-69
7.8.4.3Two Multiplexed Channels with Static Frames......................................7-70
7.8.4.4Two Multiplexed Channels with Dynamic Frames.................................7-71
7.8.4.5Programming SI RAM Entries...............................................................7-72
7.8.4.6SI RAM Programming Example............................................................7-75
7.8.4.7SI RAM Dynamic Changes....................................................................7-75
7.8.5SI Registers...........................................................................................7-77
7.8.5.1SI Global Mode Register (SIGMR)........................................................7-77
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7.8.5.2SI Mode Register (SIMODE)..................................................................7-78
7.8.5.3SI Clock Route Register (SICR).............................................................7-86
7.8.5.4SI Command Register (SICMR).............................................................7-87
7.8.5.5SI Status Register (SISTR)....................................................................7-87
7.8.5.6SI RAM Pointers (SIRP).........................................................................7-88
7.8.5.6.1SIRP When RDM = 00 (One Static TDM)..............................................7-89
7.8.5.6.2SIRP When RDM = 01 (One Dynamic TDM).........................................7-89
7.8.5.6.3SIRP When RDM = 10 (Two Static TDMs)............................................7-90
7.8.5.6.4SIRP When RDM = 11 (Two Dynamic TDMs).......................................7-90
7.8.6 SI IDL Interface Support.......................................................................7-90
7.8.6.1IDL Interface Example...........................................................................7-91
7.8.6.2IDL Interface Programming....................................................................7-95
7.8.7 SI GCI Support......................................................................................7-96
7.8.7.1SI GCI Activation/Deactivation Procedure.............................................7-98
7.8.7.2SI GCI Programming..............................................................................7-98
7.8.7.2.1Normal Mode GCI Programming...........................................................7-98
7.8.7.2.2SCIT Programming................................................................................7-98
7.8.8Serial Interface Synchronization..........................................................7-100
7.8.9NMSI Configuration..............................................................................7-100
7.9Baud Rate Generators (BRGs)............................................................7-103
7.9.1 Autobaud Support...............................................................................7-105
7.9.2 BRG Configuration Register (BRGC)..................................................7-106
7.9.3 UART Baud Rate Examples...............................................................7-108
7.10Serial Communication Controllers (SCCs)...........................................7-109
7.10.1SCC Overview.....................................................................................7-110
7.10.2 General SCC Mode Register (GSMR)................................................7-111
7.10.3 SCC Protocol-Specific Mode Register (PSMR)..................................7-120
7.10.4 SCC Data Synchronization Register (DSR)........................................7-121
7.10.5 SCC Transmit on Demand Register (TODR)......................................7-121
7.10.6 SCC Buffer Descriptors.......................................................................7-122
7.10.7 SCC Parameter RAM..........................................................................7-124
7.10.7.1BD Table Pointer (RBASE, TBASE)....................................................7-125
7.10.7.2SCC Function Code Registers (RFCR, TFCR)....................................7-125
7.10.7.3Maximum Receive Buffer Length Register (MRBLR)..........................7-127
7.10.7.4Receiver BD Pointer (RBPTR).............................................................7-127
7.10.7.5Transmitter BD Pointer (TBPTR).........................................................7-127
7.10.7.6Other General Parameters...................................................................7-128
7.10.8 Interrupts from the SCCs....................................................................7-128
7.10.8.1SCC Event Register (SCCE)...............................................................7-128
7.10.8.2SCC Mask Register (SCCM)...............................................................7-129
7.10.8.3SCC Status Register (SCCS)..............................................................7-129
7.10.9 SCC Initialization.................................................................................7-129
7.10.10SCC Interrupt Handling........................................................................7-130
7.10.11SCC Timing Control.............................................................................7-130
7.10.11.1Synchronous Protocols........................................................................7-130
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7.10.11.2Asynchronous Protocols......................................................................7-134
7.10.12Digital Phase-Locked Loop (DPLL).....................................................7-135
7.10.12.1Data Encoding.....................................................................................7-135
7.10.12.2DPLL Operation...................................................................................7-136
7.10.13Clock Glitch Detection.........................................................................7-139
7.10.14Disabling the SCCs on the Fly............................................................7-139
7.10.14.1SCC Transmitter Full Sequence..........................................................7-140
7.10.14.2SCC Transmitter Shortcut SEQUENCE..............................................7-140
7.10.14.3SCC Receiver Full Sequence..............................................................7-140
7.10.14.4SCC Receiver Shortcut Sequence......................................................7-141
7.10.14.5Switching Protocols.............................................................................7-141
7.10.15Saving Power......................................................................................7-141
7.10.16UART Controller..................................................................................7-141
7.10.16.1UART Key Features............................................................................7-143
7.10.16.2Normal Asynchronous Mode...............................................................7-143
7.10.16.3Synchronous Mode.............................................................................7-144
7.10.16.4UART Memory Map.............................................................................7-145
7.10.16.5UART Programming Model.................................................................7-147
7.10.16.6UART Command Set...........................................................................7-147
7.10.16.6.1Transmit Commands...........................................................................7-147
7.10.16.6.2Receive Commands............................................................................7-148
7.10.16.7UART Address Recognition (Receiver)...............................................7-149
7.10.16.8UART Control Characters (Receiver)..................................................7-150
7.10.16.9Wake-Up Timer (Receiver)..................................................................7-151
7.10.16.10Break Support (Receiver)....................................................................7-151
7.10.16.11Send Break (Transmitter)....................................................................7-153
7.10.16.12Sending a Preamble (Transmitter)......................................................7-153
7.10.16.13Fractional Stop Bits (Transmitter)........................................................7-153
7.10.16.14UART Error-Handling Procedure.........................................................7-154
7.10.16.14.1Transmission Error..............................................................................7-155
7.10.16.14.2Reception Errors.................................................................................7-155
7.10.16.15UART Mode Register (PSMR)............................................................7-156
7.10.16.16UART Receive Buffer Descriptor (Rx BD)...........................................7-159
7.10.16.17UART Transmit Buffer Descriptor (Tx BD)..........................................7-163
7.10.16.18UART Event Register (SCCE).............................................................7-164
7.10.16.19UART Mask Register (SCCM).............................................................7-167
7.10.16.20SCC Status Register (SCCS)..............................................................7-167
7.10.16.21SCC UART Example...........................................................................7-167
7.10.16.22S-Records Programming Example......................................................7-169
7.10.17HDLC Controller..................................................................................7-169
7.10.17.1HDLC Controller Key Features............................................................7-170
7.10.17.2HDLC Channel Frame Transmission Processing................................7-171
7.10.17.3HDLC Channel Frame Reception Processing.....................................7-172
7.10.17.4HDLC Memory Map.............................................................................7-172
7.10.17.5HDLC Programming Model.................................................................7-174
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7.10.17.6HDLC Command Set...........................................................................7-175
7.10.17.6.1Transmit Commands............................................................................7-175
7.10.17.6.2Receive Commands.............................................................................7-176
7.10.17.7HDLC Error-handling Procedure..........................................................7-176
7.10.17.7.1Transmission Errors.............................................................................7-176
7.10.17.7.2Reception Errors..................................................................................7-177
7.10.17.8HDLC Mode Register (PSMR).............................................................7-178
7.10.17.9HDLC Receive Buffer Descriptor (Rx BD)...........................................7-179
7.10.17.10HDLC Transmit Buffer Descriptor (Tx BD)...........................................7-183
7.10.17.11HDLC Event Register (SCCE).............................................................7-184
7.10.17.12HDLC Mask Register (SCCM).............................................................7-186
7.10.17.13SCC Status Register (SCCS)..............................................................7-187
7.10.17.14SCC HDLC Example #1.......................................................................7-187
7.10.17.15SCC HDLC Example #2.......................................................................7-189
7.10.18HDLC Bus Controller...........................................................................7-189
7.10.18.1HDLC Bus Key Features......................................................................7-192
7.10.18.2HDLC Bus Operation...........................................................................7-192
7.10.18.2.1Accessing the HDLC Bus.....................................................................7-192
7.10.18.2.2More Performance...............................................................................7-193
7.10.18.2.3Delayed RTS Mode..............................................................................7-194
7.10.18.2.4Using the TSA......................................................................................7-195
7.10.18.3HDLC Bus Memory Map and Programming........................................7-196
7.10.18.3.1GSMR Programming............................................................................7-196
7.10.18.3.2PSMR Programming............................................................................7-196
7.10.18.3.3HDLC Bus Controller Example............................................................7-196
7.10.19AppleTalk Controller............................................................................7-196
7.10.19.1LocalTalk Bus Operation......................................................................7-197
7.10.19.2Appletalk Controller Key Features.......................................................7-198
7.10.19.3QUICC AppleTalk Hardware Connection.............................................7-198
7.10.19.4AppleTalk Memory Map and Programming Model...............................7-198
7.10.19.4.1GSMR Programming............................................................................7-199
7.10.19.4.2PSMR Programming............................................................................7-200
7.10.19.4.3TODR Programming............................................................................7-200
7.10.19.4.4AppleTalk Controller Example.............................................................7-200
7.10.20BISYNC Controller...............................................................................7-200
7.10.20.1BISYNC Controller Features................................................................7-201
7.10.20.2BISYNC Channel Frame Transmission...............................................7-201
7.10.20.3BISYNC Channel Frame Reception.....................................................7-202
7.10.20.4BISYNC Memory Map..........................................................................7-203
7.10.20.5BISYNC Command Set........................................................................7-204
7.10.20.5.1Transmit Commands............................................................................7-204
7.10.20.5.2Receive Commands.............................................................................7-205
7.10.20.6BISYNC Control Character Recognition..............................................7-206
7.10.20.7BSYNC-BISYNC SYNC Register.........................................................7-207
7.10.20.8BDLE-BISYNC DLE Register...............................................................7-208
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7.10.20.9Transmitting and Receiving the Synchronization Sequence...............7-208
7.10.20.10BISYNC Error-Handling PROCEDURE...............................................7-209
7.10.20.10.1Transmission Errors............................................................................7-209
7.10.20.10.2Reception Errors.................................................................................7-209
7.10.20.11BISYNC Mode Register (PSMR).........................................................7-209
7.10.20.12BISYNC Receive Buffer Descriptor (Rx BD).......................................7-211
7.10.20.13BISYNC Transmit Buffer Descriptor (Tx BD).......................................7-213
7.10.20.14BISYNC Event Register (SCCE).........................................................7-216
7.10.20.15BISYNC Mask Register (SCCM).........................................................7-217
7.10.20.16SCC Status Register (SCCS)..............................................................7-217
7.10.20.17Programming the BISYNC Controller..................................................7-217
7.10.20.18SCC BISYNC Example.......................................................................7-218
7.10.21Transparent Controller........................................................................7-220
7.10.21.1Transparent Controller Features.........................................................7-221
7.10.21.2Transparent Channel Frame Transmission Processing......................7-221
7.10.21.3Transparent Channel Frame Reception Processing...........................7-222
7.10.21.4Achieving Synchronization in Transparent Mode................................7-223
7.10.21.4.1In-Line Synchronization Pattern..........................................................7-223
7.10.21.4.2Transparent Synchronization Example...............................................7-224
7.10.21.5Transparent Memory Map...................................................................7-225
7.10.21.6Transparent Command Set.................................................................7-226
7.10.21.6.1Transmit Commands...........................................................................7-226
7.10.21.6.2Receive Commands............................................................................7-227
7.10.21.7Transparent Error-Handling Procedure...............................................7-227
7.10.21.7.1Transmission Errors............................................................................7-227
7.10.21.7.2Reception Errors.................................................................................7-228
7.10.21.8Transparent Mode Register (PSMR)...................................................7-228
7.10.21.9Transparent Receive Buffer Descriptor (Rx BD).................................7-228
7.10.21.10Transparent Transmit Buffer Descriptor (Tx BD).................................7-230
7.10.21.11Transparent Event Register (SCCE)...................................................7-232
7.10.21.12Transparent Mask Register (SCCM)...................................................7-233
7.10.21.13SCC Status Register (SCCS)..............................................................7-233
7.10.21.14SCC Transparent Example.................................................................7-233
7.10.22RAM Microcodes.................................................................................7-235
7.10.23Ethernet Controller..............................................................................7-235
7.10.23.1Ethernet On QUICC—MC68EN360....................................................7-236
7.10.23.2Ethernet Key Features........................................................................7-237
7.10.23.3Learning Ethernet on the QUICC........................................................7-238
7.10.23.4Connecting QUICC to Ethernet...........................................................7-239
7.10.23.5Ethernet Channel Frame Transmission...............................................7-241
7.10.23.6Ethernet Channel Frame Reception....................................................7-242
7.10.23.7CAM Interface.....................................................................................7-243
7.10.23.8Ethernet Memory Map.........................................................................7-246
7.10.23.9Ethernet Programming Model.............................................................7-250
7.10.23.10Ethernet Command Set.......................................................................7-250
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7.10.23.10.1Transmit Commands............................................................................7-250
7.10.23.10.2Receive Commands.............................................................................7-251
7.10.23.10.3SET GROUP ADDRESS Command....................................................7-251
7.10.23.11Ethernet Address Recognition.............................................................7-252
7.10.23.12Hash Table Algorithm..........................................................................7-253
7.10.23.13Interpacket Gap Time..........................................................................7-254
7.10.23.14Collision Handling................................................................................7-254
7.10.23.15Internal and External Loopback...........................................................7-255
7.10.23.16Ethernet Error-handling Procedure......................................................7-255
7.10.23.16.1Transmission Errors.............................................................................7-255
7.10.23.16.2Reception Errors..................................................................................7-256
7.10.23.17Ethernet Mode Register (PSMR).........................................................7-256
7.10.23.18Ethernet Receive Buffer Descriptor (Rx BD)........................................7-258
7.10.23.19Ethernet Transmit Buffer Descriptor (Tx BD).......................................7-261
7.10.23.20Ethernet Event Register (SCCE).........................................................7-264
7.10.23.21Ethernet Mask Register (SCCM).........................................................7-265
7.10.23.22Ethernet Status Register (SCCS)........................................................7-265
7.10.23.23SCC Ethernet Example........................................................................7-266
7.11Serial Management Controllers (SMCs)..............................................7-268
7.11.1SMC Overview.....................................................................................7-268
7.11.2General SMC Mode Register (SMCMR)..............................................7-270
7.11.3SMC Buffer Descriptors.......................................................................7-270
7.11.4SMC Parameter RAM..........................................................................7-270
7.11.4.1BD Table Pointer (RBASE, TBASE)....................................................7-271
7.11.4.2SMC Function Code Registers (RFCR, TFCR)...................................7-272
7.11.4.3Maximum Receive Buffer Length Register (MRBLR)..........................7-273
7.11.4.4Receiver Buffer Descriptor Pointer (RBPTR).......................................7-273
7.11.4.5Transmitter Buffer Descriptor Pointer (TBPTR)...................................7-274
7.11.4.6Other General Parameters...................................................................7-274
7.11.5Disabling the SMCs on the Fly.............................................................7-274
7.11.5.1SMC Transmitter Full Sequence..........................................................7-275
7.11.5.2SMC Transmitter Shortcut Sequence..................................................7-275
7.11.5.3SMC Receiver Full Sequence..............................................................7-275
7.11.5.4SMC Receiver Shortcut Sequence......................................................7-276
7.11.5.5Switching Protocols..............................................................................7-276
7.11.6Saving Power.......................................................................................7-276
7.11.7SMC as a UART..................................................................................7-276
7.11.7.1SMC UART Key Features....................................................................7-276
7.11.7.2SMC UART Comparison......................................................................7-276
7.11.7.3SMC UART Memory Map....................................................................7-277
7.11.7.4SMC UART Transmission Processing.................................................7-278
7.11.7.5SMC UART Reception Processing......................................................7-279
7.11.7.6SMC UART Programming Model.........................................................7-279
7.11.7.7SMC UART Command Set..................................................................7-279
7.11.7.7.1Transmit Commands............................................................................7-279