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VCA8500IRGCR,VCA8500IRGCRG4,VCA8500IRGCT,VCA8500IRGCT,,VCA8500BOARD, 规格书,Datasheet 资料

FEATURES APPLICATIONS

DESCRIPTION

Control

NOTE (1): 20dB, 25dB, 27dB, or 30dB gain setting.

VCA8500

SBOS390A–JANUARY2008–REVISED MARCH2008 https://www.doczj.com/doc/2516775070.html,

8-Channel,Ultralow-Power,Variable Gain Amplifier

with Low-Noise Pre-Amp

?Medical Imaging,Ultrasound Systems ?Ultralow Power:65mW/Channel

–Portable Systems

?Low Noise:0.8nV/√Hz

–Low-and Mid-Range Systems

?Low-Noise Pre-Amp(LNP):

–20dB Fixed Gain

–250mV PP Linear Input Range

The VCA8500is an8-channel variable gain amplifier ?Variable Gain Amplifier:

consisting of a low-noise pre-amplifier(LNP)and a –Gain Control Range:46dB variable-gain amplifier(VGA).This combination,

along with the device features,makes it ideal for a –Selectable PGA Gain:

variety of ultrasound systems.

20dB,25dB,27dB,30dB

–Fast Overload Recovery The LNP gain is fixed at20dB,and has excellent

noise and signal handling characteristics.The gain of –Output Clamping Control

the voltage-controlled attenuator can vary over a ?Integrated Low-Pass Filter:46dB range with a0V to 1.2V control voltage

–Second-Order,Linear Phase common to all channels of the VCA8500.

–Bandwidth:10MHz,15MHz The post-gain amplifier(PGA)can be programmed ?High Accuracy:for four gain settings:20dB,25dB,27dB,or30dB

gain.As a means to improve system overload –Low Gain Error:±0.5dB

recovery time,the VCA8500provides an internal –Excellent Channel Matching:±0.25dB clamping function.The PGA settings as well the

?Distortion,HD2:–50dBc at5MHz clamp levels are controlled through the serial

interface.

?Integrated CW Switch Matrix:

–Easy Current Summing The VCA8500is built on TI’s BiCOM process and is

available in a small QFN-64PowerPAD?package.?Serial Control Interface

?Small Package:QFN-64,9×9mm

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

Infineon is a registered trademark of Infineon Technologies.

SPI is a trademark of Motorola.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.Copyright?2008,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas

Instruments standard warranty.Production processing does not

necessarily include testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS (1)(2)

VCA8500

SBOS390A–JANUARY 2008–REVISED MARCH 2008

This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION (1)

SPECIFIED PACKAGE-PACKAGE TEMPERATURE

PACKAGE ORDERING TRANSPORT MEDIA,

ECO PRODUCT LEAD DESIGNATOR

RANGE MARKING NUMBER QUANTITY STATUS (2)VCA8500IRGCT Tape and Reel,250Pb-Free,VCA8500

QFN-64

RGC

–40°C to +85°C

VCA8500

Green

VCA8500IRGCR

Tape and Reel,2000

(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI web site at https://www.doczj.com/doc/2516775070.html, .

(2)

Additional details including specific material content can be accessed at https://www.doczj.com/doc/2516775070.html,/leadfree

GREEN:Ti defines Green to mean Lead (Pb)-Free and in addition,uses less package materials including bromine (Br),or antimony (Sb)above 0.1%of total product weight.

N/A:Not yet available Lead (Pb)-Free;for estimated conversion dates,go to https://www.doczj.com/doc/2516775070.html,/leadfree .

Pb-FREE:Ti defines Lead (Pb)-Free to mean RoHS compatible,including a does not exceed 0.1%of total product weight,and,if designed to be soldered,suitable for use in specified lead-free soldering processes.

NOTE

These packages conform to Lead-Free and Green Manufacturing Specifications.

Over operating free-air temperature range,unless otherwise noted.

PARAMETER

VCA8500UNIT Supply voltage range,AVDD1–0.3to +3.9V Supply voltage range,AVDD2–0.3to +6V Supply voltage range,DVDD –0.3to +3.9V Voltage at analog inputs –0.3to (AVDD1+0.3)V Voltage at digital inputs

–0.3to (DVDD to +0.3)

V Soldering temperature (lead,5s)(3)

+260°C Maximum junction temperature (T J ),any condition

(2)

+150°C Maximum junction temperature (T J ),continuous operation,long-term +125°C reliability (2)

Storage temperature range,T stg –55to +150°C Operating temperature range,T A

–40to +85°C Human body model (HBM)

2000V ESD rating

Charged device model (CDM)1000V Machine model (MM)

200

(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)All voltage values are with respect to the ground terminal,which is the exposed thermal pad of the package.

(3)

Both the part being reworked and the board must be baked out before rework to reduce the risk of delamination.Refer to Application Note SLUA271(available for download at https://www.doczj.com/doc/2516775070.html, )for recommended rework techniques.

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ELECTRICAL CHARACTERISTICS

VCA8500 SBOS390A–JANUARY2008–REVISED MARCH2008

All specifications at T A=+25°C,AVDD2=5.0V,AVDD1=DVDD=3.3V;single-ended,ac-coupled(1μF)input configuration to the preamp (LNA),f IN=5MHz,V CNTL=1.0V,PG=30dB,clamp disabled(CL=1),LPF=15MHz,and R LOAD=1k?on each output to ground,unless otherwise noted.

VCA8500

TEST PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL(1) PREAMPLIFIER(LNA)

LNA gain Single-ended input to differential output20dB C

Input voltage Linear operation(THD≤–40dBc)250mV PP C

Input voltage noise At f=2MHz0.70nV/√Hz B

Input current noise At f=2MHz 3.0pA/√Hz B

Input bias voltage(V BL)Internally generated+2.4V B Bandwidth Small-signal,–3dB55MHz C

Input resistance(2)At f=4MHz8k?C

Input capacitance(2)Including internal ESD and clamping diodes30pF C

TGC SIGNAL PATH(LNA,VCA,PGA)

PGA=30dB,R S=0?,f=2MHz0.81nV/√Hz B

Input voltage noise

PGA=20dB,R S=0?,f=2MHz0.95nV/√Hz B Noise figure R S=200?,f=1MHz to10MHz 1.1dB C Group delay variation1MHz to10MHz±3ns B

To within1%of2V PP output

Overload recovery time80ns B

(V CNTL=0.54V),PGA=20dB

Output voltage(V OUT)Differential,non-clipped2V PP B Output common-mode voltage(V CM)+1.65V B

DC to10MHz,single-ended,

Output impedance1?C

either output

Output current R L=5?into V CM±20mA B Second-harmonic distortion f IN=5MHz,PGA=20dB,V OUT=1V PP–50–60dBc A

f IN=5MHz,PGA=30dB,V OUT=2V PP–42–55dBc A

Third-harmonic distortion f IN=5MHz,PGA=20dB,V OUT=1V PP–48–68dBc A

f IN=5MHz,PGA=30dB,V OUT=2V PP–40–50dBc A

f1=4.99MHz,f2=5.01MHz,

Two-tone intermodulation–52dBc B

V CNTL=1V;V OUT=1V PP

Worst case;PGA=20dB,V CNTRL=0.6V,

–67dBc B

V OUT=1V PP

Crosstalk,channel-to-channel

PGA=30dB,V OUT=1V PP–66dBc B FILTER

Low-pass filter(second-order)–3dB point10,15MHz B Tolerance±15%B

High-pass filter(first-order,due to

–3dB point,V CNTL=1.2V150kHz C internal ac coupling)

(1)Test levels:(A)100%tested at+25°C.Over temperature limits set by characterization and simulation.(B)Limits set by characterization

and simulation,not production tested.(C)Typical value only for information.

(2)See Figure29of the Typical Characteristics.

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VCA8500

SBOS390A–JANUARY 2008–REVISED MARCH 2008

ELECTRICAL CHARACTERISTICS (continued)

All specifications at T A =+25°C,AVDD2=5.0V,AVDD1=DVDD =3.3V;single-ended,ac-coupled (1μF)input configuration to the preamp (LNA),f IN =5MHz,V CNTL =1.0V,PG =30dB,clamp disabled (CL =1),LPF =15MHz,and R LOAD =1k ?on each output to ground,unless otherwise noted.

VCA8500

TEST PARAMETER

TEST CONDITIONS MIN TYP MAX UNIT

LEVEL (1)

ACCURACY 20,25,Gain (PGA)

Selectable through SPI?dB

A 27,30

Total gain,maximum LNA +PGA gain,V CNTL =1.2V 4849.551

dB A Gain range V CNTL =0V to 1.2V 46dB A Gain range V CNTL =0.1V to 1.0V 40dB A Gain slope

V CNTL =0.1V to 1.0V 44.4dB/V A Gain error,absolute

A 0.1V

B A 1.0V

±0.5dB A Gain matching Channel-to-channel ±0.25

±0.5dB A Output offset voltage Differential –25±1+25mV A Single-ended (3)

–50

±25+50

mV A Clamp level (V OUT )

CL =0

1.7V PP A CL =1(clamp disabled)

2.8

V PP

GAIN CONTROL INTERFACE Input voltage range (V CNTL )Gain range =46dB

0to 1.2V A Input resistance 25k ?C V CNTL =0V to 1.2V step;

Response time 0.5μs B to 90%signal level,V OUT =1V PP Gain control bandwidth 1.5

MHz

CW SIGNAL PATH

Output transconductance (V/I)At V IN =100mV PP 14

16.418

mA/V A At V IN =200mV PP

14.5mA/V B Dynamic CW output current,max 2.9mA PP B Static CW output current (sink)0.9mA B Output common-mode voltage (V CM0)Supplied externally +2.5V B Output compliance range Symmetric around V CMO ±0.5V B Output capacitance 10pF C Output impedance

50k ?C Input voltage noise,CW mode At f =2MHz

1.15nV/√Hz B Signal-dependent noise (RTO)

At 2kHz offset from 2MHz CW carrier +2dB B At 2kHz offset from 5MHz CW carrier

+2dB B Summing of eight channels (all modes)Output noise correlation factor

0.6

[compared to ideal 0dB](3)

Deviation from ideal common-mode voltage (V CM =1.65V).

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VCA8500 SBOS390A–JANUARY2008–REVISED MARCH2008

ELECTRICAL CHARACTERISTICS(continued)

VCA8500

TEST PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL(1) DIGITAL INPUTS(SDI)(PD,DIN,DOUT,CLK,RST)

V IH,high-level input voltage 2.0V D V B

V IL,low-level input voltage00.8V B

Input current±10μA A Clock frequency(f CLK)10k20M Hz B

Input resistance1M?C

Input capacitance5pF C POWER SUPPLY

Supply Voltages

AVDD1,DVDD Operating 3.15 3.3 3.6V B AVDD2Operating 4.755 5.25V B Supply Currents(4)

IAVDD1TGC mode(D5=1)145156mA A

CW mode(D5=0)7884mA A IDVDD TGC,CW mode 1.53mA A IAVDD2TGC mode810mA A

CW mode5459mA A Power dissipation,total All channels,TGC mode,no signal522570mW A

All channels,CW mode,no signal533575mW A POWER-DOWN MODES

Standby Mode PD(pin49)=high

IAVDD118mA A IDVDD 1.5mA A IAVDD28mA A Power dissipation104130mW A Power-down response time0.2μs C Power-up response time(5)PD to valid output(90%level)50μs C

Shut-Down Mode D2(PWR)=high

IAVDD1 1.5mA A IDVDD 1.5mA A IAVDD22mA A Power dissipation1935mW A THERMAL CHARACTERISTICS

Temperature range Ambient,operating–40+85°C

Thermal resistance,θJA22.5°C/W

Soldered pad;four-layer PCB

with thermal vias

Thermal resistance,θJC17.0°C/W

(4)Clamp enabled(D4=0).

(5)See Figure59of the Typical Characteristics.

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DEVICE INFORMATION

48474645444342

414039383736353433

VBL5IN5AVDD1IN6VBL6VBL7IN7VBL8IN8AVDD2VB2VB6VB4V REFH V REFL AVDD1

1234567

910111213141516

VBL1IN1AVDD1

IN2VBL2VBL3IN3VBL4IN4V CNTL AVDD2VB3VB1VB5V CM O U T 4

O U T 4

O U T 3

O U T 2

O U T 1

O U T 5

O U T 6

O U T 7

O U T 8

646362616059585756555417181920212223242526275352515049

2829303132

VCA8500

(GND)

PowerPAD TM

AVDD1

P D

C W 0

C W 1

C W 2

C W 3

C W 4

D _I N

C L K

D _O U T

R S T

D V D D

C W 5

C W 6

C W 7

C W 8

C W 9

VCA8500

SBOS390A–JANUARY 2008–REVISED MARCH 2008

RGC PACKAGE

QFN-64(TOP VIEW)

Table 1.TERMINAL FUNCTIONS

TERMINAL

PIN NO.

NAME I/O

DESCRIPTION

1VBL1LNA bias voltage (+2.4V);bypass with 0.1μF capacitor (min)2IN1I LNA input channel 13AVDD1+3.3V analog supply 4IN2I LNA input channel 2

5VBL2LNA bias voltage (+2.4V);bypass with 0.1μF capacitor (min)6VBL3LNA bias voltage (+2.4V);bypass with 0.1μF capacitor (min)7IN3I LNA input channel 3

8VBL4LNA bias voltage (+2.4V);bypass with 0.1μF capacitor (min)9IN4LNA input channel 4

10V CNTL I Attenuator control voltage input (all channels)11AVDD2+5V analog supply (VCA,CW)

12VB3Internal bias voltage (+4.2V);bypass with 0.1μF capacitor (min)13VB1Internal bias voltage (+2.4V);bypass with 2.2μF capacitor (1.0μF min)14VB5Internal bias voltage (+2.4V);bypass with 0.1μF capacitor (min)

15V CM Internal common-mode voltage (+1.65V);bypass with 0.1μF capacitor (min)16AVDD1+3.3V analog supply

17OUT4O PGA output channel 4(inverted)18

OUT4

O PGA output channel 4

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VCA8500

SBOS390A–JANUARY2008–REVISED MARCH2008 Table1.TERMINAL FUNCTIONS(continued)

TERMINAL

PIN https://www.doczj.com/doc/2516775070.html, I/O DESCRIPTION

19OUT3O PGA output channel3(inverted)

20OUT3O PGA output channel3

21OUT2O PGA output channel2(inverted)

22OUT2O PGA output channel2

23OUT1O PGA output channel1(inverted)

24OUT1O PGA output channel1

25OUT5O PGA output channel5(inverted)

26OUT5O PGA output channel5

27OUT6O PGA output channel6(inverted)

28OUT6O PGA output channel6

29OUT7O PGA output channel7(inverted)

30OUT7O PGA output channel7

31OUT8O PGA output channel8(inverted)

32OUT8O PGA output channel8

33AVDD1+3.3V analog supply

34V REFL Clamp reference level low,2.0V;bypass with0.1μF capacitor(min)

35V REFH Clamp reference level high,2.7V;bypass with0.1μF capacitor(min)

36VB4Internal bias voltage(+2.4V);bypass with0.1μF capacitor(min)

37VB6Internal bias voltage(+2.9V);bypass with0.1μF capacitor(min)

38VB2Internal bias voltage(+2.7V);bypass with0.1μF capacitor(min)

39AVDD2+5V analog supply(VCA,CW)

40IN8I LNA input channel8

41VBL8LNA bias voltage(+2.4V);bypass with0.1μF capacitor(min)

42IN7I LNA input channel7

43VBL7LNA bias voltage(+2.4V);bypass with0.1μF capacitor(min)

44VBL6I LNA bias voltage(+2.4V);bypass with0.1μF capacitor(min)

45IN6LNA input channel6

46AVDD1+3.3V analog supply

47IN5I LNA input channel5

48VBL5LNA bias voltage(+2.4V);bypass with0.1μF capacitor(min)

49PD I Power-down pin for standby mode;0=normal operation,1=power down

50CW0O CW channel0current output

51CW1O CW channel1current output

52CW2O CW channel2current output

53CW3O CW channel3current output

54CW4O CW channel4current output

55D_IN I Serial data input

56CLK I Clock input for serial interface

57D_OUT O Serial data output

58RST I Reset input;rising edge resets register to default values.

59DVDD+3.3V digital supply;connect to a low-noise analog supply plane(AVDD1)

60CW5CW channel5current output

61CW6CW channel6current output

62CW7CW channel7current output

63CW8CW channel8current output

64CW9CW channel9current output

PowerPAD must be connected to the analog ground of the printed circuit board;use this ground for —GND

bypass capacitor return ground.

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FUNCTIONAL BLOCK DIAGRAM

CLK RST D_OUT D_IN IN1

VBL1

IN2

VBL2

IN3

VBL3

CNTL

REFH REFL

VB1IN4

VBL4

IN5

VBL5

IN6

VBL6

IN7

VBL7

VB2VB3VB4VB5VB6

IN8

VBL8

VCA8500

SBOS390A–JANUARY 2008–REVISED MARCH 2008

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INPUT REGISTER BIT MAPS

VCA8500

SBOS390A–JANUARY

2008–REVISED MARCH 2008

BYTE #1BYTE #2BYTE #3

BYTE #4

BYTE #5

D0:D7D8:D11

D12:D15D16:D19

D20:D23D24:D27

D28:D31D32:D35

D36:D39Control

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

Table 2.Default Register Configuration

D7D6D5D4D3D2D1D00

Table 3.Byte 1—Control Byte Register Map

Table 4.Byte 2—First Data Byte

BIT #NAME DESCRIPTION

D8(LSB)DB1:1Channel 1,LSB of matrix control D9DB1:2Channel 1,matrix control D10DB1:3Channel 1,matrix control D11DB1:4Channel 1,MSB of matrix control D12DB2:1Channel 2,LSB of matrix control D13DB2:2Channel 2,matrix control D14DB2:3Channel 2,matrix control D15(MSB)

DB2:4

Channel 2;MSB of matrix control

Table 5.Byte 3—Second Data Byte

BIT #NAME DESCRIPTION

D16(LSB)DB3:1Channel 3,LSB of matrix control D17DB3:2Channel 3,matrix control D18DB3:3Channel 3,matrix control D19DB3:4Channel 3,MSB of matrix control D20DB4:1Channel 4,LSB of matrix control D21DB4:2Channel 4,matrix control D22DB4:3Channel 4,matrix control D23(MSB)

DB4:4

Channel 4,MSB of matrix control

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VCA8500

SBOS390A–JANUARY 2008–REVISED MARCH 2008

Table 6.Byte 4—Third Data Byte

BIT #NAME DESCRIPTION

D24(LSB)DB5:1Channel 5,LSB of matrix control D25DB5:2Channel 5,matrix control D26DB5:3Channel 5,matrix control D27DB5:4Channel 5,MSB of matrix control D28DB6:1Channel 6;LSB of matrix control D29DB6:2Channel 6,matrix control D30DB6:3Channel 6,matrix control D31(MSB)

DB6:4

Channel 6,MSB of matrix control

Table 7.Byte 5—Fourth Data Byte

BIT #NAME DESCRIPTION

D32(LSB)DB7:1Channel 7,LSB of matrix control D33DB7:2Channel 7,matrix control D34DB7:3Channel 7,matrix control D35DB7:4Channel 7,MSB of matrix control D36DB8:1Channel 8;LSB of matrix control D37DB8:2Channel 8,matrix control D38DB8:3Channel 8,matrix control D39(MSB)

DB8:4

Channel 8,MSB of matrix control

Table 8.Clamp Level and LPF Bandwidth Setting

NAME SETTING FUNCTION

D3=0Bandwidth set to 15MHz (default)BW D3=1Bandwidth set to 10MHz

D4=0Clamps the output signal at 1.7V PP on each PGA output channel (default)CL

D4=1

Clamp transparent (disabled)

Table 9.PGA Gain Setting

PG1PG0FUNCTION

00Set PGA gain to 20dB (default)01Set PGA gain to 25dB 10Set PGA gain to 27dB 1

Set PGA gain to 30dB

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(T o Other Channels)

VCA8500 SBOS390A–JANUARY2008–REVISED MARCH2008

Table10.CW Switch Matrix Control for Each Channel

DBn:4DBn:1

(MSB)DBn:3DBn:2(LSB)LNA Input Channel Directed To:

0000Output CW0

0001Output CW1

0010Output CW2

0011Output CW3

0100Output CW4

0101Output CW5

0110Output CW6

0111Output CW7

1000Output CW8

1001Output CW9

1010Connected to AVDD2;channel disabled

1011Connected to AVDD2;channel disabled

1100Connected to AVDD2;channel disabled

1101Connected to AVDD2;channel disabled

1110Connected to AVDD2;channel disabled

1111Connected to AVDD2;channel disabled

Figure1.Basic CW Cross-Point Switch Matrix Configuration

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SERIAL DIGITAL INTERFACE (SDI)

TIMING INFORMATION

SERIAL PORT TIMING TABLE

VCA8500

SBOS390A–JANUARY 2008–REVISED MARCH 2008

?All writes and reads are five bytes at a time.Each byte consists of 8bits,for a total instruction set of 40bits.?Data are latched on the falling edge of CLK.

?Separate write (DIN)and read data (DOUT)lines.

?Reads follow the same bitstream pattern seen in the write cycle.?Reads extract data from the FIFO buffer,not the latched register.

?DOUT data are continuously available and do not need to be enabled with a read cycle.Selecting a read cycle in the control register only prevents latching of data.The control register remains latched.

The Reset pin (RST)must be low in order to allow the register to update with new data.RST can be held low permanently.To initiate a reset cycle,pull the RST pin high for at least 100ns.

NOTE:This figure shows timing example for one data byte.A full register update cycle requires all five bytes (that is,40bits).

PARAMETER

DESCRIPTION MIN TYP

MAX

UNIT t 1Serial CLK period 100ns t 2Serial CLK HIGH time 40ns t 3Serial CLK LOW time

40ns t 4Data hold time 5ns t 5Data setup time 5ns RST

Reset pulse (L -H -L)

100

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TYPICAL CHARACTERISTICS

5550454035302520151050510

-- 1.2

G a i n (d B )

V (V)

CNTRL 00.10.2 1.11.00.90.70.80.50.60.40.3

0.50

0.25

0.50

-- 1.2

G a i n (d B )

V (V)

CNTRL 0 1.11.00.90.70.80.50.60.40.30.20.1

5550454035302520151050510

-- 1.2

G a i n (d B )

V (V)

CNTRL 0.0 1.11.00.90.70.80.50.60.40.3

0.10.2 1.501.251.000.75

0.500.2500.250.500.751.001.251.50

------ 1.2

G a i n E r r o r (d B )

V (V)

CNTRL 0

1.11.00.90.70.80.50.60.40.3

0.20.15550454035302520151050510

-- 1.2

G a i n (d B )

V (V)

CNTRL 0

1.11.0

0.90.70.80.50.60.40.30.20.10.500.450.40

0.350.300.250.200.150.100.050 1.2

G a i n M a t c h i

n g (d B )

V (V)CNTRL 0

1.11.00.90.70.80.50.60.40.30.20.1VCA8500

SBOS390A–JANUARY 2008–REVISED MARCH 2008

All specifications at T A =+25°C,AVDD2=5.0V,AVDD1=DVDD =3.3V;single-ended,ac-coupled (1μF)input configuration to the preamp (LNA),f IN =5MHz,V CNTL =1.0V,clamp disabled (CL =1),LPF =15MHz,and R LOAD =1k ?on each output to

ground,unless otherwise noted.

GAIN vs V CNTRL (at PGA =X)

GAIN ERROR vs V CNTRL

Figure 2.

Figure 3.

GAIN vs V CNTRL OVER TEMPERATURE GAIN ERROR DRIFT vs V CNTRL

Figure 4.

Figure 5.

GAIN vs V CNTRL OVER FREQUENCY

GAIN MATCHING vs V CNTRL

Figure 6.Figure 7.

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300025002000

150010005000

U n i t s

D Gain (dB)

-1.001.05

-0.82-0.63-0.44-0.26-0.070.110.300.490.670.860.950.770.580.390.210.02-0.16-0.35-0.54-0.72-0.9

13000

25002000

150010005000

U n i t s

D Gain (dB)

-1.001.05

-0.82-0.63-0.44-0.26-0.070.110.300.490.670.860.950.770.580.390.210.02-0.16-0.35-0.54-0.72-0.91

2000180016001400

120010008006004002000

U n i t s

D Gain (dB)-0.810.91-0.68-0.55-0.42-0.28-0.150.120.250.380.650.780.850.710.580.320.180.05-0.22-0.35-0.48-0.62-0.75-0.08-0.020.450.98

0.52

2500

2000

1500

1000

500

C W O u t p u t s

Transconductance (mA/V)

15.0

17.8

15.2

15.4

18.017.4

17.6

17.2

16.2

15.8

16.6

17.0

15.6

16.0

16.4

16.

16.75

16.50

16.25

16.00

15.75

15.50

T r a n s c o n d u c t a n c e (m A /V )

T emperature (C)

°85

-40

603510-1500.10.20.30.40.50.60.70.80.91.01.11.21.31.4

--------------O u t p u t O f f s e t (m V )

T emperature (C)

°85

-4060

3510-15VCA8500

SBOS390A–JANUARY 2008–REVISED MARCH 2008

TYPICAL CHARACTERISTICS (continued)

GAIN MATCH AT V CNTRL =0.1V

GAIN MATCH AT V CNTRL =0.6V

Figure 8.

Figure 9.GAIN MATCH AT V CNTRL =1.2V

CW ACCURACY

Figure 10.

Figure 11.

TRANSCONDUCTANCE vs TEMPERATURE

OUTPUT OFFSET vs TEMPERATURE

Figure 12.Figure 13.

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1701601501401301201101009080706050403020100

T G C C u r r e n t (m A )

T emperature (C)°

-40

603510-15

90858075706560555045403530252015105085

C W C u r r e n t (m A )

T emperature (C)

°-40

-15

560550

540

530520510500490

T o t a l P o w e r (V )

T emperature (C)

°85

-40

-15

5045403530252015105051015202530

------100

G a i n (d B )

Frequency (MHz)

0.110

504540353025201510505101520

----100

G a i n (d B )

Frequency (MHz)

0.1

250

200

150

100

1.2

N o i s e (n V /)

?H z

V (V)

CNTRL 0

0.20.1 1.11.00.90.30.40.50.60.70.8VCA8500

SBOS390A–JANUARY 2008–REVISED MARCH 2008

TYPICAL CHARACTERISTICS (continued)

TGC CURRENT vs TEMPERATURE

CW CURRENT vs TEMPERATURE

Figure 14.

Figure 15.

FREQUENCY RESPONSE vs V CNTRL AT PGA =20dB

TOTAL POWER vs TEMPERATURE

(LPF =15MHz and 10MHz)

Figure 16.

Figure 17.

FREQUENCY RESPONSE vs V CNTRL AT PGA =30dB

(LPF =15MHz and 10MHz)

OUTPUT-REFERRED NOISE vs V CNTRL

Figure 18.Figure 19.

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250200

150

100

0 1.2

N o i s e (n V /)

?H z V (V)

CNTRL 0

0.20.1

1.11.00.90.30.40.50.60.70.812011010090

8070605040302010

1.2

N o i s e (n V /)

?H z V (V)

CNTRL 0

0.2

0.1 1.11.00.90.30.40.50.60.70.812011010090

80706050403020100 1.2

N o i s e (n V /)

?H z V (V)

CNTRL 0

0.2

0.1 1.11.00.90.30.40.50.60.70.8 4.03.8

3.63.43.23.02.82.62.42.22.0

C u r r e n t N o i s e (p A /)

?H z Frequency (MHz)

101500140013001200110010009008007006005004003002001000

N o i s e

(n V /)

?H z Frequency (MHz)

6.56.05.55.04.54.03.53.02.52.01.51.00.50

N o i s e

(n V /)

?H z Frequency (MHz)1

VCA8500

SBOS390A–JANUARY 2008–REVISED MARCH 2008

TYPICAL CHARACTERISTICS (continued)

OUTPUT-REFERRED NOISE vs V CNTRL

INPUT-REFERRED NOISE vs V CNTRL

Figure 20.

Figure 21.

INPUT-REFERRED NOISE vs V CNTRL

CURRENT NOISE vs FREQUENCY OVER R SOURCE

Figure 22.

Figure 23.

OUTPUT-REFERRED NOISE vs FREQUENCY OVER R S

INPUT-REFERRED NOISE vs FREQUENCY OVER R S

Figure 24.Figure 25.

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3.53.0

2.52.01.51.00.5020

N o i s e F i g u r e (d B )

Frequency (MHz)1

1.000.95

0.900.850.800.750.70

30dB

N o i s e (n V /)

?H z Gain Setting (PGA)

20dB

25dB

27dB

12k

10k

8k 6k 0100M

M a g n i t u d e ()

W 10080

6040

100P h a s e ()

°-80-20

-40-604k 2k Frequency (Hz)

100k

10M

1.301.281.261.241.221.201.181.161.141.121.101.081.061.041.021.00

N o i s e (n V /)

?H z Frequency (MHz)

0.1

101.0

-4550

60657075

------10

D i s t o r

t i o n (d B c )

Frequency (MHz)

-4550

6065

------10

D i s t o r t

i o n (d B c )

Frequency (MHz)

VCA8500

SBOS390A–JANUARY 2008–REVISED MARCH 2008

TYPICAL CHARACTERISTICS (continued)

NOISE FIGURE vs FREQUENCY OVER R S

INPUT-REFERRED NOISE

Figure 26.

Figure 27.

INPUT-REFERRED NOISE vs FREQUENCY

MAGNITUDE AND PHASE vs FREQUENCY

Figure 28.

Figure 29.

2ND HARMONIC vs FREQUENCY

3RD HARMONIC vs FREQUENCY

Figure 30.Figure 31.

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4550

60657075

------- 1.2

D i s t o r t i o n (d B )

V (V)

CNTRL 0.6

1.1

1.0

0.90.8

0.7

-------4550

55606570

1.2

D i s t o r t i o n (d B c )

V (V)

CNTRL 0.6

1.1

1.0

0.90.8

0.7

-------4550

5560657075

1.2

D i s t o r

t i o n (d B c )

V (V)

CNTRL 0.6

1.1

1.0

0.90.8

0.7

-------4550

5560657075

1.2

D i s t o

r t i o n (d B )

V (V)

CNTRL 0.6

1.1

1.0

0.90.8

0.7

-------4550

5560

657075

1.2

D i s t o

r t i o n (d B )

V (V)

CNTRL 0.6

1.1

1.0

0.90.8

0.7

-------4550

5560657075

1.2

D i s t o

r t i o n (d B )

V (V)

CNTRL 0.6

1.1

1.0

0.90.8

0.7

VCA8500

SBOS390A–JANUARY 2008–REVISED MARCH 2008

TYPICAL CHARACTERISTICS (continued)

2ND HARMONIC vs V CNTRL OVER PGA GAIN

3RD HARMONIC vs V CNTRL OVER PGA GAIN

Figure 32.

Figure 33.

2ND HARMONIC vs V CNTRL OVER FREQUENCY

Figure 34.

Figure 35.

2ND HARMONIC vs V CNTRL OVER FREQUENCY

Figure 36.Figure 37.

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-------4550

55606570

1.2

D i s t o r t i o n (d B )

V (V)

CNTRL 0.6

1.1

1.0

0.90.8

0.7

-------4550

55606570

1.2

D i s t o r t i o n (d B )

V (V)

CNTRL 0.6

1.1

1.0

0.90.8

0.7

-------4550

5560657075

1.2

D i s t o r t i o n (d B )

V (V)

CNTRL

0.6

1.1

1.0

0.9

0.8

0.7

-------4550

60657075

1.2

D i s t o r t i o n (d B )

V (V)

CNTRL 0.6

1.1

1.0

0.90.8

0.7

-------4550

5560

6570

1500

D i s t o r t i o n (d B

)

Output Resistor Load ()

W 750

1250

1000

-------45

55606570

1500

D i s t o r t i o n (d B )

Output Resistor Load ()

W 750

1250

1000

VCA8500

SBOS390A–JANUARY 2008–REVISED MARCH 2008

TYPICAL CHARACTERISTICS (continued)

3RD HARMONIC vs V CNTRL OVER FREQUENCY

Figure 38.

Figure 39.

3RD HARMONIC vs V CNTRL OVER FREQUENCY

Figure 40.

Figure 41.

DISTORTION vs R LOAD

(Clamp Disabled)

(Clamp Enabled)

Figure 42.Figure 43.

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-------4550

556065

7075

D i s t o r t i o n (d B )

Frequency (MHz)

-------4550

60657075

D i s t o r t i o n (d B )

PGA Gain (dB)

-------4550

5560657075

2.0

D i

s t o r t i o n (d B )

V (V )

OUT PP 1.0

1.4

1.2

1.8

1.6

10010

20304050607080

--------- 5.10

M a g n i t u d e (

d B m )

Frequency (MHz)

4.90 4.944.92 4.984.96

5.00 5.02 5.04 5.06 5.08-5055

6065707580

------ 1.2C r o s s t a

l k (d B c )

V (V)

CNTRL 0.5

0.7

0.6

0.9

0.8

1.0

1.1-5055

606570

7580

------ 1.2

C r o s s t a l

k (d B c )

V (V)

CNTRL 0.50.70.60.90.8 1.0 1.10.4VCA8500

SBOS390A–JANUARY 2008–REVISED MARCH 2008

TYPICAL CHARACTERISTICS (continued)

DISTORTION vs FREQUENCY

DISTORTION vs PGA GAIN

Figure 44.

Figure 45.

INTERMODULATION DISTORTION

DISTORTION vs V OUT ,PEAK-TO-PEAK

(4.99MHz and 5.01MHz)

Figure 46.

Figure 47.

CROSSTALK vs V CNTRL

Figure 48.Figure 49.

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