P
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U
C
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P
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I
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F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1
F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
https://www.doczj.com/doc/2c11449052.html, SPRS742C–JUNE2011–REVISED JANUARY2012
Concerto Microcontrollers
1F28M35x(Concerto?)MCUs
1.1Features
?Master Subsystem—ARM?Cortex?-M3?Control Subsystem—TMS320C28x?32-Bit
CPU
–100MHz
–150MHz
–Embedded Memory
–Embedded Memory
?Up to512KB Flash(ECC)
?Up to512KB Flash(ECC)?Up to32KB RAM(ECC/Parity)
?Up to36KB RAM(ECC/Parity)?Up to64KB Shared RAM
?Up to64KB Shared RAM
?2KB IPC Message RAM
?2KB IPC Message RAM –5Universal Asynchronous
Receiver/Transmitters(UARTs)–IEEE-754Single-Precision Floating-Point
Unit(FPU)
–4Synchronous Serial Interfaces(SSIs)/
Serial Peripheral Interface(SPI)–Viterbi,Complex Math,CRC Unit(VCU)–2Inter-integrated Circuits(I2Cs)–Serial Communications Interface(SCI)
–Universal Serial Bus On-the-Go(USB-OTG)+–Serial Peripheral Interface(SPI) PHY–Inter-integrated Circuit(I2C)–10/100ENET1588MII–6-Channel Direct Memory Access(DMA)
–2Controller Area Networks(CANs)–9Enhanced Pulse Width Modulator(ePWM)–32-Channel Direct Memory Access(μDMA)Modules
–Dual Security Zones(128-Bit Password per?18Outputs(16High-Resolution) Zone)–632-Bit Enhanced Capture(eCAP)Modules –External Peripheral Interface(EPI)–332-Bit Enhanced Quadrature Encoder
–Micro Cyclic Redundancy Check(μCRC)(eQEP)Modules
Module–Multi-Channel Buffered Serial Port(McBSP)–4General-Purpose Timers–One Security Zone(128-Bit Password)
–2Watchdog Timer Modules–332-Bit Timers
–Endianness:Little Endian–Endianness:Little Endian
?Clocking
–On-chip Crystal Oscillator/External Clock?Analog Subsystem
Input–Dual12-Bit Analog-to-Digital Converters –Dynamic PLL Ratio Changes Supported(ADCs)
? 1.2-V Digital,1.8-V Analog,3.3-V I/O Design–Up to2.88MSPS
–Up to20Channels
?Interprocessor Communications(IPC)–4Sample-and-Hold(S/H)Circuits –32Handshaking Channels–Up to6Comparators With10-Bit
–4Channels Generate IPC Interrupts Digital-to-Analog Converter(DAC)
–Can be Used to Coordinate Transfer of Data–On-chip Temperature Sensor Through IPC Message RAMs
?Package
?Up to72Individually Programmable,–144-Pin RFP PowerPAD?Thermally Multiplexed GPIO Pins Enhanced Thin Quad Flatpack(HTQFP)
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C28x,PowerPAD,C28x,C2000,Piccolo,Delfino,TMS320C2000,XDS are trademarks of Texas Instruments.
Cortex is a trademark of ARM Limited.
F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1
F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
SPRS742C–JUNE2011–REVISED https://www.doczj.com/doc/2c11449052.html,
1.2Description
The Concerto?family is a multi-core system-on-chip microcontroller(MCU)with independent
communication and real-time control subsystems.The F28M35x is the first series in the Concerto family.
The communications subsystem is based on the industry-standard32-bit ARM?Cortex?-M3CPU and
features a wide variety of communication peripherals,including Ethernet1588,USB OTG with PHY,CAN,
UART,SSI,I2C,and an external interface.
The real-time control subsystem is based on TI’s industry-leading proprietary32-bit C28x?Floating-Point
CPU and features the most flexible and high-precision control peripherals,including ePWMs with fault
protection,and encoders and captures—all as implemented by TI’s C2000?Piccolo?and Delfino?
families.In addition,the C28-CPU has been enhanced with the addition of the Viterbi,Complex Math,
CRC Unit(VCU)instruction accelerator that implements efficient Viterbi,Complex Arithmetic,16-bit FFTs
and CRC algorithms.
A high-speed analog subsystem and supplementary RAM memory is shared,along with on-chip voltage
regulation and redundant clocking circuitry.Safety considerations also include Error Correction Code
(ECC),Parity,and Code Secure Memory,as well as documentation to assist with system-level industrial
safety certification.
PRODUCT PREVIEW
P R O D U C T P R E V I E W
F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
https://www.doczj.com/doc/2c11449052.html,
SPRS742C –JUNE 2011–REVISED JANUARY 2012
1.3Functional Block Diagram
Figure 1-1.Functional Block Diagram
F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1
F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
SPRS742C–JUNE2011–REVISED https://www.doczj.com/doc/2c11449052.html, 1F28M35x(Concerto?)MCUs........................13Device Pins (65)
1.1Features..............................................1 3.1Pin Assignments (65)
1.2Description...........................................2 3.2Terminal Functions (66)
4Device Operating Conditions (85)
1.3Functional Block Diagram (3)
4.1Absolute Maximum Ratings (85)
Revision History (5)
2Device Overview.......................................10 4.2Recommended Operating Conditions.. (85)
2.1Device Characteristics..............................11 4.3Electrical Characteristics (86)
2.2Memory Maps......................................135Peripheral Information and Timings (87)
2.3Master Subsystem..................................23 5.1Master Subsystem Peripherals (87)
2.4Control Subsystem.................................28 5.2Control Subsystem Peripherals.. (88)
2.5Analog Subsystem..................................33 5.3Analog/Shared Peripherals. (91)
2.6Master Subsystem NMIs...........................36 5.4Current Consumption. (97)
5.5Power Sequencing (99)
2.7Control Subsystem NMIs (36)
6Device and Documentation Support (100)
2.8Resets (38)
6.1Device Support (100)
2.9Master Subsystem Clocking (43)
2.10Control Subsystem Clocking.......................46 6.2Documentation Support (101)
2.11Analog Subsystem Clocking........................48 6.3Community Resources. (101)
7Mechanical Packaging and Orderable
2.12Shared Resources Clocking (49)
Information (102)
PRODUCT PREVIEW
2.13GPIOs and Other Pins (49)
7.1Packaging Information (102)
P R O D U C T P R E V I E W
F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
https://www.doczj.com/doc/2c11449052.html,
SPRS742C –JUNE 2011–REVISED JANUARY 2012
Revision History
NOTE:Page numbers for previous revisions may differ from page numbers in the current version.
This data sheet revision history highlights the technical changes made to the SPRS742B device-specific data sheet to make it an SPRS742C revision.
Scope:
See table below.
LOCATION ADDITIONS,DELETIONS,AND MODIFICATIONS
Section 1.1
Features:?Changed "Up to 74Individually Programmable,Multiplexed GPIO Pins"to "Up to 72Individually
Programmable,Multiplexed GPIO Pins"Figure 1-1Updated Functional Block Diagram
Table 2-1
Hardware Features:?Updated S and Q "Temperature options"rows ?Added footnote about availability of Q temperature range on F28M35Mxxx1devices ?Added footnote about availability of Q temperature range on F28M35ExxC1and F28M35ExxB1
devices Section 2.2.2Master Subsystem Memory Map:?Added "MPU is not available on silicon revision 0devices"NOTE
Table 2-9Master Subsystem Flash,ECC,OTP,Boot ROM:?04000000–07FF FFFF:Updated "Master Subsystem Flash,ECC,OTP,Boot ROM"column Table 2-10Master Subsystem RAMs:?24000000–27FF FFFF:Updated "Master Subsystem RAMs"column
Table 2-13Cortex ?-M3Private Bus:?E0000000–E0000FFF:Updated "Cortex ?-M3Private Bus"column and "Size (Bytes)"column Section 2.3.1Cortex ?-M3CPU:?Added "MPU is not available on silicon revision 0devices"NOTE Figure 2-1Updated "Master Subsystem"figure
Table 2-14Interrupts from NVIC to Cortex ?-M3:?Interrupt Number 89:Changed Vector Number from "1–5"to "105"Figure 2-2Updated "Control Subsystem"figure
Section 2.4.2
C28x Peripheral Interrupt Expansion (PIE):?Changed "On the F28M35x,70of the possible 96interrupts are used"to "On the F28M35x,66of the
possible 96interrupts are used"Figure 2-3Updated "Analog Subsystem"figure Section 2.8Resets:?Added list of requirements on XRS pin Table 2-17
Master Subsystem Boot Mode Selection:?Added "PF2_GPIO34(BOOT_3)"column ?Added footnote Figure 2-7Updated "C28x Clocks and Low-Power Modes"figure
Section 2.10.3C28x Standby Mode:?Updated "In Standby Mode,the C28x processor stops executing instructions ..."paragraph Section 2.13GPIOs and Other Pins:?Updated "Most of the I/O pins of the Concerto ?MCU ..."paragraph Section 2.13.1Updated "GPIO_MUX1"section Figure 2-8Updated "GPIOs and Other Pins"figure Figure 2-9Updated "GPIO_MUX1Block"figure
Figure 2-10
Updated "GPIO_MUX1Pin Mapping Through Register Set A"figure
PRODUCT PREVIEW F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1
F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
SPRS742C–JUNE2011–REVISED https://www.doczj.com/doc/2c11449052.html, LOCATION ADDITIONS,DELETIONS,AND MODIFICATIONS
Table2-21GPIO_MUX1Pin Assignments(M3Primary Modes):
?PF6_GPIO38:
–Removed CCP1from"M3Primary Mode1"column
–Removed MII_RXD2from"M3Primary Mode3"column
–Removed U1RTS from"M3Primary Mode10"column
?PG6_GPIO46:
–Removed MII_TXCK from"M3Primary Mode3"column
–Removed U1RI from"M3Primary Mode10"column
Table2-22GPIO_MUX1Pin Assignments(M3Alternate Modes):
?PF0_GPIO32:Added TRACED2to"M3Alternate Mode14"column
?PF1_GPIO33:Added TRACED3to"M3Alternate Mode14"column
?PF2_GPIO34:Added TRACECLK to"M3Alternate Mode14"column
?PF3_GPIO35:Added TRACED0to"M3Alternate Mode14"column
?PG3_GPIO43:Added TRACED1to"M3Alternate Mode14"column
Table2-23GPIO_MUX1Pin Assignments(C28x Peripheral Modes):
?PA5_GPIO5:Changed MFSRA O to MFSRA in"C28x Peripheral Mode2"column
?PA7_GPIO7:Changed MCLKRA O to MCLKRA in"C28x Peripheral Mode2"column
?PD0_GPIO16:Changed SPISIMOA O to SPISIMOA in"C28x Peripheral Mode1"column
?PD1_GPIO17:Changed SPISOMIA O to SPISOMIA in"C28x Peripheral Mode1"column
?PD2_GPIO18:Changed SPICLKA O to SPICLKA in"C28x Peripheral Mode1"column
?PD3_GPIO19:Changed SPISTEA O to SPISTEA in"C28x Peripheral Mode1"column
?PD6_GPIO22:Changed EQEP1S O to EQEP1S in"C28x Peripheral Mode1"column
?PD6_GPIO22:Changed MCLKXA O to MCLKXA in"C28x Peripheral Mode2"column
?PD7_GPIO23:Changed EQEP1I O to EQEP1I in"C28x Peripheral Mode1"column
?PD7_GPIO23:Changed MFSXA O to MFSXA in"C28x Peripheral Mode2"column
?PE2_GPIO26:Changed EQEP2I O to EQEP2I in"C28x Peripheral Mode2"column
?PE3_GPIO27:Changed EQEP2S O to EQEP2S in"C28x Peripheral Mode2"column
?PF0_GPIO32:Changed SDAAOC to I2CASDA in"C28x Peripheral Mode1"column
?PF1_GPIO33:Changed SCLAOC to I2CASCL in"C28x Peripheral Mode1"column
?PF6_GPIO38:Removed GPIO38from"C28x Peripheral Mode0"column
?PF7_GPIO39:Removed GPIO39from"C28x Peripheral Mode0"column
?PG4_GPIO44:Removed GPIO44from"C28x Peripheral Mode0"column
?PG6_GPIO46:Removed GPIO46from"C28x Peripheral Mode0"column
?PH4_GPIO52:Changed EQEP1S O to EQEP1S in"C28x Peripheral Mode1"column
?PH5_GPIO53:Changed EQEP1I O to EQEP1I in"C28x Peripheral Mode1"column
?PH6_GPIO54:Changed SPISIMOA O to SPISIMOA in"C28x Peripheral Mode1"column
?PH7_GPIO55:Changed SPISOMIA O to SPISOMIA in"C28x Peripheral Mode1"column
?PJ0_GPIO56:Changed SPICLKA O to SPICLKA in"C28x Peripheral Mode1"column
?PJ0_GPIO56:Changed EQEP3S O to EQEP3S in"C28x Peripheral Mode3"column
?PJ1_GPIO57:Changed SPISTEA O to SPISTEA in"C28x Peripheral Mode1"column
?PJ1_GPIO57:Changed EQEP3I O to EQEP3I in"C28x Peripheral Mode3"column
?PJ2_GPIO58:Changed MCLKRA O to MCLKRA in"C28x Peripheral Mode1"column
?PJ3_GPIO59:Changed MFSRA O to MFSRA in"C28x Peripheral Mode1"column
?PJ7_GPIO63/XCLKIN:Changed GPIO63/XCLKIN to GPIO63in"C28x Peripheral Mode0"column
?PC0_GPIO64:Removed GPIO64from"C28x Peripheral Mode0"column
?PC1_GPIO65:Removed GPIO65from"C28x Peripheral Mode0"column
?PC2_GPIO66:Removed GPIO66from"C28x Peripheral Mode0"column
?PC3_GPIO67:Removed GPIO67from"C28x Peripheral Mode0"column
Section2.13.2GPIO_MUX2:
?"Peripheral Modes0,1,2,and3are chosen by..."paragraph:
–Changed GPIO130to GPIO194
P R O D U C T P R E V I E W
F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
https://www.doczj.com/doc/2c11449052.html,
SPRS742C –JUNE 2011–REVISED JANUARY 2012
LOCATION ADDITIONS,DELETIONS,AND MODIFICATIONS
Table 2-24
GPIO_MUX2Pin Assignments (C28x Peripheral Modes):?Changed GPIO128to GPIO192?Changed GPIO129to GPIO193?Changed GPIO130to GPIO194?Changed GPIO131to GPIO195?Changed GPIO132to GPIO196?Changed GPIO133to GPIO197?Changed GPIO134to GPIO198?Changed GPIO135to GPIO199
Figure 2-11Updated "Pin Muxing on AIO_MUX1,AIO_MUX2,and GPIO_MUX2"figure Figure 3-1
144-Pin RFP PowerPAD ?HTQFP (Top View):?Pin 91:Changed signal name from V DD12to NC ?Pin 109:Changed signal name from GPIO135/COMP5OUT to GPIO199/COMP5OUT ?Pin 110:Changed signal name from GPIO134to GPIO198?Pin 111:Changed signal name from GPIO133/COMP4OUT to GPIO197/COMP4OUT
?Pin 112:Changed signal name from GPIO132/COMP3OUT to GPIO196/COMP3OUT ?Pin 140:Changed signal name from GPIO128to GPIO192?Pin 141:Changed signal name from GPIO129/COMP1OUT to GPIO193/COMP1OUT ?Pin 142:Changed signal name from GPIO130/COMP6OUT to GPIO194/COMP6OUT ?Pin 143:Changed signal name from GPIO131/COMP2OUT
to GPIO195/COMP2OUT
Table 3-1
Terminal Functions:?Changed "ADC 1Inputs,Analog Comparator Inputs,AIO Group 1"signals group title to "ADC 1
Analog Power,Ground,Reference Inputs,Analog Comparator Inputs,DAC Inputs,AIO Group 1"?Changed "Analog,Digital,and I/O Power"signals group title to "Digital Logic Power Pins for I/Os,
Flash,USB,and Internal Oscillators"?"ADC 1Analog Power,Ground,Reference Inputs,Analog Comparator Inputs,DAC Inputs,AIO
Group 1"signals group:
–Moved V DDA1(pin 119)from "Digital Logic Power Pins for I/Os,Flash,USB,and Internal
Oscillators"signals group to "ADC 1Analog Power,Ground,Reference Inputs,Analog Comparator Inputs,DAC Inputs,AIO Group 1"signals group
–"ADC1V REFLO ,V SSA1"(pin 118):Updated DESCRIPTION ?Changed "ADC 2Inputs,Analog Comparator Inputs,AIO Group 2"signals group title to "ADC 2
Analog Power,Ground,Reference Inputs,Analog Comparator Inputs,DAC Inputs,AIO Group 2"?"ADC 2Analog Power,Ground,Reference Inputs,Analog Comparator Inputs,DAC Inputs,AIO
Group 2"signals group:
–Moved V DDA2(pin 134)from "Digital Logic Power Pins for I/Os,Flash,USB,and Internal
Oscillators"signals group to "ADC 2Analog Power,Ground,Reference Inputs,Analog Comparator Inputs,DAC Inputs,AIO Group 2"signals group
–"ADC2V REFLO ,V SSA2"(pin 135):Updated DESCRIPTION ?"Analog Comparator Results (Digital)and GPIO Group 2(C28x Access Only)"signals group:
–Pin 140:Changed signal name from GPIO128to GPIO192.Updated DESCRIPTION.–Pin 141:Changed signal name from GPIO129to GPIO193.Updated DESCRIPTION.–Pin 142:Changed signal name from GPIO130to GPIO194.Updated DESCRIPTION.–Pin 143:Changed signal name from GPIO131to GPIO195.Updated DESCRIPTION.–Pin 112:Changed signal name from GPIO132to GPIO196.Updated DESCRIPTION.–Pin 111:Changed signal name from GPIO133to GPIO197.Updated DESCRIPTION.–Pin 110:Changed signal name from GPIO134to GPIO198.Updated DESCRIPTION.–Pin 109:Changed signal name from GPIO135to GPIO199.Updated DESCRIPTION.
F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1
F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
SPRS742C–JUNE2011–REVISED https://www.doczj.com/doc/2c11449052.html, LOCATION ADDITIONS,DELETIONS,AND MODIFICATIONS
Table3-1Terminal Functions(continued):
?"GPIO Group1and Peripheral Signals"group:
–Pin9:Updated"I/O/Z"value and DESCRIPTION of M_SSI0RX
–Pin14:
?Changed M_MII_RXD1to M_MIIRXD1
?Updated DESCRIPTION of M_U1RI
–Pin30:Changed M_EPIOS23to M_EPI0S23
–Pin26:Updated DESCRIPTION of M_SSI1CLK
–Pin65:Updated DESCRIPTION of M_U1RI
–Pin45:Updated DESCRIPTION of M_SSI1RX
–Pin104:
?Added M_TRACED2signal
?Changed C_SDAA to C_I2CASDA
–Pin103:
?Added M_TRACED3signal
?Changed C_SCLA to C_I2CASCL
–Pin82:
?Updated DESCRIPTION of PF2_GPIO34
?Added M_TRACECLK signal
–Pin81:Added M_TRACED0signal
–Pin69: PRODUCT PREVIEW
?Updated DESCRIPTION of PF6_GPIO38
?Removed M_CCP1
?Removed M_MIIRXD2
?Removed M_U1RTS
–Pin78:Added M_TRACED1signal
–Changed"PF7_GPIO44"to"PG4_GPIO44"
–Pin70:
?Updated DESCRIPTION of PG6_GPIO46
?Removed M_MIITCK
?Removed M_U1RI
–Pin52:Added M_CCP5signal
–Pin36:Updated DESCRIPTION of C_EQEP1A
–Pin46:Changed M_USB0FLT to M_USB0PFLT
–Pin56:Updated DESCRIPTION of M_MIICRS
–Pin97:Added M_XCLKIN signal
?"Clocks"signals group:
–Pin93(X1):
?Updated DESCRIPTION
?Added reference to new"Input Clock Configurations"figure(Figure3-2)
–Pin95(X2):Added reference to new"Input Clock Configurations"figure(Figure3-2)
–Moved V SSOSC(pin94)from"Analog,Digital,and I/O Power"signals group to"Clocks"signals
group
–Pin94(V SSOSC):
?Updated DESCRIPTION
?Added reference to new"Input Clock Configurations"figure(Figure3-2)
?"Boot Pins"signals group:
–BOOT_2:Changed"see PG3_GPIO35"to"see PF3_GPIO35"
–Added BOOT_3signal
?Added"ITM Trace(ARM?Instrumentation Trace Macrocell)"signals group
?Changed"Analog,Digital,and I/O Power"signals group title to"Digital Logic Power Pins for I/Os,
Flash,USB,and Internal Oscillators"
P R O D U C T P R E V I E W
F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
https://www.doczj.com/doc/2c11449052.html,
SPRS742C –JUNE 2011–REVISED JANUARY 2012
LOCATION ADDITIONS,DELETIONS,AND MODIFICATIONS
Table 3-1
Terminal Functions (continued):?"Digital Logic Power Pins for I/Os,Flash,USB,and Internal Oscillators"signals group:
–Moved V DDA1(pin 119)from "Digital Logic Power Pins for I/Os,Flash,USB,and Internal
Oscillators"signals group to "ADC 1Analog Power,Ground,Reference Inputs,Analog Comparator Inputs,DAC Inputs,AIO Group 1"signals group
–Moved V DDA2(pin 134)from "Digital Logic Power Pins for I/Os,Flash,USB,and Internal
Oscillators"signals group to "ADC 2Analog Power,Ground,Reference Inputs,Analog Comparator Inputs,DAC Inputs,AIO Group 2"signals group
–Moved V SSOSC (pin 94)from "Digital Logic Power Pins for I/Os,Flash,USB,and Internal
Oscillators"signals group to "Clocks"signals group
?Added "Digital Logic Power Pins (Analog Subsystem)"signals group title ?Added "Digital Logic Power Pins (Master and Control Subsystems)"signals group title ?"Digital Logic Power Pins (Master and Control Subsystems)"signals group:
–Pin 91:Changed V DD12to NC and move to new "No Connect Pins"signals group –V SS (PWR PAD):Updated DESCRIPTION ?Added "Digital Logic Ground (Analog,Master,and Control Subsystems)"signals group title ?Added "No Connect Pins"signals group ?"No Connect Pins"signals group:
–Moved pin 91from "Digital Logic Power Pins (Master and Control Subsystems)"signals group to
"No Connect Pins"signals group Figure 3-2Added "Input Clock Configurations"figure
Section 4.2
Recommended Operating Conditions:?Device supply voltage,Analog Subsystem,V DD18:
–Changed MAX value from 1.89V to 1.995V
Section 4.3Electrical Characteristics:?Updated footnote
Section 5.2.1Changed section title from "Pulse Width Modulator (PWM)Modules"to "Pulse Width Modulator (PWM)and High-Resolution PWM (HRPWM)Modules"
Section 5.2.1
Pulse Width Modulator (PWM)and High-Resolution PWM (HRPWM)Modules:?Updated "There are nine PWM modules in the Concerto device ..."paragraph ?Updated "The synchronization inputs to the PWM modules include the SYNCI signal ..."paragraph Figure 5-1Updated "ePWM,eQEP,eCAP"figure Figure 5-4Updated "Comparator +DAC Units"figure
Table 5-1
F28M35Hx Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK:?Added TYP values for SLEEP IDLE mode,SLEEP STANDBY mode,and DEEP SLEEP STANDBY
mode Figure 6-1
Device Nomenclature:?RAM:
–Changed "0=132KB"to "0=72KB"
F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1
F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
SPRS742C–JUNE2011–REVISED https://www.doczj.com/doc/2c11449052.html, 2Device Overview
The Concerto?microcontroller(MCU)comprises three subsystems:the Master Subsystem,the Control
Subsystem,and the Analog Subsystem.While the Master and Control Subsystem each have dedicated
local memories and peripherals,they can also share data and events through shared memories and
peripherals.The Analog Subsystem has two ADC converters and six Analog Comparators.Both the
Master and Control Subsystems access the Analog Subsystem through the Analog Common Interface
Bus(ACIB).The NMI Blocks force communication of critical events to the Master and Control Subsystem
processors and their Watchdog Timers.The Reset Block responds to Watchdog Timer NMI Reset,
External Reset,and other events to initialize subsystem processors and the rest of the chip to a known
state.The Clocking Blocks support multiple low-power modes where clocks to the processors and
peripherals can be slowed down or stopped in order to manage power consumption.
NOTE
Throughout this document,the Master Subsystem is denoted by the color"blue";the Control
Subsystem is denoted by the color"green";and the Analog Subsystem is denoted by the
color"orange".
PRODUCT PREVIEW
P R O D U C T P R E V I E W
F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
https://www.doczj.com/doc/2c11449052.html,
SPRS742C –JUNE 2011–REVISED JANUARY 2012
2.2Memory Maps
Section 2.2.1shows the Control Subsystem Memory Map.Section 2.2.2shows the Master Subsystem Memory Map.
2.2.1Control Subsystem Memory Map
Table 2-2.Control Subsystem M0,M1RAM
C Address Size C DMA Access (1)
Control Subsystem M0,M1RAM
(x16Aligned)(1)(Bytes)no 00000000–000003FF M0RAM (ECC)2K no
00000400–000007FF
M1RAM (ECC)
2K
(1)The letter "C "refers to the Control Subsystem.
Table 2-3.Control Subsystem Peripheral Frame 0(Includes Analog)
C Address Control Subsystem Peripheral Frame 0
Size C DMA Access (1)
(x16Aligned)(1)(Includes Analog)
(Bytes)
00000800–0000087F
Reserved
Control Subsystem Device Configuration Registers (Read no
00000880–0000089034Only)00000891–00000ADF
Reserved
no 00000AE0–00000AEF C28x CSM Registers 3200000AF0–00000AFF Reserved
yes 00000B00–00000B0F ADC1Result Registers 3200000B10–00000B3F Reserved
yes 00000B40–00000B4F ADC2Result Registers 3200000B50–00000BFF Reserved no 00000C00–00000C07CPU Timer 016no 00000C08–00000C0F CPU Timer 116no 00000C10–00000C17CPU Timer 21600000C18–00000CDF Reserved no 00000CE0–00000CFF PIE Registers 64no 00000D00–00000DFF PIE Vector Table
512no 00000E00–00000EFF PIE Vector Table Copy (Read Only)51200000F00–00000FFF Reserved
no 00001000–000011FF C28x DMA Registers 1K 00001200–000016FF Reserved
no
00001700–0000177F Analog Subsystem Control Registers 25600001780–00003FFF
Reserved
(1)
The letter "C "refers to the Control Subsystem.
F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1
F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
SPRS742C–JUNE2011–REVISED https://www.doczj.com/doc/2c11449052.html,
Table2-4.Control Subsystem Peripheral Frame3
C Address Control Subsystem Size M AddressμDMA
C DMA Access(1)
(x16Aligned)(1)Peripheral Frame3(Bytes)(Byte-Aligned)(2)Access no00004000–00004181C28x Flash Control Registers772
00004182–000042FF Reserved
C28x Flash ECC Error Log
no00004300–0000432372
Registers
00004324–000043FF Reserved
no00004400–0000443F M Clock Control Registers(2)128400F B800–400F B87F no
00004440–000048FF Reserved
no00004900–0000497F RAM Configuration Registers256400F B200–400F B2FF no
00004980–000049FF Reserved
RAM ECC/Parity/Access Error
no00004A00–00004A7F256400F B300–400F B3FF no
Log Registers
00004A80–00004DFF Reserved
no00004E00–00004E3F CtoM and MtoC IPC Registers128400F B700–400F B77F no
00004E40–00004FFF Reserved
yes00005000–0000503F McBSP-A128
00005040–000050FF Reserved PRODUCT PREVIEW
yes00005100–0000517F EPWM1(Hi-Resolution)256
yes00005180–000051FF EPWM2(Hi-Resolution)256
yes00005200–0000527F EPWM3(Hi-Resolution)256
yes00005280–000052FF EPWM4(Hi-Resolution)256
yes00005300–0000537F EPWM5(Hi-Resolution)256
yes00005380–000053FF EPWM6(Hi-Resolution)256
yes00005400–0000547F EPWM7(Hi-Resolution)256
yes00005480–000054FF EPWM8(Hi-Resolution)256
yes00005500–0000557F EPWM9256
00005580–000057FF Reserved
(1)The letter"C"refers to the Control Subsystem.
(2)The letter"M"refers to the Master Subsystem.
P R O D U C T P R E V I E W
F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
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SPRS742C –JUNE 2011–REVISED JANUARY 2012
Table 2-5.Control Subsystem Peripheral Frame 1
C Address Size C DMA Access (1)
Control Subsystem Peripheral Frame 1
(x16Aligned)(1)(Bytes)
00005800–000059FF
Reserved
no 00005A00–00005A1F ECAP164no 00005A20–00005A3F ECAP264no 00005A40–00005A5F ECAP364no 00005A60–00005A7F ECAP464no 00005A80–00005A9F ECAP564no 00005AA0–00005ABF ECAP66400005AC0–00005AFF Reserved no 00005B00–00005B3F EQEP1128no 00005B40–00005B7F EQEP2128no 00005B80–00005BBF EQEP3128
00005BC0–00005F7F Reserved
no 00005F80–00005FFF C GPIO Group 1Registers (1)25600006000–000063FF Reserved no 00006400–0000641F COMP1Registers 64no 00006420–0000643F COMP2Registers 64no 00006440–0000645F COMP3Registers 64no 00006460–0000647F COMP4Registers 64no 00006480–0000649F COMP5Registers 64no 000064A0–000064BF COMP6Registers 64000064C0–00006F7F Reserved
no
00006F80–00006FFF
C GPIO Group 2Registers and AIO Mux Registers (1)
256(1)
The letter "C "refers to the Control Subsystem.
Table 2-6.Control Subsystem Peripheral Frame 2
C Address Size C DMA Access (1)
Control Subsystem Peripheral Frame 2
(x16Aligned)(1)(Bytes)
00007000–000070FF
Reserved
no 00007010–0000702F C28x System Control Registers 6400007030–0000703F Reserved no 00007040–0000704F SPI-A 32no 00007050–0000705F SCI-A
32no 00007060–0000706F NMI Watchdog Interrupt Registers 32no
00007070–0000707F External Interrupt Registers 3200007080–000070FF
Reserved
ADC1Configuration Registers
no 00007100–0000717F 256(Only 16-bit read/write access supported)ADC2Configuration Registers
no
00007180–000071FF 256(Only 16-bit read/write access supported)00007200–000078FF
Reserved no
00007900–0000793F I2C-A 12800007940–00007FFF
Reserved
(1)
The letter "C "refers to the Control Subsystem.
F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1
F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
SPRS742C–JUNE2011–REVISED https://www.doczj.com/doc/2c11449052.html,
Table2-7.Control Subsystem RAMs
C Address Size M AddressμDMA
C DMA Access(1)Control Subsystem RAMs
(x16Aligned)(1)(Bytes)(Byte-Aligned)(2)Access
no00008000–00008FFF L0RAM(ECC,Secure)8K
no00009000–00009FFF L1RAM(ECC,Secure)8K
yes0000A000–0000AFFF L2RAM(Parity,Interleaving)8K
yes0000B000–0000BFFF L3RAM(Parity,Interleaving)8K
yes0000C000–0000CFFF S0RAM(Parity,Shared)8K20008000–20009FFF yes
yes0000D000–0000DFFF S1RAM(Parity,Shared)8K2000A000–2000BFFF yes
yes0000E000–0000EFFF S2RAM(Parity,Shared)8K2000C000–2000DFFF yes
yes0000F000–0000FFFF S3RAM(Parity,Shared)8K2000E000–2000FFFF yes
yes00010000–00010FFF S4RAM(Parity,Shared)8K20010000–20011FFF yes
yes00011000–00011FFF S5RAM(Parity,Shared)8K20012000–20013FFF yes
yes00012000–00012FFF S6RAM(Parity,Shared)8K20014000–20015FFF yes
yes00013000–00013FFF S7RAM(Parity,Shared)8K20016000–20017FFF yes
00014000–0003F7FF Reserved
yes yes0003F800–0003FBFF CtoM MSG RAM(Parity)2K2007F000–2007F7FF
read only
yes PRODUCT PREVIEW
0003FC00–0003FFFF MtoC MSG RAM(Parity)2K2007F800–2007FFFF yes read only
00040000–00047FFF Reserved
no00048000–00048FFF L0RAM-ECC Bits8K
no00049000–00049FFF L1RAM-ECC Bits8K
no0004A000–0004AFFF L2RAM-Parity Bits8K
no0004B000–0004BFFF L3RAM-Parity Bits8K
no0004C000–0004CFFF S0RAM-Parity Bits8K20088000–20089FFF no
no0004D000–0004DFFF S1RAM-Parity Bits8K2008A000–2008BFFF no
no0004E000–0004EFFF S2RAM-Parity Bits8K2008C000–2008DFFF no
no0004F000–0004FFFF S3RAM-Parity Bits8K2008E000–2008FFFF no
no00050000–00050FFF S4RAM-Parity Bits8K20090000–20091FFF no
no00051000–00051FFF S5RAM-Parity Bits8K20092000–20093FFF no
no00052000–00052FFF S6RAM-Parity Bits8K20094000–20095FFF no
no00053000–00053FFF S7RAM-Parity Bits8K20096000–20097FFF no
no00054000–0007EFFF Reserved
no0007F000–0007F3FF M0RAM-ECC Bits2K
no0007F400–0007F7FF M1RAM-ECC Bits2K
no0007F800–0007FBFF CtoM MSG RAM-Parity Bits2K200F F000–200F F7FF no
no0007FC00–0007FFFF MtoC MSG RAM-Parity Bits2K200F F800–200F FFFF no
00080000–0009FFFF Reserved
(1)The letter"C"refers to the Control Subsystem.
(2)The letter"M"refers to the Master Subsystem.
P R O D U C T P R E V I E W
F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
https://www.doczj.com/doc/2c11449052.html,
SPRS742C –JUNE 2011–REVISED JANUARY 2012
Table 2-8.Control Subsystem Flash,ECC,OTP,Boot ROM
C Address Size C DMA Access (1)
Control Subsystem Flash,ECC,OTP,Boot ROM (x16Aligned)(1)(Bytes)no 00100000–00101FFF Sector N (not available for 256KB Flash configuration)16K no 00102000–00103FFF Sector M (not available for 256KB Flash configuration)16K no 00104000–00105FFF Sector L (not available for 256KB Flash configuration)16K no 00106000–00107FFF Sector K (not available for 256KB Flash configuration)16K no 00108000–0010FFFF Sector J (not available for 256KB Flash configuration)64K no 00110000–00117FFF Sector I (not available for 256KB Flash configuration)64K no 00118000–0011FFFF Sector H (not available for 256KB Flash configuration)64K no 00120000–00127FFF Sector G 64K no 00128000–0012FFFF Sector F 64K no 00130000–00137FFF Sector E 64K no 00138000–00139FFF Sector D 16K no 0013A000–0013BFFF Sector C 16K no 0013C000–0013DFFF Sector B
16K Sector A
no 0013E000–0013FFFF 16K
(CSM password in the high address)no 00140000–001F FFFF Reserved
Flash -ECC Bits
no 00200000–00207FFF 64K (1/8of Flash used =64KBytes)no 00208000–002401FF Reserved no 00240200–002403FF TI OTP 1K no 00240400–003F 7FFF Reserved
no
003F 8000–003F FFFF
C28x Boot ROM (64KBytes)
64K (1)
The letter "C "refers to the Control Subsystem.
PRODUCT PREVIEW F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1
F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
SPRS742C–JUNE2011–REVISED https://www.doczj.com/doc/2c11449052.html, 2.2.2Master Subsystem Memory Map
Table2-9.Master Subsystem Flash,ECC,OTP,Boot ROM
M Address Size
μDMA Access Master Subsystem Flash,ECC,OTP,Boot ROM
(Byte-Aligned)(1)(Bytes)
Boot ROM-Dual-mapped to0x01000000
no00000000–0000FFFF64K
(Both maps access same physical location.)
00010000–001F FFFF Reserved
Sector N
no00200000–00203FFF16K
(Zone1CSM password in the low address.)
no00204000–00207FFF Sector M16K
no00208000–0020BFFF Sector L16K
no0020C000–0020FFFF Sector K16K
no00210000–0021FFFF Sector J64K
no00220000–0022FFFF Sector I(not available for256KB Flash configuration)64K
no00230000–0023FFFF Sector H(not available for256KB Flash configuration)64K
no00240000–0024FFFF Sector G(not available for256KB Flash configuration)64K
no00250000–0025FFFF Sector F(not available for256KB Flash configuration)64K
no00260000–0026FFFF Sector E64K
no00270000–00273FFF Sector D16K
no00274000–00277FFF Sector C16K
no00278000–0027BFFF Sector B16K
Sector A
no0027C000–0027FFFF16K
(Zone2CSM password in the high address.)
00280000–005F FFFF Reserved
Flash-ECC Bits
no00600000–0060FFFF64K
(1/8of Flash used=64KBytes)
00610000–0068047F Reserved
no00680480–006807FF TI OTP896
no00680800OTP–Security Lock4
no00680804Reserved
no00680808Reserved
no0068080C OTP–Zone2Flash Start Address4
no00680810OTP–EMAC Address04
no00680814OTP–EMAC Address14
00680818–007000FF Reserved
OTP–ECC Bits–Application Use
no00700100–007001023
(1/8of OTP used=3Bytes)
00700103–00FF FFFF Reserved
Boot ROM–Dual-mapped to0x00000000
no01000000–0100FFFF64K
(Both maps access same physical location.)
01010000–03FF FFFF Reserved
ROM/Flash/OTP/Boot ROM–Mirror-mapped forμCRC.
Accessing this area of memory by theμCRC peripheral
will cause an access in00000000–03FF FFFF
memory space.
Mirrored boot ROM:0x04000000–0x0400FFFF(Not no04000000–07FF FFFF dual-mapped ROM address)64M
Mirrored Flash bank:0x04200000–0x042F FFFF
Mirrored Flash OTP:0x04680000–0x04681FFF
(Read cycles from this space cause theμCRC peripheral
to continuously update data checksum inside a register,
when reading a block of data.)
08000000–1FFF FFFF Reserved
P R O D U C T P R E V I E W
F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
https://www.doczj.com/doc/2c11449052.html,
SPRS742C –JUNE 2011–REVISED JANUARY 2012
Table 2-10.Master Subsystem RAMs
μDMA M Address Size C Address Master Subsystem RAMs C DMA Access (2)
Access (Byte-Aligned)(1)(Bytes)(x16Aligned)(2)
no 20000000–20001FFF C0RAM (ECC,Secure)8K no 20002000–20003FFF C1RAM (ECC,Secure)8K yes 20004000–20005FFF C2RAM (Parity)8K yes 20006000–20007FFF C3RAM (Parity)8K yes 20008000–20009FFF S0RAM (Parity,Shared)8K 0000C000–0000CFFF yes yes 2000A000–2000BFFF S1RAM (Parity,Shared)8K 0000D000–0000DFFF yes yes 2000C000–2000DFFF S2RAM (Parity,Shared)8K 0000E000–0000EFFF yes yes 2000E000–2000FFFF S3RAM (Parity,Shared)8K 0000F000–0000FFFF yes yes 20010000–20011FFF S4RAM (Parity,Shared)8K 00010000–00010FFF yes yes 20012000–20013FFF S5RAM (Parity,Shared)8K 00011000–00011FFF yes yes 20014000–20015FFF S6RAM (Parity,Shared)8K 00012000–00012FFF yes yes 20016000–20017FFF S7RAM (Parity,Shared)8K
00013000–00013FFF
yes
20018000–2007EFFF Reserved
yes 2007F000–2007F7FF CtoM MSG RAM (Parity)2K 0003F800–0003FBFF yes
read only yes yes 2007F800–2007FFFF MtoC MSG RAM (Parity)2K 0003FC00–0003FFFF
read only
no 20080000–20081FFF C0RAM -ECC Bits 8K no 20082000–20083FFF C1RAM -ECC Bits 8K no 20084000–20085FFF C2RAM -Parity Bits 8K no 20086000–20087FFF C3RAM -Parity Bits 8K no 20088000–20089FFF S0RAM -Parity Bits 8K 0004C000–0004CFFF no no 2008A000–2008BFFF S1RAM -Parity Bits 8K 0004D000–0004DFFF no no 2008C000–2008DFFF S2RAM -Parity Bits 8K 0004E000–0004EFFF no no 2008E000–2008FFFF S3RAM -Parity Bits 8K 0004F000–0004FFFF no no 20090000–20091FFF S4RAM -Parity Bits 8K 00050000–00050FFF no no 20092000–20093FFF S5RAM -Parity Bits 8K 00051000–00051FFF no no 20094000–20095FFF S6RAM -Parity Bits 8K 00052000–00052FFF no no 20096000–20097FFF S7RAM -Parity Bits 8K
00053000–00053FFF
no
20098000–200F EFFF Reserved
no 200F F000–200F F7FF CtoM MSG RAM -Parity Bits 2K 0007F800–0007FBFF no no
200F F800–200F FFFF MtoC MSG RAM -Parity Bits 2K
0007FC00–0007FFFF
no
20100000–21FF FFFF
Reserved
Bit Banded RAM Zone
(Dedicated address for each yes
22000000–23FF FFFF
32M RAM bit of Cortex ?-M3RAM blocks above)
All RAM Spaces –
Mirror-Mapped for μCRC .Accessing this memory by the μCRC peripheral will cause an access to
20000000–23FF FFFF yes 24000000–27FF FFFF 64M
memory space.
(Read cycles from this space cause the μCRC peripheral to continuously update data checksum inside a register when reading a block of data.)28000000–3FFF FFFF
Reserved
(1)The letter "M "refers to the Master Subsystem.
PRODUCT PREVIEW F28M35H20B1,F28M35H20C1
F28M35H22B1,F28M35H22C1,F28M35H32B1,F28M35H32C1
F28M35H50B1,F28M35H50C1,F28M35H52B1,F28M35H52C1
SPRS742C–JUNE2011–REVISED https://www.doczj.com/doc/2c11449052.html,
Table2-11.Master Subsystem Peripherals
μDMA M Address Master Subsystem Size C Address
C DMA Access(2) Access(Byte-Aligned)(1)Peripherals(Bytes)(x16Aligned)(2)
yes40000000–40000FFF Watchdog Timer0Registers4K
yes40001000–40001FFF Watchdog Timer1Registers4K
40002000–40003FFF Reserved
yes40004000–40004FFF M GPIO Port A(APB Bus)(1)4K
yes40005000–40005FFF M GPIO Port B(APB Bus)(1)4K
yes40006000–40006FFF M GPIO Port C(APB Bus)(1)4K
yes40007000–40007FFF M GPIO Port D(APB Bus)(1)4K
yes40008000–40008FFF SSI04K
yes40009000–40009FFF SSI14K
yes4000A000–4000AFFF SSI24K
yes4000B000–4000BFFF SSI34K
yes4000C000–4000CFFF UART04K
yes4000D000–4000DFFF UART14K
yes4000E000–4000EFFF UART24K
yes4000F000–4000FFFF UART34K
yes40010000–40010FFF UART44K
40011000–4001FFFF Reserved
no40020000–400207FF I2C0Master2K
no40020800–40020FFF I2C0Slave2K
no40021000–400217FF I2C1Master2K
no40021800–40021FFF I2C1Slave2K
40022000–40023FFF Reserved
yes40024000–40024FFF M GPIO Port E(APB Bus)(1)4K
yes40025000–40025FFF M GPIO Port F(APB Bus)(1)4K
yes40026000–40026FFF M GPIO Port G(APB Bus)(1)4K
yes40027000–40027FFF M GPIO Port H(APB Bus)(1)4K
40028000–4002FFFF Reserved
yes40030000–40030FFF GP Timer04K
yes40031000–40031FFF GP Timer14K
yes40032000–40032FFF GP Timer24K
yes40033000–40033FFF GP Timer34K
40034000–4003CFFF Reserved
yes4003D000–4003DFFF M GPIO Port J(APB Bus)(1)4K
4003E000–4003FFFF Reserved
yes40048000–40048FFF ENET MAC04K
40049000–4004FFFF Reserved
yes40050000–40050FFF USB MAC04K
40051000–40057FFF Reserved
yes40058000–40058FFF M GPIO Port A(AHB Bus)(1)4K
yes40059000–40059FFF M GPIO Port B(AHB Bus)(1)4K
yes4005A000–4005AFFF M GPIO Port C(AHB Bus)(1)4K
yes4005B000–4005BFFF M GPIO Port D(AHB Bus)(1)4K
yes4005C000–4005CFFF M GPIO Port E(AHB Bus)(1)4K
yes4005D000–4005DFFF M GPIO Port F(AHB Bus)(1)4K
yes4005E000–4005EFFF M GPIO Port G(AHB Bus)(1)4K