DESCRIPTION
The MSM54V32126A is a Graphics DRAM organized in a 131,072-word ￥ 32-bit configuration. The technology used to fabricate the MSM54V32126A is OKI's CMOS silicon gate process technology. The device operates with a single 3.3 V power supply.
FEATURES
?131,072-word ￥ 32-bit organization
?Single 3.3 V power supply, ±0.3 V tolerance
?Refresh:512 cycles/8 ms
?Fast Page Mode with Extended Data Out (EDO)
?Byte write, Byte read
?RAS only refresh
?CAS before RAS refresh
?CAS before RAS self-refresh
?Hidden refresh
?Package options:
64-pin 525 mil plastic SSOP(SSOP64-P-525-0.80-K)(Product : MSM54V32126A-xxGS-K) 70/64-pin 400 mil plastic TSOP (Type II)(TSOPII70/64-P-400-0.65-K)(Product : MSM54V32126A-xxTS-K)
xx indicates speed rank. PRODUCT FAMILY
Family
t RAC
50 ns
60 ns
Operating (Max.)
504 mW
486 mW
Power Dissipation Cycle Time
(Min.)
100 ns
120 ns
MSM54V32126A-50 MSM54V32126A-60
t AA
25 ns
30 ns
t CAC
15 ns
18 ns
Standby (Max.) Access Time (Max.)
3.1 mW
t OEA
15 ns
18 ns
45 ns540 mW
90 ns
MSM54V32126A-4523 ns13 ns13 ns
? Semiconductor MSM54V32126A
PIN CONFIGURATION (TOP VIEW)
Pin Name Function
A0 - A8Address Input
Power Supply (3.3 V)Ground (0 V)NC
No Connection
V CC V SS DQ0 - DQ31
Data Input / Data Output RAS Row Address Strobe CAS1 - CAS4
Column Address Strobe Write Enable WE OE Output Enable Note:
The same power supply voltage must be provided to every V CC pin, and the same GND voltage level must be provided to every V SS pin.
64-Pin Plastic SSOP
70/64-Pin Plastic TSOP (II )
(K Type)
DQ28DQ29DQ27V CC DQ26DQ24DQ25DQ23V SS DQ22DQ20DQ21DQ19V CC DQ18DQ16DQ17V SS NC DQ14DQ15NC V CC DQ12DQ10DQ11DQ1DQ2DQ3V CC DQ4DQ5DQ6DQ7DQ13V SS DQ30V CC V SS DQ8DQ9DQ31DQ0A2A3V CC CAS1CAS2CAS3CAS4OE A8A7A6A5A4V SS
V SS NC WE A1A0NC RAS
DQ28DQ29DQ27V CC DQ26DQ24DQ25DQ23V SS DQ22DQ20DQ21DQ19V CC
DQ18DQ16DQ17V SS NC DQ14DQ15NC V CC
DQ12DQ10DQ11DQ1DQ2DQ3V CC DQ4DQ5DQ6DQ7DQ13V SS DQ30V CC V SS DQ8DQ9DQ31DQ0A2A3V CC CAS1CAS2CAS3CAS4OE A8A7A6A5A4V SS
V SS NC WE A1A0NC RAS 12345678910111213141516
202122232425262728293031323334357069686766656463626160595857565551504948474645444342414039383736
? Semiconductor
MSM54V32126A
BLOCK DIAGRAM
R A S
C A S 4
C A S 3
A 0 -
D Q 8 - D Q 15
D Q 16 - D Q 23
V C C
V S S
D Q 0 - D Q 7
D Q 24 - D Q 31
C A S 2
C A S 1
? Semiconductor MSM54V32126A ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating
–0.5 to 4.5
50
1
0 to 70–55 to 150
V mA W °C °C
Voltage on Any Pin Relative to V SS Short Circuit Output Current Power Dissipation
Operating Temperature Storage Temperature
V T I OS P D T opr T stg
Parameter Unit
Symbol
Recommended Operating Conditions
Input High Voltage Power Supply Voltage Input Low Voltage V CC
V SS
V IH
V IL
Max.
3.6
3.6
0.3
V
V
V
V
Typ.
3.3
—
—
Min.
3.0
3.0
–0.3
(Ta = 0°C to 70°C)
Parameter Unit
Symbol
Capacitance
Input Capacitance C IN
C IO pF pF
Input / Output Capacitance
Max.
7
7
Typ.
—
—
(V CC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz)
Parameter Unit
Symbol
? Semiconductor MSM54V32126A
DC Characteristics
Average Power Supply Current
(CAS before RAS Refresh)RAS = cycling,CAS before RAS
1, 2, 4
mA 110130——I CC5Average Power Supply Current (Fast Page Mode)RAS = V IL ,CAS cycling,t HPC = Min.1, 2, 4
135140——I CC4mA Input Leakage Current
Output High Voltage Condition Note Average Power
Supply Current (Operating)Power Supply Current (Standby)Output Low Voltage Output Leakage Current Unit Average Power Supply Current (RAS Only Refresh)Parameter I OH = –0.1 mA I OL = 0.1 mA 0 V < V IN < V CC ;All other pins not under test = 0 V 0 V < V OUT < 3.6 V Output Disable RAS , CAS cycling,t RC = Min.RAS ≥ V CC – 0.2 V,CAS ≥ V CC – 0.2 V RAS = cycling,CAS = V IH ,t RC = Min.V V m A
m A
1, 2, 3
mA m A
1, 2, 3
mA Max.
V CC 0.810
10110850
110Min.2.00–10
–10—Max.V CC 0.810
10130850130Min.2.00–10
–10—————Symbol
V OH V OL I LI
I LO I CC1I CC2
I CC3MSM54V32126A
-60
MSM54V32126A -50(V CC = 3.3 V ±0.3 V, Ta = 0°C to 70°C)
140—150—Max.V CC 0.810
10140850140Min.2.00–10
–10———MSM54V32126A -45Average Power Supply Current (CAS before RAS Self-Refresh)
RAS = V IL ,CAS = V IL
1, 2
m A 950950——I CCS
950—Notes:
1.Specified values are obtained with minimum cycle time.
2.I CC is dependent on output loading. Specified values are obtained with the output open.
3.Address can be changed once or less while RAS = V IL .
4.Address can be changed once or less while CAS = V IH .
? Semiconductor MSM54V32126A
AC Characteristics (1/2)
Parameter
Symbol Note
Unit —t RC t PRWC t AA t CAC t CPA
t RASP t CAS t RCD Max.Min.Max.Min.MSM54V32126A
-60MSM54V32126A -50——t HPC t RAC t REZ t RSH t CSH t T t RP t RAS t RAD t ASR t RAH t ASC t CAH t AR t RCS t RCH t RRH t WCS t WCH
—t RWC t RAL t CRP t CP Access Time from Column Address Column Address Hold Time referenced to RAS Column Address Set-up Time Row Address Set-up Time Access Time from CAS
Column Address Hold Time
CAS Pulse Width CAS Precharge Time (Hyper Page Mode)Access Time from CAS Precharge
CAS to RAS Precharge Time
CAS Hold Time Output Buffer Turn-off Delay Time from RAS Fast Page Mode Cycle Time
Fast Page Mode Read-Modify-Write Cycle Time Row Address Hold Time RAS Pulse Width (Hyper Page Mode Only)Random Read or Write Cycle Time RAS to CAS Delay Time
Read Command Hold Time
Read Command Set-up Time Read Modify Write Cycle RAS Precharge Time Read Command Hold Time referenced to RAS Access Time from RAS
RAS to Column Address Delay Time Column Address to RAS Lead Time RAS Pulse Width
RAS Hold Time Transition Time (Rise and Fall)Write Command Set-up Time Write Command Hold Time
ns —120100ns 30—25—ns 18—15—ns 35—30—ns 353353ns 100k 60100k 50ns —8070ns 10k 910k 792020ns —2420ns 60—50—5ns 203203ns —54—44ns —14—14ns —60—50ns 10k 6010k 5010
15150097001084035006, 12006000010
8
4, 104, 94, 134, 9,10
3
ns 4235ns 3025ns ns ns ns ns ns ns ns ns ns
ns —170145ns —28—248697ns ns 8, 12———————————————————————
—
t CEZ Output Buffer Turn-off Delay Time from CAS 5ns 203203t CRL CAS "H" to RAS "H" Lead Time 00ns ——t RCL RAS "H" to CAS "H" Lead Time 00ns ——t DOH Data Output Hold after CAS Low 1133ns ——MSM54V32126A -45Max.—23132835100k —10k —4520———10k 3222——————————————
20———Min.90———3456562018—3391245451506073000007
135********(V CC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3
131512121212
? Semiconductor MSM54V32126A
AC Characteristics (2/2)
Parameter
Symbol Note
Unit —t DS t RWD t CWD t DZC t DZO t CSR t REF
t RASS
Max.Min.Max.Min.MSM54V32126A
-60MSM54V32126A -50t DHR t AWD t OEA t CHR t RPC t OEZ t OEH t ROH t RPS
t CHS
t DH Column Address to WE Delay Time CAS Hold Time for CAS before RAS Cycle CAS Set-up Time for CAS before RAS Cycle CAS to WE Delay Time Data Hold Time
Data Hold Time referenced to RAS Data Set-up Time Data to CAS Delay Time Data to OE Delay Time CAS H old Time (CAS before RAS Self-Refresh) OE Command Hold Time Refresh Period RAS Hold Time referenced to OE RAS Precharge to CAS Active Time RAS to WE Delay Time
RAS Precharge Time (CAS before RAS Self-Refresh)
Access Time from OE
RAS Pulse Width (CAS before RAS Self-Refresh)Output Buffer Turn-off Delay Time from OE ns —00ns 4035ns 00ns 00ns 203203ns 108ns 8070ms 88100100ns 4035ns 5045ns 1815ns 109ns 108ns 1010ns 12101301100
88m s ns ns
ns 1087, 12
7, 128—————————————————————————————————
—
t WCR t WP t RWL t CWL Write Command to CAS Lead Time Write Command to RAS Lead Time Write Command Hold Time referenced to RAS Write Command Pulse Width 4035109109109ns ns ns ns ————————t WEZ
Output Buffer Turn-off Delay Time from WE 33ns 202055t OCH OE "L" to CAS "H" Lead Time ns 1010——t CHO CAS "H" to OE "L" Lead Time ns 1010——t OEP OE Precharge Time
ns 1210——t OED OE to Data-in Delay Time ns 1212——t CPT CAS Precharge Time (Refresh Counter Test)ns 3025——MSM54V32126A -45—Max.Min.
0320020366581003042138610101000
7—————————————————
30888————32010—10—10—12—20—t WPE WE Pulse Width (Output Disable) ns 1210——10—1415121312(V CC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3
? Semiconductor MSM54V32126A Notes: 1.An initial pause of 200 m s is required after power-up followed by any 8 RAS cycles (Example : RAS only refresh) before proper device operation is achieved. In case of
using internal refresh counter, a minimum of 8 CAS before RAS cycles instead of 8 RAS
cycles are required.
2.The AC characteristics assume at t T = 3 ns.
3.V IH (Min.) and V IL (Max.) are reference levels for measuring timing of input signals.
Also, transition times are measured between V IH and V IL. Input levels at the AC testing
are 3.0 V/0 V.
4.Data outputs are measured with a load of 30 pF.
DOUT reference levels : V OH/V OL = 2.0 V/0.8 V.
5.t REZ (Max.), t CEZ (Max.), t WEZ (Max.) and t OEZ (Max.) define the time at which the
outputs achieve the open circuit condition and are not referenced to output voltage
levels. This parameter is sampled and not 100% tested.
6.Either t RCH or t RRH must be satisfied for a read cycle.
7.These parameters are referenced to CAS leading edge of early write cycles and to WE
leading edge in OE controlled write cycles and read modify write cycles.
8.t WCS, t RWD, t CWD and t AWD are not restrictive operating parameters. They are included
in the data sheet as electrical characteristics only. If t WCS ≥ t WCS (Min.), the cycle is an
early write cycle and the data out pin will remain open circuit throughout the entire
cycle; If t RWD≥ t RWD (Min.), t CWD≥ t CWD (Min.) and t AWD≥ t AWD (Min.), the cycle is
a read modify write cycle and the data out will contain data read from the selected cell:
If neither of the above sets of conditions is satisfied, the condition of the data out is
indeterminate.
9.Operation within the t RCD (Max.) limit ensures that t RAC (Max.) can be met.
t RCD (Max.) is specified as a reference point only: If t RCD is greater than the specified
t RCD (Max.) limit, then access time is controlled by t CAC.
10.Operation within the t RAD (Max.) limit ensures that t RAC (Max.) can be met. t RAD (Max.)
is specified as a reference point only: If t RAD is greater than the specified t RAD (Max.)
limit, then access time is controlled by t AA.
11.This is guaranteed by design. (t DOH = t CAC - output transition time) This parameter is
not 100% tested.
12.These parameters are determined by the earliest falling edge of CAS1, CAS2, CAS3, or
CAS4.
13.These parameters are determined by the latest rising edge of CAS1, CAS2, CAS3, or
CAS4.
14.t CWL should be satisfied by all CAS es.
15.t CP and t CPT are determined by the time that all CAS es are high.
? Semiconductor MSM54V32126A CASn-DQ FUNCTION TABLE
CAS1 H H CAS2
H
H
CAS3
H
H
CAS4
H
L
DQ0-7
*
*
DQ8-15
*
*
DQ16-23
*
*
DQ24-31
*
Enable
H H L H**Enable* H H L L**Enable Enable H L H H*Enable** H L H L*Enable*Enable H L L H*Enable Enable* H L L L*Enable Enable Enable L H H H Enable*** L H H L Enable**Enable L H L H Enable*Enable* L H L L Enable*Enable Enable L L H H Enable Enable** L L H L Enable Enable*Enable L L L H Enable Enable Enable* L L L L Enable Enable Enable Enable
Read cycle Write cycle
Enable
Valid Data-out
Write Data
*
High-Z
Don't Care
? Semiconductor MSM54V32126A
TIMING WAVEFORM
Read Cycle (Outputs Controlled by RAS )
RAS
Address
WE
DQ0 - DQ31
CAS1 | CAS4
OE
? Semiconductor
MSM54V32126A
Read Cycle (Outputs Controlled by CAS )
RAS
Address
WE
DQ0 - DQ31
CAS1 | CAS4
OE
? Semiconductor MSM54V32126A
Write Cycle (Early Write)
RAS
CAS1 | CAS4
Address
"H" or "L"
WE
DQ0 - DQ31
OE
? Semiconductor
MSM54V32126A
Write Cycle (OE Control Write)
RAS
CAS1 | CAS4
Address
"H" or "L"
WE
DQ0 - DQ31
OE
? Semiconductor MSM54V32126A Read Modify Write Cycle
CAS1
|
CAS4
Address
WE
OE
DQ0 - DQ31
? Semiconductor
MSM54V32126A
Fast Page Mode Read Cycle with EDO
RAS
Address
WE
DQ0 - DQ31
CAS1 | CAS4
OE
"H" or "L"
? Semiconductor
MSM54V32126A
Fast Page Mode Write Cycle (Early Write)
RAS
Address
WE
DQ0 - DQ31
CAS1 | CAS4OE
"H" or "L"
? Semiconductor
MSM54V32126A
Fast Page Mode Read Modify Write Cycle
RAS
Address
WE
DQ0 - DQ31
CAS1 | CAS4
OE
"H" or "L"
? Semiconductor MSM54V32126A
RAS Only Refresh Cycle
RAS
Address
CAS1 | CAS4
"H" or "L"
Note: DQs are open, WE , OE = "H" or "L"
? Semiconductor MSM54V32126A CAS before RAS Refresh Cycle
CASn
DQ0 - DQ31
Note:WE, OE, A0 - A8 = "H" or "L"
? Semiconductor MSM54V32126A Hidden Refresh Read Cycle
RAS
CAS1
|
CAS4
Address
OE
"H" or "L"
WE
DQ0 - DQ31