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FULLY INTEGRATED 8-CHANNEL DC/DC CONVERTER FOR DIGITAL STILL CAMERAS
1
FEATURES
APPLICATIONS
? ? Digital Still Cameras (DSCs) Portable Electronics Equipment
? 8-Channel DC/DC Converter and Low Dropout (LDO) ? Integrated Power MOSFET Switch Except CH8 – Boost (CH5/7) – Buck (CH1/3) – Buck-Boost (CH2/4) – Invert (CH6) ? Low-Power Suspend Mode (Sleep Mode) ? Power ON/OFF Sequence (CH1/2/3 and CH5/6) ? LED-Back Light Brightness Control (CH7) ? Fixed Switching Frequency (CH1–4: 1.5 MHz, CH5–8: 750 kHz) ? Fixed Max Duty Cycle Internally ? Soft Start ? Undervoltage Lockout (UVLO) ? Protection – Thermal Shutdown (TSD) – Overvoltage Protection (OVP) – Overcurrent Protection (OCP) Except CH8 ? Supply Voltage Range: 1.5 V to 5.5 V ? Operating Temperature Range: –25°C to 85°C ? 6 × 6 mm, 0.4-mm Pitch, 48-Pin QFN Package
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DESCRIPTION/ ORDERING INFORMATION
The TPS65530 is a fully integrated 8-channel switching dc/dc converter, and seven channels have integrated power FET. CH2/4 are configured for H bridge for buck-boost topology and single inductor supports. These channels achieve higher efficiency in spite of input/output voltage conditions. CH7 has a brightness control and drives white LED by constant current. Also, CH7 supports overvoltage protection (OVP) for open load. CH1/2/3 have a power ON/OFF sequence suitable for a digital still camera (DSC) system. CH5/6 have a power ON/OFF sequence, depending on the CCD. Power ON/OFF for CCD block (CH5/6) is selectable by the input voltage level at the SEQ56 pin. CH4 and CH7 have individual ON/OFF sequences. The TPS65530 high switching frequency is achieved by an integrated power MOSFET switch. It reduces external parts dynamically. Shutdown current consumption is less than 1 μA as a typical value.
ORDERING INFORMATION
TA –25°C to 85°C (1) (2) QFN PACKAGE
(1) (2)
ORDERABLE PART NUMBER TPS65530RSLT TPS65530RSLR
TOP-SIDE MARKING TPS65530
Reel of 250 Reel of 2500
Package drawings, thermal data, and symbolization are available at https://www.doczj.com/doc/1818981297.html,/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at https://www.doczj.com/doc/1818981297.html,.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
Copyright ? 2007–2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
CHANNEL CONFIGURATION
CHANNEL CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 REF OPERATION MODE Buck SW Buck-boost SW Buck SW Buck-boost SW Boost SW Invert SW Boost SW Boost SW Low dropout voltage RECTIFY MODE Synchronous Synchronous Synchronous Synchronous Nonsynchronous Nonsynchronous Nonsynchronous Synchronous – CONTROL METHOD Voltage Average current Voltage Average current Peak current Voltage Voltage Voltage – OUTPUT VOLTAGE (V) 0.9 to 2.5 2.5 to 3.6 0.9 to 2.5 2.2 to 3.6 Up to 18 –10 to –5 3 to 20 3.3 to 5.5 2.8 APPLICATION Engine core Engine I/O (DSP I/F) External memory AFE CCD+ CCD– Backlight LED Motor controller and IC drive supply Internal supply for logic MAXIMUM SUPPLY CURRENT (mA) 600 600 300 300 50 100 25 – 15
QFN PACKAGE (TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
SW4S PGND4 SW4I VOUT4 FB4 ENAFE XSLEEP EN7 S/S AGND REF VCC2
1 2 3 4 5 6
37
PGND5/7
SWOUT
SEQ56
S/S56
EN56
SW6
VCC6
VCC5
FB5
SW5
VCC4
FB6
36 35 34 33 32 31
SW7 FBV CIN FBC B-ADJ FBG7/8 FB8 PS SW8HD LL8 SW8LD PGND3
PowerPAD?
7 8 9 10 11 12 30 29 28 27 26 25
13
18
19
20
15
21
23
14
16
SW2I
FB2
17
FB1
VOUT2
VCC1
FB3
22
SW1
VCC3
SW2S
PGND2
2
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PGND1
Copyright ? 2007–2008, Texas Instruments Incorporated
SW3
24
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TERMINAL FUNCTIONS
TERMINAL NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 (1) NAME SW4S PGND4 SW4I VOUT4 FB4 ENAFE XSLEEP EN7 S/S AGND REF VCC2 SW2S PGND2 SW2I VOUT2 FB2 VCC1 SW1 PGND1 FB1 FB3 VCC3 SW3 PGND3 SW8LD LL8 SW8HD PS FB8 FBG7/8 B-ADJ FBC CIN FBV SW7 PGND5/7 SW5 I/O (1) O G I O I I I I I/O G O P O G I O O P O G I I P O G O O O I I I I I I I O G O Buck-side terminal of coil for CH4 GND for CH4 low-side FET Boost-side terminal of coil for CH4 Output of CH4 Output voltage feedback for CH4. The external resistors should be connected as close as possible to the terminal. Enable for CH4 (L: Disable, H: Enable) Control for sleep mode/normal operation (L: Sleep mode, H: Normal operation) Enable for CH7 (L: Disable, H: Enable) Soft-start time adjustment. The time is programmable by an external capacitor (see the Soft Start description). Analog ground Output of LDO. From 2.2 μF to 4.7 μF, capacitor should be connected to AGND. Power supply at CH2 buck-side FET from battery Buck-side terminal of coil for CH2 GND for CH2 low-side FET Boost-side terminal of coil for CH2 Output of CH2 Output voltage feedback for CH2. The external resistors should be connected as close as possible to the terminal. Power supply at CH1 high-side FET from battery Output of CH1. The terminal should be connected to the external inductor. GND for CH1 low-side FET Output voltage feedback for CH1. The external resistors should be connected as close as possible to the terminal. Output voltage feedback for CH3. The external resistors should be connected as close as possible to the terminal. Power supply at CH3 high-side FET from battery Output of CH3. The terminal should be connected to the external inductor. GND for CH3 low-side FET Output for CH8 external low-side FET drive. The terminal is connected to the gate of the low-side external FET. Switching output for CH8 at wake mode. The terminal is switched when the output voltage of CH8 is less than 2.5 V. Output for CH8 external high-side FET drive. The terminal is connected to the gate of the high-side external FET. Power input for IC inside. The terminal should be connected to CH8 output voltage. Output voltage feedback for CH8. The external resistors should be connected as close as possible to the terminal. GND for CH7/8 feedback resistors Brightness adjustment for W-LED Output current feedback for CH7 Input current at CH7 load switch Output voltage feedback for CH7. The external resistors should be connected as close as possible to the terminal. Output of CH7. The terminal should be connected to the external inductor. Power GND for CH5/7. The terminal should be connected by power ground layer at PCB via a through hole. Low-side terminal of coil for CH5 DESCRIPTION
I = input, O = output, I/O = input/output, P = power supply, G = GND Submit Documentation Feedback Product Folder Link(s): TPS65530 3
Copyright ? 2007–2008, Texas Instruments Incorporated
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TERMINAL FUNCTIONS (continued)
TERMINAL NO. 39 40 41 42 43 44 45 46 47 48 Back side NAME SWOUT VCC5 FB5 VCC6 SW6 FB6 S/S56 EN56 SEQ56 VCC4 PowerPAD? I/O (1) O P I P O I I/O I I P G High-side terminal of coil for CH5 Power supply at CH5 high-side FET from battery Output voltage feedback for CH5. The external resistors should be connected as close as possible to the terminal. Power supply at CH6 load switch from battery Output of CH6. The terminal should be connected to the external inductor. Output voltage feedback for CH6. The external resistors should be connected as close as possible to the terminal. Soft-start time adjustment for CH5/6. The time is programmable by external capacitor (see the Soft Start description). Enable for CH5/6 (L: Disable, H: Enable) Sequence select for CH5/6 (see the Power ON/OFF Sequence description) Power supply at CH4 high-side FET from battery Must be soldered to achieve appropriate power dissipation. Should be connected to PGND to use a Φ0.3-mm through hole. DESCRIPTION
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
UNIT VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, SWOUT, FB2, FB4, FB5, FB8, FBC, FBV. PS, XSLEEP, ENAFE, SEQ56, EN56, EN7, SW4S, SW4I, VOUT4, SW2S, SW2I, VOUT2, SW1, SW3, SW8LD, SW8HD, FBG78 (based on PGND or AGND) BADJ, SS, FB1, FB3, FB6, SS56 Input voltage LL8 REF SW5 SW7, CIN SW6 (based on VCC6) PGND1, PGND2, PGND3, PGND4, PGND57, AGND CIN SW2S, SW2I SW4S, SW4I SW1 Switching current SW3 SW5 SW6 SW7 LL8 SW8LD, SW8HD TJ Tstg Maximum junction temperature range Storage temperature range ESD rating, Human-Body Model (HBM) ESD rating, Charged-Device Model (CDM) (1) JEDEC JESD22A-A114 JEDEC JESD22A-C101
–0.3 to 6
–0.3 to 3 –0.3 to 7 –0.3 to 3.6 –0.3 to 22 –0.3 to 27 –20 –0.3 to 0.3 0.05 3.3 1.65 1.9 1 1.6 –1.35 1.2 1 0.6 –30 to 150 –40 to 150 2 500 °C °C kV V A V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Product Folder Link(s): TPS65530
Copyright ? 2007–2008, Texas Instruments Incorporated
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DISSIPATION RATINGS
PACKAGE 48-pin QFN (1) RθJA (1) 27°C/W POWER RATINGS TA < 25°C 2.9 W POWER RATINGS RATE TA > 25°C 0.029°C/W
The thermal resistance, RθJA, is based on a soldered PowerPAD package on a 2S2P JEDEC board (3-in × 3-in, four layers) using thermal vias (0.3-mm diameter × 12 vias)
RECOMMENDED OPERATING CONDITIONS
MIN Supply voltage High-level input voltage Low-level input voltage Operating temperature VCC1, VCC2, VCC4, VCC5 VCC3, VCC6 XSLEEP, ENAFE, EN56, EN7 SEQ56 XSLEEP, ENAFE, EN56, EN7, SEQ56 –25 1.5 2.5 1.4 1.4 REF 0.4 85 MAX 5.5 5.5 UNIT V V V °C
ELECTRICAL CHARACTERISTICS
0°C ≤ TJ ≤ 125°C, 1.8 V ≤ VCC2 ≤ 5 V (unless otherwise noted)
PARAMETER For All Circuits ICC_Iq ICC_sleep Consumption current at PS (pin 29) ICC_PWM ICC_Iq2 ICC_sleep2 Consumption current at VCC2 (pin 12) ICC_PWM2 TSD V(UV_ON) OSC OSC_SUB Iss Thermal shutdown temperature UVLO detect level Internal OSC frequency CH5–8 switching frequency REF output voltage SS source current Pulldown resistance at XSLEEP, ENAFE, EN56, EN7, SEQ56 CH1 VCC1 VOUT1 IOUT1 VFB1 Supply voltage Output voltage (2) Output current (2) FB1 reference voltage Overcurrent protection threshold Overvoltage protection threshold (sensing at FB1 pin) 0.67 VCC1 > 2.4 V, VOUT1 = 1.2 V, Feedback resistance: R1 = 330 k?, R2 = 330 k? No load 0.59 0.6 0.9 0.75 1.5 0.9 5.5 2.5 600 0.61 1.9 0.83 V V mA V A V
(2)
TEST CONDITIONS VCC2 = VPS = 3.6 V, XSLEEP = AGND VCC2 = 3.6 V, VPS = 5 V, XSLEEP = AGND, ENAFE = VCC2 VCC2 = 3.6 V , VPS = 5 V, XSLEEP = VCC2, ENAFE = VCC2, EN56 = VCC2, EN7 = VCC2 VCC2 = VPS = 3.6 V, XSLEEP = AGND VCC2 = 3.6 V, VPS = 5 V, XSLEEP = AGND, ENAFE = VCC2 VCC2 = 3.6 V , VPS = 5 V, XSLEEP = VCC2, ENAFE = VCC2, EN56 = VCC2, EN7 = VCC2 VCC2 from 0 V to 5.5 V, XSLEEP = VCC2 VCC2 from 5.5 V to 0 V VCC2 = 3.6 V OSC = 1.5 MHz, VPS = 5 V XSLEEP = VCC2 S/S = AGND XSLEEP = ENAFE = EN56 = EN7 = SEQ56 = 3 V
MIN
TYP (1) 1 40 20 1 12 0.3 150
MAX 10 70 30 10 30 1
UNIT
μA
mA μA
mA °C
1.25 50 1.35 2.72 6
1.4 100 1.5 750 2.8 10 200
1.55 150 1.65 3.03 14
V mV MHz KHz V μA k?
V(UV_OFF) UVLO hysteresis
(1) (2)
TA = 25°C Specified by design Submit Documentation Feedback Product Folder Link(s): TPS65530 5
Copyright ? 2007–2008, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS (continued)
0°C ≤ TJ ≤ 125°C, 1.8 V ≤ VCC2 ≤ 5 V (unless otherwise noted)
PARAMETER High-side Nch FET ON resistance Trigger voltage to start CH3 Trigger voltage to power off LDO CH2 VCC2 VOUT2 IOUT2 VFB2 Supply voltage Output voltage
(2) (3)
TEST CONDITIONS VPS = 5 V VPS = 5 V
MIN
TYP (1) 320 200 0.48 0.25
MAX 500 250
UNIT m? m? V V
Low-side Nch FET ON resistance (3)
1.5 2.5 VCC2 > 2.4 V, VOUT2 = 3.3 V, Feedback resistance: R1 = 180 k?, R2 = 820 k? No load 0.595 0.605 2.6 0.67 VPS = 5 V VPS = 5 V VPS = 5 V VPS = 5 V VOUT2 = 0.5 V VOUT2 = 0.5 V XSLEEP = AGND, ENAFE = AGND 2.5
(5)
5.5 3.6 600 0.615 3.3 0.83 210
V V mA V A V
Output current (2) FB2 reference voltage Overcurrent protection threshold Overvoltage protection threshold (sensing at FB2 pin) Buck side (3) High-side FET ON resistance Low-side FET ON resistance High-side FET ON resistance Low-side FET ON resistance
0.75 100 450 130 80 0.5
m? 600 240 m? 140 V 1 1 2 5.5 2.5 300 0.59 0.6 0.6 0.67 VPS = 5 V VPS = 5 V XSLEEP = AGND, ENAFE = AGND 0.75 370 300 1 0.48 0.2 1.5 2.2 VCC4 > 2.4 V, VOUT4 = 3.3 V, Feedback resistance: R1 = 82 k?, R2 = 330 k? No load 0.595 100 0.605 5.5 3.6 300 0.615 0.61 1 0.83 750 600 2 μA k? V V mA V A V m? m? k? V V V V mA V
Boost side (4)
Trigger voltage to power off CH3 VOUT2 leakage current Nch FET ON resistance for discharge CH3 VCC3 VOUT3 IOUT3 VFB3 Supply voltage Output voltage
0.9 VCC3 > 2.5 V, VOUT3 = 1.8 V, Feedback resistance: R1 = 220 k?, R2 = 470 k? No load
Output current (5) FB3 reference voltage Overcurrent protection threshold Overvoltage protection threshold (sensing at FB3 pin) High-side Nch FET ON resistance (4) Low-side Nch FET ON resistance (4) Nch FET ON resistance for discharge Trigger voltage to start CH2 Trigger voltage to power off CH1
CH4 VCC4 VOUT4 IOUT4 VFB4 Supply voltage Output voltage (5) Output current (5) FB4 reference voltage
(3) (4) (5) 6
The value of FET ON resistance includes the resistance of bonding wire. The value of FET ON resistance includes the resistance of bonding wire. Specified by design Submit Documentation Feedback Product Folder Link(s): TPS65530
Copyright ? 2007–2008, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS (continued)
0°C ≤ TJ ≤ 125°C, 1.8 V ≤ VCC2 ≤ 5 V (unless otherwise noted)
PARAMETER Overcurrent protection threshold Overvoltage protection threshold (sensing at FB4 pin) Buck side (4) High-side FET ON resistance Low-side FET ON resistance High-side FET ON resistance Low-side FET ON resistance VPS = 5 V VPS = 5 V VPS = 5 V VPS = 5 V VOUT4 = 0.5 V XSLEEP = AGND, ENAFE = AGND 1.5 VCC5 No load VCC5 > 2.4 V, VOUT5 = 15 V, Feedback resistance: R1 = 40 k?, R2 = 560 k? 1.3 1.09 VPS = 5 V 1.5 V < VCC5 < 5.5 V 1.5 V < VCC5 < 5.5 V, SWOUT capacitance = 4.7 μF 1.25 610 100 200 1 96 SEQ56 = AGND 2.5
(6)
TEST CONDITIONS
MIN
TYP (1) 1.4
MAX 1.65 0.83 310
UNIT A V
0.67
0.75 130 600 170 130
m? 730 270 m? 250 1 1 2 5.5 18 1 1.02 50 1.6 1.38 900 470 μA k? V V V mA A V m? m? μS μA % V 5.5 –5 100 –0.02 0 1.1 –0.3 VCC6 = 3.6 V 84 SEQ56 = AGND S/S56 = AGND 0.5 1.22 170 1.5 –0.2 640 91 0.53 1.25 200 0.02 1.35 –0.1 1100 98 0.56 1.28 230 5.5 V V mA V A V m? % V V μA V
Boost side (4)
VOUT4 leakage current Nch FET ON resistance for discharge CH5 VCC5 VOUT5 VFB5 IOUT5 Supply voltage Output voltage (5) FB5 reference voltage Output current (6) Overcurrent protection threshold Overvoltage protection threshold (sensing at FB5 pin) Nch FET ON resistance (7) Load switch ON resistance (between VCC5 and SW5) Load switch ramp-up time (between VCC5 and SW5) (6) Load switch leakage current (between VCC5 and SW5) Max duty cycle Trigger voltage to start up CH6 CH6 VCC6 VOUT6 IOUT6 VFB6 Supply voltage Output voltage
0.98
98 0.8
–10 VCC6 > 2.8 V, VOUT6 = –7.5 V, Feedback resistance: R1 = 136 k?, R2 = 820 k? No load VCC6 > 2.8 V
Output current (6) FB6 reference voltage Overcurrent protection threshold Overvoltage protection threshold (sensing at FB6 pin) Pch FET ON resistance (7) Max duty cycle Trigger voltage to power off CH6
VS/S56 IS/S56 CH7 VCC7 (6) (7)
S/S56 pin voltage S/S56 pin source current Supply voltage (6)
Specified by design The value of FET ON resistance includes the resistance of bonding wire. Submit Documentation Feedback Product Folder Link(s): TPS65530 7
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ELECTRICAL CHARACTERISTICS (continued)
0°C ≤ TJ ≤ 125°C, 1.8 V ≤ VCC2 ≤ 5 V (unless otherwise noted)
PARAMETER VOUT7 IOUT7_L Output voltage
(8)
TEST CONDITIONS VCC7 < VOUT7 VCC7 > 2.4 V, VOUT7 = 15 V, Feedback resistance: R1 = 47 k?, R2 = 680 k?, Rsense = 10 ?, B_ADJ pin voltage = 0 V VCC7 > 2.4 V, VOUT7 = 15 V, Feedback resistance: R1 = 47 k?, R2 = 680 k?, Rsense = 10 ?, B_ADJ pin voltage = 1 V No load
MIN 3 3.7
TYP (1)
MAX 20
UNIT V mA
Lower output current (6)
5
6.3
IOUT7_H VFBV
Higher output current
(6)
23.7 0.97 1.15
25 1 1.25 0.8 700
26.3 1.03 1.35 1.2 1200 99 4 1
mA V V A m? % ? μA mΩ
FBV reference voltage Overvoltage protection threshold (sensing at FBV pin) Overcurrent protection threshold Nch FET ON resistance (7) Max duty cycle Load switch ON resistance Load switch leakage current (between C-IN and FBC)
86
91 2
RB-ADJ CH8
B-ADJ pin input impedance TA = 25°C, Start up (XSLEEP from AGND to VCC2) XSLEEP = VCC2
1
Supply voltage (9) VPS VFB8 Output voltage (9) FB8 reference voltage Fixed ON time at PFM mode Max duty cycle SW8LD driver SW8HD driver Source impedance Sink impedance Source impedance Sink impedance
1.8 1.5 3.3 1.23 1.2 76 1.25 1.25 250 85 5 1 10 5 1.3 1.56 0.6
5.5 5.5 5.5 1.27 1.35 92 7.5 1.5 15 7.5 1.8
V V V ns % ? Ω V k?
XSLEEP = H, ENAFE = AGND, No load CH8 operation mode: PFM mode, No load VCC2 = 3.6 V VPS = 5 V, ISW = 100 mA VPS = 5 V, ISW = –100 mA VPS = 5 V, ISW = 100 mA VPS = 5 V, ISW = –100 mA
Overvoltage protection threshold (sensing at FB8 pin) FBG7/8 FET ON resistance FBG7/8 leakage current (8) (9) VPS = 5 V, XSLEEP = VCC2 XSLEEP = AGND, ENAFE = AGND
1
μA
Due to constant current control for CH7, the operating condition is that Input voltage is less than LED supply voltage (output voltage). Specified by design
8
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BLOCK DIAGRAM
EN56 46 SEQ56 47 48
CP/BST
VCC4
S/S56 45 FB6 44 SW6 43
1
SW4S
CH6 INV
SEQUENCE CONTROL (CH5/6)
CH4 Buck Boost
CP/BST
2
PGND4
3
SW4I
VCC6
42
CH1-6, 8 OCP+ UV X 64
4 5
VOUT4 FB4
FB5 41 VCC5
6
CP
ENAFE XSLEEP EN7 S/S AGND REF
40
TSD
U-SD
7
To CH7
SWOUT 39
CH5 Boost 1.5 MHz OSC
POR S/S, REF
LDO
8 9 10 11
SW5 38
INT Power
PGND5/7 37
1/2
12
CP/BST
VCC2
13
SW2S
SW7 36
FBV CIN
35 34 33
CH7 Boost SEQUENCE CONTROL CH1/2/3 W/ Discharge
From EN7
CH2 Buck Boost
CP/BST
14
GND2
15 SW2I 16 VOUT2 17 FB2
FBC
B- ADJ 32
18
CP/BST
VCC1
FBG7/8
31
PFM
CH1 Buck
19 20 21
SW1
PGND1 FB1
FB8 30 PS 29 SW8HD 28
CH8 Boost
CP/BST
22 23
FB3 VCC3
LL8 27
Start Up
SW8LD 26
EEPROM
CH3 Buck
24 25
SW3 PGND3
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APPLICATION INFORMATION
A. B. C.
When output voltage is higher than input voltage at 2AA battery models, VCC1 and VCC3 should be connected to the CH8 output. When the 2AA battery is connected, VCC6 should be connected to the CH8 output. The external FET for CH8 is dependent on the load. When the motor is connected to CH8, the external FET is large. It is acceptable to connect directly to PS without resistor.
10
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FUNCTIONAL DESCRIPTION Logic True Table
The enable/disable of each channel is controlled by logic input signals level at XSLEEP (pin 7 for all channels), ENAFE (pin 6 for CH4), EN56 (pin 46 for CH5/6) and EN7 (pin 8 for CH7). Table 1 is the summary of the enable/disable mode. Table 1. Control Pin vs Enable/Disable
NO. OF STATE 1 2 3 4 5 6 7 8 9 10 (2) (1) (2) XSLEEP L H H H H H H H H L ENAFE L L L L L H H H H H EN56 – L L H H L L H H – EN7 – L H L H L H L H – CH1 OFF ON ON ON ON ON ON ON ON OFF CH2 OFF ON ON ON ON ON ON ON ON OFF CH3 OFF ON ON ON ON ON ON ON ON OFF CH4 OFF OFF OFF OFF OFF ON ON ON ON OFF CH5 OFF OFF OFF ON ON OFF OFF ON ON OFF CH6 OFF OFF OFF ON ON OFF OFF ON ON OFF CH7 OFF OFF ON OFF ON OFF ON OFF ON OFF CH8 (1) OFF PWM PWM PWM PWM PWM PWM PWM PWM PFM LDO OFF ON ON ON ON ON ON ON ON OFF
PWM = pulse width modulation, PFM = pulse frequency modulation State 10 (CH8: PFM mode) must go through State 2.
Power ON/OFF Sequence
This device has the power ON/OFF sequence of CH1/2/3/8/REF and CH5/6 for DSC application. The CH1/2/3/8/REF sequence is shown in Figure 1. The CH5/6 sequence is shown in Figure 2. CH4 and CH7 have individual sequences but CH4–6 has the subordinate relationship with CH1–3 because the slope of soft start is the same and puts high priority of CH1–3 to avoid the functional conflict (see the Soft Start description). Due to this, CH4–6 should not be ON before CH1–3 is ON. When XSLEEP is forced low, all channels turn OFF with the power OFF sequence.
Figure 1. CH1/CH2/CH3/CH8/REF Power ON/OFF Sequence
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Figure 2. CH5/6 Power ON/OFF Sequence
Soft Start
This function reduces the rush current from the battery at start-up. This device has two slopes, defined by S/S (pin 9) and S/S56 (pin 45). The slopes of CH1–4 are defined by S/S; the slopes of CH5/6 depend on SEQ56 (pin 47) signal level. When SEQ56 is low, the slope of CH5 is defined by S/S; the slope of CH6 is defined by S/S56. When SEQ56 is high, the slopes of CH5/6 are defined by S/S56. The soft-start time is calculated by Equation 1 and Equation 2.
TS/S = CS/S × 60 TS/S56 = CS/S56 × 6.25 (1) (2)
Where: CS/S = Capacitance at S/S [μF] TS/S = Soft-start duration defined by S/S [ms] CS/S56 = Capacitance at S/S56 [μF] TS/S56 = Soft-start duration defined by S/S56 [ms] The recommended capacitances are CS/S = 0.1 [μF] or TS/S = 6.0 [ms], CS/S56 = 1.0 [μF] or TS/S56 = 6.25 [ms].
Undervoltage Lockout (UVLO)
This device monitors the battery voltage level at VCC2 (pin 12). When XSLEEP is high and VCC2 (pin 12) is less than the threshold (defined in Electrical Characteristics as UVLO detect level), the operation shuts down immediately without the power OFF sequence. UVLO has a hysteresis as shown in Figure 3. This factor is defined in Electrical Characteristics as UVLO hysteresis.
Figure 3. UVLO Hysteresis
Protection
The TPS65530 has three protection conditions: overcurrent protection (OCP), overvoltage protection (OVP), and thermal shutdown (TSD) (see Table 2).
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Table 2. Protection Conditions
PROTECTION Change mode Detect condition OCP CH1–CH6 All CH shutdown (latch-off) (without power OFF sequence) Current over the threshold, VOUT less than 80% to compare the target, and count 64 cycle × 1.5 MHz XSLEEP: Change level from Low to High ENAFE: Change level from Low to High (for CH4) EN56: Change level from Low to High (for CH5/6) or VCC2: Apply more than UVLO threshold (1.4 V) after removing VCC2 Forced OFF at applicable CH MOSFET Voltage over the threshold at feedback CH7 CH8 REF (LDO) All CH shutdown All CH shutdown (latch-off) Forced OFF at MOSFET (latch-off) (without power (without power OFF OFF sequence) sequence) Current over the threshold VOUT less than 70% to compare the target VOUT less than 80% to compare the target
Comeback condition
Current less than the threshold (automatic restoration) or VCC2: Apply more than UVLO threshold (1.4 V) after removing VCC2 Forced OFF at MOSFET, load switch turns ON Voltage over the threshold at feedback
XSLEEP: Change level from Low to High ENAFE: Change level from Low to High or VCC2: Apply more than UVLO threshold (1.4 V) after removing VCC2
XSLEEP: Change level from Low to High ENAFE: Change level from Low to High or VCC2: Apply more than UVLO threshold (1.4 V) after removing VCC2
Change mode OVP Detect condition Comeback condition Change mode TSD Detect condition Comeback condition
Forced OFF at MOSFET Voltage over the threshold at feedback Voltage less than the threshold at feedback (auto-recovery) No OVP function
Voltage less than the threshold at EN7: Change level from feedback (auto-recovery) Low to High All CH shutdown (without power OFF sequence) The junction temperature is more than the threshold.
XSLEEP: Change level from Low to High, ENAFE: Change level from Low to High (for CH4), EN56: Change level from Low to High (for CH5/6), or VCC2: More than 1.4 V
CHANNEL DESCRIPTIONS CH1/3 Description
Both CH1 and CH3 are the same topology. CH1/3 are the voltage-mode-controlled synchronous buck converters for engine core (CH1) or external memory (CH3). Both high-side and low-side switches are integrated into the device and consist of NMOS-FET only. The gate of the high-side switch is driven by bootstrap circuit. The capacitance of the bootstrap is included in the device. These channels are able to operate up to 100% duty cycle. This device has a discharge path to use the switch (Q_Discharge1/3) for the CH1/3 output capacitor via the inductor. The switch is activated after the power OFF sequence has started. Typical resistance at the discharge circuit is 1 k?. When the device detects the threshold at FB1/3 after the power OFF sequence has started, the MOSFET turns OFF and the output is fixed with high impedance. It is acceptable to connect the battery to VCC1/VCC3 (pins 18/23) directly when the battery voltage is more than 2.5 V. When the battery voltage is less than 2.5 V, the CH8 output should be connected to VCC1/VCC3. The output voltage is programmed from 0.9 V to 2.5 V (both CH1 and CH3) to use the feedback loop sensed by the external resistances. The output voltage is calculated by Equation 3. The block diagram is shown in Figure 4.
VOUT = (1 + R2/R1) × 0.6 [V] (3)
Where: VOUT = Output voltage [V] R1, R2 = Feedback resistance (see Figure 4)
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Figure 4. CH1/3 Block Diagram CH1/3 Recommended Parts Table 3. Recommended Parts for Inductor (CH1/3)
VENDOR TOKO TYPE NO. DE2812C-1098AS-4R7M INDUCTANCE (μH) 4.7 DCR (m?) 130 SIZE (mm) 2.8 × 3.0 × 1.2
Table 4. Recommended Parts for Capacitor (Input, CH1/3)
VENDOR Murata TYPE NO. GRM21BB30J226ME38 CAPACITANCE (μF) 22.0 TOLERANCE (%) 20 SIZE (mm) 2.0 × 1.25 × 1.25 (EIA code: 0805)
Table 5. Recommended Parts for Capacitor (Output, CH1/3)
VENDOR TDK TYPE NO. C2012X5R0J106M CAPACITANCE (μF) 10.0 TOLERANCE (%) 20 SIZE (mm) 2.0 × 1.25 × 1.25 (EIA code: 0805)
CH2/4 Description
Both CH2 and CH4 are the same topology. CH2/4 are the average current-mode-controlled synchronous back-boost converters for engine I/O (CH2) or AFE (CH4). This converter is an adapted H-bridge circuit to use four switches. These switches are integrated into the device and consist of NMOS-FET only. The gate of the high-side switch is controlled by the bootstrap circuit. The capacitance of the bootstrap is included in the device. The device automatically switches from buck operation to boost operation or from boost operation to buck operation as required by the configuration. It always uses one active switch, one rectifying switch, one switch permanently on, and one switch permanently off. Therefore, it operates as a buck converter when the input voltage is higher than the output voltage, and as a boost converter when the input voltage is lower than the output voltage. There is no mode of operation in which all four switches are permanently switching.
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This device has a discharge switch (Q_Discharge2/4) for the CH2/4 output capacitor. The typical ON resistance at the discharge switch is 1 k?. The discharge switch is activated when XSLEEP turns low. For CH4 only, the switch is also activated when ENAFE turns low. After output voltage reaches approximately 0.5 V, the discharge switch turns OFF and VOUT2/VOUT4 is changed into high impedance. The output voltage is programmable from 2.5 V to 3.6 V (for CH2) or from 2.2 V to 3.6 V (for CH4) to use the feedback loop sensed by the external resistances. The output voltage is calculated by Equation 4. The block diagram is shown in Figure 5.
VOUT = (1 + R2/R1) × 0.6 [V] (4)
Where: VOUT = Output voltage [V] R1, R2 = Feedback resistance (see Figure 5)
Figure 5. CH2/4 Block Diagram
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CH2/4 Recommended Parts Table 6. Recommended Parts for Inductor (CH2)
VENDOR TOKO TYPE NO. DE2812C-1098AS-2R7M INDUCTANCE (μH) 2.7 DCR (m?) 72 SIZE (mm) 2.8 × 3.0 × 1.2
Table 7. Recommended Parts for Inductor (CH4)
VENDOR TOKO TYPE NO. DE2812C-1098AS-4R7M INDUCTANCE (μH) 4.7 DCR (m?) 130 SIZE (mm) 2.8 × 3.0 × 1.2
Table 8. Recommended Parts for Capacitor (Input, CH2/4)
VENDOR Murata TYPE NO. GRM21BB30J226ME38 CAPACITANCE (μF) 22.0 TOLERANCE (%) 20 SIZE (mm) 2.0 × 1.25 × 1.25 (EIA code: 0805)
Table 9. Recommended Parts for Capacitor (Output, CH2/4)
VENDOR Taiyo Yuden TYPE NO. JMK212BJ476MG-T CAPACITANCE (μF) 47.0 TOLERANCE (%) 20 SIZE (mm) 2.0 × 1.25 × 1.25 (EIA code: 0805)
CH5 Description
CH5 is the peak current-mode-controlled nonsynchronous boost converter for CCD+. The switch between inductor and power GND is integrated into the device and consists of NMOS-FET. Also, this device has a load switch between the battery and inductor and consists of NMOS-FET. The gate of the switch is controlled by a charge-pump circuit. The output voltage is programmable up to 18 V to use the feedback loop sensed by the external resistances. The output voltage is calculated by Equation 5. The block diagram is shown in Figure 6.
VOUT5 = (1 + R2/R1) × 1.0 [V] (5)
Where: VOUT5 = Output voltage of CH5 [V] R1, R2 = Feedback resistance (see Figure 6)
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Figure 6. CH5 Block Diagram CH5 Recommended Parts Table 10. Recommended Parts for Inductor (CH5)
VENDOR TOKO TYPE NO. DE2812C-1098AS-120M INDUCTANCE (μH) 12.0 DCR (m?) 340 SIZE (mm) 2.8 × 3.0 × 1.2
Table 11. Recommended Parts for Capacitor (Output, CH5)
VENDOR Murata TYPE NO. GRM31CB31E106KA75 CAPACITANCE (μF) 10.0 TOLERANCE (%) 10 SIZE (mm) 3.2 × 1.6 × 1.6 (EIA code: 1206)
Table 12. Recommended Parts for Capacitor (SWOUT, CH5)
VENDOR TDK TYPE NO. C2012X5R1A335M CAPACITANCE (μF) 3.3 TOLERANCE (%) 20 SIZE (mm) 2.0 × 1.25 × 1.25 (EIA code: 0805)
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Table 13. Recommended Parts for Diode (CH5)
VENDOR Sanyo TYPE NO. SB0503EJ VR (V) 30 IF (mA) 500 VF (V)/IF (A) 0.55/0.5 CAPACITANCE (pF) 16.5 SIZE (mm) 1.6 × 0.8 × 0.6
CH6 Description
CH6 is the voltage-mode-controlled nonsynchronous inverting converter for CCD–. The switch between the input voltage and inductor is integrated into the device and consists of PMOS-FET. It is acceptable to connect the battery to VCC6 (pin 42) directly when the battery voltage is more than 2.5 V. When the battery voltage is less than 2.5 V, the CH8 output should be connected to VCC6. The output voltage is programmable from –10 V to –5 V to use the feedback loop sensed by the external resistances. The output voltage is calculated by Equation 6. The block diagram is shown in Figure 7.
VOUT6 = 1.25 – (1 + R2/R1) × 1.25 [V] (6)
Where: VOUT6 = Output voltage of CH6 [V] R1, R2 = Feedback resistance (see Figure 7)
Figure 7. CH6 Block Diagram CH6 Recommended Parts Table 14. Recommended Parts for Inductor (CH6)
VENDOR TOKO TYPE NO. DE2815C-1071AS-120M INDUCTANCE (μH) 12.0 DCR (m?) 240 SIZE (mm) 2.8 × 3.0 × 1.2
Table 15. Recommended Parts for Capacitor (Input, CH6)
VENDOR Murata TYPE NO. GRM21BB31A106KE18 CAPACITANCE (μF) 10.0 TOLERANCE (%) 10 SIZE (mm) 2.0 × 1.25 × 1.25 (EIA code: 0805)
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Table 16. Recommended Parts for Capacitor (Output, CH6)
VENDOR Murata TYPE NO. GRM31CB31E106KA75 CAPACITANCE (μF) 10.0 TOLERANCE (%) 10 SIZE (mm) 3.2 × 1.6 × 1.6 (EIA code: 1206)
Table 17. Recommended Parts for Diode (CH6)
VENDOR Sanyo TYPE NO. SB0503EJ VR (V) 30 IF (mA) 500 VF (V)/IF (A) 0.55/0.5 CAPACITANCE (pF) 16.5 SIZE (mm) 1.6 × 0.8 × 0.6
CH7 Description
CH7 is the voltage-mode-controlled nonsynchronous boost converter for the backlight LED. The switch between the inductor and power GND is integrated into the device and consists of NMOS-FET. Also, this device has a load switch to control the output current and consists of NMOS-FET. The output current is constant and is calculated by Equation 7. It is controlled by the B_ADJ (pin 32) input voltage as shown in Figure 8. The B_ADJ input voltage is required as an analog input. When it is required to input PWM signal for B_ADJ, the RC filter is needed.
ILED =
Where:
0.2 0.05 ? VBADJ + RSENSE RSENSE
(7)
ILED = Output current of CH7 [A] RSENSE = Sense resistor between FBC and PGND5/7 [?] VBADJ = B_ADJ input voltage (0 < VBADJ < 1) [V]
Figure 8. Output Current vs B_ADJ Input Voltage (RSENSE = 10 ?) The principle of the operation is to adjust the duty cycle of the MOSFET. When the B_ADJ input voltage is changed, the level of “A” point shown in Figure 9 is changed to get the desired duty cycle compared to the sense current.
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Figure 9. LED Brightness Control Block Diagram At first, CH7 operates as pulse frequency modulation (PFM) mode at start-up. After reaching the target output voltage, CH7 operation is changed from PFM mode to pulse width modulation (PWM) mode automatically. The output voltage is programmable up to 20 V to use the feedback loop sensed by the external resistances. The maximum output voltage is calculated by Equation 8. The block diagram is shown in Figure 10.
VOUT7
MAX
= 1 + (R2/R1) × 1.25 [V]
(8)
Where: VOUT7
MAX
= Maximum output voltage of CH7 [V]
R1, R2 = Feedback resistance (see Figure 10)
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