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VHDL设计数码管扫描显示

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SCAN IS
PORT ( CLK : IN STD_LOGIC;
DIG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;
ARCHITECTURE BEHAV OF SCAN IS
SIGNAL CN: STD_LOGIC_VECTOR(2 DOWNTO 0);
--SIGNAL H: INTEGER RANGE 0 TO 15;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK ='1' THEN CN <= CN+1;
IF CN > "111" THEN CN <= "000";
END IF;
END IF;
CASE CN IS
WHEN "000" => DIG<="00000001"; --H<=2;
WHEN "001" => DIG<="00000010"; --H<=3;
WHEN "010" => DIG<="00000100"; --H<=6;
WHEN "011" => DIG<="00001000"; --H<=8;
WHEN "100" => DIG<="00010000"; --H<=9;
WHEN "101" => DIG<="00100000"; --H<=10;
WHEN "110" => DIG<="01000000"; --H<=11;
WHEN "111" => DIG<="10000000"; --H<=12;
WHEN OTHERS => NULL;
END CASE;
END PROCESS ;
END;

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