File Number3142.2 HI-506, HI-507, HI-508, HI-509
Single16and8/Differential8-Channel and 4-Channel CMOS Analog Multiplexers
The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS multiplexers each include an array of sixteen and eight analog switches respectively, a digital decoder circuit for channel selection,voltage reference for logic thresholds,and an enable input for device selection when several multiplexers are present. The Dielectric Isolation (DI) process used in fabrication of these devices eliminates the problem of latchup. DI also offers much lower substrate leakage and parasitic capacitance than conventional junction isolated CMOS (see Application Notes AN520 and AN521).
The switching threshold for each digital input is established by an internal +5V reference, providing a guaranteed minimum 2.4V for logic “1” and maximum 0.8V for logic “0”. This allows direct interface without pullup resistors to signals from most logic families: CMOS, TTL, DTL and some PMOS. For protection against transient overvoltage, the digital inputs include a series 200? resistor and diode clamp to each supply.
The HI-506 is a single 16-Channel, the HI-507 is an
8-Channel differential, the HI-508 is a single 8-Channel and the HI-509 is a 4-Channel differential multiplexer.
If input overvoltages are present, the HI-546/HI-547/HI-548/ HI-549 multiplexers are recommended.Features
?Low ON Resistance. . . . . . . . . . . . . . . . . . . . . . . . . 180??Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . . ±15V ?TTL/CMOS Compatible
?Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns ?Maximum Power Supply. . . . . . . . . . . . . . . . . . . . . . . .44V ?Break-Before-Make Switching
?No Latch-Up
?Replaces DG506A/DG506AA and DG507A/DG507AA ?Replaces DG508A/DG508AA and DG509A/DG509AA Applications
?Data Acquisition Systems
?Precision Instrumentation
?Demultiplexing
?Selector Switch
Ordering Information
PART NUMBER
TEMP.
RANGE (o C)PACKAGE
PKG.
NO.
HI9P0506-9-40 to 8528 Ld SOIC M28.3
HI3-0506-50 to 7528 Ld PDIP E28.6
HI4P0506-50 to 7528 Ld PLCC N28.45
HI1-0506-50 to 7528 Ld CERDIP F28.6
HI1-0506-4-25 to 8528 Ld CERDIP F28.6
HI1-0506-2-55 to 12528 Ld CERDIP F28.6
HI4P0507-50 to 7528 Ld PLCC N28.45
HI3-0507-50 to 7528 Ld PDIP E28.6
HI1-0507-2-55 to 12528 Ld CERDIP F28.6
HI1-0508-50 to 7516 Ld CERDIP F16.3
HI3-0508-50 to 7516 Ld PDIP E16.3
HI1-0508-4-25 to 8516 Ld CERDIP F16.3
HI1-0508-2-55 to 12516 Ld CERDIP F16.3
HI4P0508-50 to 7520 Ld PLCC N20.35
HI9P0508-9-40 to 8516 Ld SOIC M16.15 HI9P0508-50 to 7516 Ld SOIC M16.15 HI9P0509-50 to 7516 Ld SOIC M16.15 HI1-0509-4-25 to 8516 Ld CERDIP F16.3
HI1-0509-50 to 7516 Ld CERDIP F16.3
HI3-0509-50 to 7516 Ld PDIP E16.3
HI4P0509-50 to 7520 Ld PLCC N20.35
HI1-0509-2-55 to 12516 Ld CERDIP F16.3
Data Sheet June 1999元器件交易网https://www.doczj.com/doc/0c6094607.html,
Pinouts
HI-506 (PDIP, CERDIP, SOIC)
TOP VIEW
HI-507
(PDIP, CERDIP) TOP VIEW
HI-506 (PLCC) TOP VIEW
HI-507 (PLCC) TOP VIEW
+V SUPPL Y
NC
NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
GND
NC ADDRESS A3
OUT
IN 8
IN 7
IN 6
IN 5
IN 3
IN 1
ENABLE
ADDRESS A0
ADDRESS A1
ADDRESS A2
-V SUPPL Y
IN 4
IN 2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+V SUPPLY
OUT B
NC
IN 8B
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
IN 2B
IN 1B
GND
NC
NC
OUT A
IN 8A
IN 7A
IN 6A
IN 5A
IN 3A
IN 1A
ENABLE
ADDRESS A0
ADDRESS A1
ADDRESS A2
-V SUPPL Y
IN 4A
IN 2A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
IN 15 IN 14 IN 13 IN 12 IN 11 IN 10 IN 9
I
N
1
6
N
C
N
C
+
V
S
U
P
P
L
Y
O
U
T
-
V
S
U
P
P
L
Y
I
N
8
G
N
D
N
C
A
3
A
2
A
1
E
N
A
B
L
E
A
IN 7
IN 6
IN 5
IN 4
IN 3
IN 2
IN 1
11
10
5
6
7
8
9
23
24
25
22
21
20
19
1415161718
1213
321
4282726
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
IN 2B
IN 1B
I
N
8
B
N
C
O
U
T
B
+
V
S
U
P
P
L
Y
O
U
T
A
-
V
S
U
P
P
L
Y
I
N
8
A
G
N
D
N
C
N
C
A
2
A
1
E
N
A
B
L
E
A
IN 7A
IN 6A
IN 5A
IN 4A
IN 3A
IN 2A
IN 1A
11
10
5
6
7
8
9
23
24
25
22
21
20
19
1415161718
1213
321
4282726
HI-508
(PDIP, CERDIP, SOIC)
TOP VIEW
HI-509
(PDIP, CERDIP, SOIC)
TOP VIEW
HI-508(PLCC)TOP VIEW
HI-509(PLCC)TOP VIEW
Pinouts
(Continued)
141516913121110123
45768
A 0ENABLE -V SUPPL Y IN 1IN 2IN 3OUT IN 4A 1GND +V SUPPL Y IN 5IN 6IN 7IN 8
A 2141516913121110123
45768
A 0ENABLE -V SUPPLY IN 1A IN 2A IN 3A OUT A IN 4A A 1+V SUPPL Y IN 1
B IN 2B IN 3B IN 4B OUT B
GND -V SUPPL Y
IN 1NC IN 2IN 3
E N A B L E
A 0
N C
A 1
A 2
I N 4
O U T
N C
I N 8
I N 7
GND +V SUPPLY NC IN 5IN 6
45678
1011121393
2120
19
1617181514-V SUPPLY
IN 1A NC IN 2A IN 3A
E N A B L E
A 0
N C A 1
G N D I N 4A
O U T A
N C
O U T B
I N 4B
+V SUPPL Y IN 1B NC IN 2B IN 3B 45678
10111213932120
19
1617181514
Truth Tables
HI-506
A3A2A1A0EN“ON” CHANNEL X X X X L None
L L L L H1
L L L H H2
L L H L H3
L L H H H4
L H L L H5
L H L H H6
L H H L H7
L H H H H8
H L L L H9
H L L H H10
H L H L H11
H L H H H12
H H L L H13
H H L H H14
H H H L H15
H H H H H16
HI-507
A2A1A0EN“ON” CHANNEL X X X L None
L L L H1
L L H H2
L H L H3
L H H H4
H L L H5
H L H H6
H H L H7
H H H H8
HI-508
A2A1A0EN“ON” CHANNEL X X X L None
L L L H1
L L H H2
L H L H3
L H H H4
H L L H5
H L H H6
H H L H7
H H H H8
HI-509
A1A0EN“ON” CHANNEL PAIR X X L None
L L H1
L H H2
H L H3
H H H4
Functional Diagrams
HI-506
HI-507
HI-508HI-509
DECODER/DRIVER
????
OUT IN 1IN 2
IN 16
? DIGITAL
PROTECTION
A 0A 1A 2A 3
?
EN
INPUT
LEVEL SHIFT
5V REF
DECODER/DRIVER
?
?
?
OUT B
IN 8A IN 1A IN 1B
? DIGITAL
PROTECTION
A 0
A 1
A 2
?
EN
INPUT
LEVEL SHIFT
5V REF OUT A
IN 8B
DECODER/DRIVER
?
?
?
OUT IN 1IN 2
IN 8
? DIGITAL
PROTECTION
A 0
A 1
A 2
?
EN
INPUT
LEVEL SHIFT
5V REF DECODER/DRIVER
?
?
OUT B
IN 4A IN 1A IN 1B
? DIGITAL
PROTECTION
A 0
A 1
?
EN
INPUT
LEVEL SHIFT
5V REF OUT A
IN 4B
Schematic Diagrams
ADDRESS DECODER
ADDRESS INPUT BUFFER LEVEL SHIFTER
TTL REFERENCE CIRCUIT
MULTIPLEX SWITCH
P
N
A 0 OR A 0
TO N-CHANNEL DEVICE OF THE SWITCH
A 1 OR A 1
A 2 OR A 2
A 3 OR A 3
ENABLE
P
P
P
P
P
P
V+
V-
N
N
N
N
N N
TO P-CHANNEL DEVICE OF THE SWITCH
DELETE A 3 OR A 3 INPUT FOR HI-507, HI-508, HI-509DELETE A 2 OR A 2 INPUT FOR HI-509
V+P3
D1
D2
200?
A IN
V R ALL N-CHANNEL BODIES TO V-ALL P-CHANNEL BODIES TO V+UNLESS OTHERWISE INDICATED
A
V-P1
N1
V L P2
N2
N3
V-
V+
P4
P5
P6
P7
P8
P9
P10
N6
N7
N8N9N10
N4
N5
A
V L
Q9P
Q10N N13
N14
P15
Q1P
N15
Q5N
D3
Q11P
R36.8K
P16
R216.8K Q12N
Q6N Q2P V+
Q3P
Q4P
N12
Q7P
V-GND
Q8N
V R
FROM DECODE
V+
N18
N19
P17
N17
V-P18
OUT
FROM DECODE
IN
Absolute Maximum Ratings Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V V+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V Digital Input Voltage (V EN, V A) . . . . .(V-) -4V to (V+) +4V or 20mA,
Whichever Occurs First Analog Signal (V IN, V OUT, Note 2) . . . . . . . . . .(V-) -2V to (V+) +2V Continuous Current, In or Out . . . . . . . . . . . . . . . . . . . . . . . . .20mA Peak Current, In or Out (Pulsed 1ms, 10% Duty Cycle Max) .40mA Operating Conditions
Temperature Ranges
HI-506/507/508/509-2 . . . . . . . . . . . . . . . . . . . . .-55o C to 125o C HI-506/508/509-4. . . . . . . . . . . . . . . . . . . . . . . . . .-25o C to 85o C HI-506/507/508/509-5 . . . . . . . . . . . . . . . . . . . . . . . .0o C to 75o C HI-506/508-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40o C to 85o C Thermal Resistance (T ypical, Note 1)θJA (o C/W)θJC (o C/W) 16 Ld CERDIP Package. . . . . . . . . . . .8532
16 Ld SOIC Package . . . . . . . . . . . . . .115N/A
16 Ld PDIP Package . . . . . . . . . . . . . .100N/A
20 Ld PLCC Package. . . . . . . . . . . . . .80N/A
28 Ld CERDIP Package. . . . . . . . . . . .5518
28 Ld PDIP Package . . . . . . . . . . . . . .60N/A
28 Ld SOIC Package . . . . . . . . . . . . . .70N/A
28 Ld PLCC Package. . . . . . . . . . . . . .70N/A Maximum Junction T emperature
Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175o C Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150o C Maximum Storage Temperature Range. . . . . . . . . .-65o C to 150o C Maximum Lead T emperature (Soldering 10s) . . . . . . . . . . . . .300o C (SOIC and PLCC - Lead Tips Only)
CAUTION:Stresses above those listed in“Absolute Maximum Ratings”may cause permanent damage to the device.This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied.
NOTES:
1.θJA is measured with the component mounted on an evaluation PC board in free air.
2.Signals on IN or OUT exceeding V+or V-are clamped by internal diodes.Limit resulting current to maximum current ratings.If an overvoltage
condition is anticipated (analog input exceeds either power supply voltage), the Harris HI-546/HI-547/HI-548/HI-549 multiplexers are recommended.
Electrical Speci?cations Supplies = +15V, -15V; V AH (Logic Level High) = 2.4V; V AL (Logic Level Low) = 0.8V,
Unless Otherwise Speci?ed. For Test Conditions, Consult Test Circuits Section
PARAMETER
TEST
CONDITIONS
TEMP
(o C)
-2-4, -5, -9
UNITS
MIN TYP MAX MIN TYP MAX
DYNAMIC CHARACTERISTICS
Access Time, t A25-250500-250-ns
Full--1000--1000ns Break-Before-Make Delay, t OPEN252580-2580-ns Enable Delay (ON), t ON(EN)25-250500-250-ns
Full--1000--1000ns Enable Delay (OFF), t OFF(EN)25-250500-250-ns
Full--1000--1000ns
Settling Time, t S (HI-506 and HI-507)To 0.1%25- 1.2-- 1.2-μs To 0.01%25- 2.4-- 2.4-μs
Settling Time, t S (HI-508 and HI-509)To 0.1%25-360--360-ns To 0.01%25-600--600-ns
Off Isolation Note 6255068-5068-dB Channel Input Capacitance, C S(OFF)25-10--10-pF Channel Output Capacitance, C D(OFF)
HI-50625-52--52-pF HI-50725-30--30-pF HI-50825-17--17-pF HI-50925-12--12-pF Digital Input Capacitance, C A25-6--6-pF Input to Output Capacitance, C DS(OFF)25-0.08--0.08-pF
DIGITAL INPUT CHARACTERISTICS Input Low Threshold, V AL Full --0.8--0.8V Input High Threshold, V AH Full
2.4-- 2.4--V Input Leakage Current (High or Low), I A
Note 5
Full
-
-
1.0
-
-
1.0
μA
ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, V IN Full
-15-+15-15-+15V On Resistance, r ON Note 3
25-180300-180400??r ON , (Any Two Channels)25
-5--5-%Off Input Leakage Current, I S(OFF)
Note 4
25-0.03--0.03-nA Full
--50--50nA Off Output Leakage Current,I D(OFF )
Note 425-0.3--0.3-nA HI-506Full --300--300nA HI-507Full --200--200nA HI-508Full --200--200nA HI-509
Full
--100--100nA On Channel Leakage Current, I D(ON)
Note 425-0.3--0.3-nA HI-506Full --300--300nA HI-507Full --200--200nA HI-508Full --200--200nA HI-509
Full --100--100nA Differential Off Output Leakage Current,I DIFF (HI-507, HI-509 Only)
Full
-
-
50
-
-
50
nA
POWER SUPPLY CHARACTERISTICS Current, I+
HI-506/HI-507Note 7Full - 1.5 3.0- 1.5 3.0mA HI-508/HI-509Note 7
Full
-
1.5
2.4
-
1.5
2.4
mA
Current, I-HI-506/HI-507Note 7Full -0.4 1.0-0.4 1.0mA HI-508/HI-509Note 7
Full
-
0.4
1.0
-
0.4
1.0
mA
Power Dissipation, P D
HI-506/HI-507Full --60--60mW HI-508/HI-509Full
-
-
51
-
-
51
mW
NOTES:
3.V OUT =±10V , I OUT =+1mA.
4.10nA is the practical lower limit for high speed measurement in the production test environment.
5.Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25o C.
6.V EN = 0.8V, R L = 1K, C L = 15pF, V S = 7V RMS , f = 100kHz.
7.V EN , V A = 0V or 2.4V.
Electrical Speci?cations
Supplies = +15V , -15V; V AH (Logic Level High) = 2.4V; V AL (Logic Level Low) = 0.8V ,
Unless Otherwise Speci?ed. For Test Conditions, Consult Test Circuits Section (Continued)
PARAMETER
TEST CONDITIONS
TEMP (o C)
-2
-4, -5, -9UNITS
MIN
TYP
MAX
MIN
TYP
MAX
Test Circuits and Waveforms
T A = 25o C, V SUPPL Y =±15V , V AH = 2.4V , V AL = 0.8V , Unless Otherwise Specified
FIGURE 1A.TEST CIRCUIT
FIGURE 1B.ON RESISTANCE vs ANALOG INPUT VOLTAGE
FIGURE 1C.NORMALIZED ON RESISTANCE vs SUPPL Y
VOLTAGE
FIGURE 1.ON RESISTANCE
FIGURE 2A.LEAKAGE CURRENT vs TEMPERATURE
FIGURE 2B.I D(OFF) TEST CIRCUIT (NOTE 8)
1mA
OUT
IN V IN
r ON =
V 21mA
V 2
400
300
200
100
0-15
ANALOG INPUT (V)
O N R E S I S T A N C E (?)
-10
-5051015
125o C
25o C
-55o C
2.22.01.81.61.41.21.00.80.6
N O R M A L I Z E D R E S I S T A N C E (R E F E R R E D T O V A L U E A T ±15V )
7
8
9
10
11
12
13
14
15
SUPPLY VOLTAGE (±V)
-55o C TO 125o C V IN = 0V
100nA
10nA 1nA
100pA
10pA
L E A K A G E C U R R E N T
255075100125
TEMPERATURE (o C)
OFF OUTPUT
LEAKAGE CURRENT
I D(OFF)
I D(ON)
OFF INPUT
LEAKAGE CURRENT I S(OFF)
A
+10V
±10V
0.8V
EN
OUT
I D(OFF)
FIGURE 2C.I S(OFF) TEST CIRCUIT (NOTE 8)FIGURE 2D.I D(ON) TEST CIRCUIT (NOTE 8)
FIGURE 2.LEAKAGE CURRENTS
NOTE:
8.Two measurements per channel:±10V and +10V. (Two measurements per device for I D(OFF)±10V and +10V)
FIGURE 3A.ON CHANNEL CURRENT vs VOLTAGE
FIGURE 3B.TEST CIRCUIT
FIGURE 3.ON CHANNEL CURRENT
FIGURE 4A.SUPPLY CURRENT vs TOGGLE FREQUENCY
FIGURE 4B.TEST CIRCUIT
FIGURE 4.DYNAMIC SUPPL Y CURRENT
+10V
±10V
0.8V
EN
A
OUT
I S(OFF)
OUT
I D(ON)
A
+10V
±10V
2.4V
EN
A 0
A 1
706050
403020100
02
46810121416
VOLTAGE ACROSS SWITCH (±V)
S W I T C H C U R R E N T (m A )
-55o C
25o C
125o C
A
±V IN
8
6
4
2
1K
TOGGLE FREQUENCY (Hz)
S U P P L Y C U R R E N T (m A )
10K 100K
1M
10M
V SUPPL Y =±15V
V SUPPL Y =±10V
±10V/±5V
+15V/+10V
V+V-IN 1
IN 2IN 8/16
OUT A 0
EN
A 11014M ?
pF
A 3A 2
50?
V A
3.5V
GND
A
-15V/-10V
A
-I SUPPLY +I SUPPL Y
+10V/+5V
V A
HIGH = 3.5V LOW = 0V
50% DUTY CYCLE
THRU IN 7/15HI-506?
?Similar connection for HI-507/HI-508/
HI-509
FIGURE 5A.ACCESS TIME vs LOGIC LEVEL (HIGH)FIGURE 5B.TEST CIRCUIT
FIGURE 5C.MEASUREMENT POINTS
FIGURE 5D.WAVEFORMS
FIGURE 5.ACCESS TIME
FIGURE 6A.TEST CIRCUIT
600
400
200
02
A C C E S S T I M E (n s )
LOGIC LEVEL (HIGH) (V)
3
4515
14
13±10V
+15V
V+V-
IN 1IN 2 THRU
IN 16
OUT A 0
EN
A 11050k ?pF
A 3
A 2
50?
V A
3.5V
GND
-15V
+10V
IN 7/15HI-506?
?Similar connection for HI-507/HI-508/
HI-509
50%
3.5V
10%
+10V
0V
OUTPUT -10V
t A
ADDRESS DRIVE (V A )
200ns/DIV.
S 1 ON
S 16 ON
V A INPUT 2V/DIV .OUTPUT 5V/DIV.
+15V
V+
V-IN 1
IN 2 THRU IN 8 /16
OUT A 0
EN
A 150pF
200?
V OUT
-15V
A 3A 2
50?
V A
3.5V GND
+5V
IN 7/IN 15HI-506?
?Similar connection for HI-507/HI-508/HI-509
FIGURE 6B.MEASUREMENT POINTS
FIGURE 6C.WAVEFORMS
FIGURE 6.BREAK-BEFORE-MAKE DELAY
FIGURE 7A.TEST CIRCUIT
FIGURE 7B.MEASUREMENT POINTS
FIGURE 7C.WAVEFORMS
FIGURE 7.ENABLE DELAYS
50%50%
3.5V
0V
OUTPUT
ADDRESS DRIVE (V A )
t OPEN
S 1 ON
S 16 ON
V A INPUT 2V/DIV.
OUTPUT 1V/DIV .
100ns/DIV.
+15V
V+
V-IN 1
IN 2 THRU IN 8 /16
OUT A 0EN
A 150pF
200?
V OUT
-15V
A 3A 2
V A
GND
+10V
IN 7/IN 15HI-506?
?Similar connection for HI-507/HI-508/HI-509
50?
3.5V
0V OUTPUT t OFF(EN)
ENABLE DRIVE (V A )
10%
50%50%
90%
t ON(EN)
0V
DISABLED
OUTPUT 2V/DIV .
ENABLE DRIVE 2V/DIV .
ENABLED (S 1 ON)
100ns/DIV
Typical Performance Curves
T A = 25o C, V SUPPL Y =±15V , V AH = 2.4V , V AL = 0.8V , Unless Otherwise Specified
FIGURE 8.LOGIC THRESHOLD vs POWER SUPPL Y VOLTAGE FIGURE 9.OFF ISOLATION vs FREQUENCY
FIGURE 10A.HI-506/HI-507FIGURE 10B.HI-508/HI-509
FIGURE 10.POWER SUPPL Y CURRENT vs TEMPERATURE
68
101214161820
POWER SUPPL Y VOLTAGE (±V)
I N P U T L O G I C T H R E S H O L D (V )
43
2
1
100
80
60
40
20
0104
(V S ), (V D ) O F F I S O L A T I O N (d B )
105106107
FREQUENCY (Hz)
V EN = 0V
C LOA
D = 28pF V S = 7V RMS
R L = 1K
R L = 10M
32
1
0P O W E R S U P P L Y C U R R E N T (m A )
-55
TEMPERATURE (o C)
-35-15
-545256585105125
V EN = 2.4V
V EN = 0V
3
2
1
0-55
P O W E R S U P P L Y C U R R E N T (m A )
TEMPERATURE (o C)
-35-15
-5254565
85105125
EN = 5V
EN = 0V
129 mils x 82 mils METALLIZATION:T ype: CuAl
Thickness: 16k ?±2k ?SUBSTRATE POTENTIAL (NOTE):-V SUPPL Y
Type: Nitride/Silox
Nitride Thickness:3.5k ?±1k ?Silox Thickness:12k ?±2k ?WORST CASE CURRENT DENSITY:1.4 x 105 A/cm 2TRANSISTOR COUNT:421PROCESS:CMOS-DI
NOTE:The substrate appears resistive to the -V SUPPL Y terminal,therefore it may be left ?oating (Insulating Die Mount)or it may be mounted on a conductor at -V SUPPL Y potential.
Metallization Mask Layout
HI-506
HI-507
+V IN 16IN 15
IN 14IN 13
IN 12IN 11IN 10IN 9GND
NC
A 3
OUT IN 8IN 7
IN 6IN 5IN 3IN 1EN A 0
A 1
A 2
-V IN 4IN 2
+V IN 8B
IN 7B
IN 6B IN 5B
IN 4B IN 3B IN 2B IN 1B GND
OUT B
NC
OUT A IN 8A IN 7A
IN 6A IN 5A IN 3A IN 1A EN
A 0
A 1
A 2-V IN 4A IN 2A
81.9 mils x 90.2 mils METALLIZATION:T ype: CuAl
Thickness: 16k ?±2k ?SUBSTRATE POTENTIAL (NOTE):-V SUPPL Y
Type: Nitride/Silox
Nitride Thickness:3.5k ?±1k ?Silox Thickness:12k ?±2k ?WORST CASE CURRENT DENSITY:1.4 x 105 A/cm 2TRANSISTOR COUNT:234PROCESS:CMOS-DI
NOTE:The substrate appears resistive to the -V SUPPL Y terminal,therefore it may be left ?oating (Insulating Die Mount)or it may be mounted on a conductor at -V SUPPL Y potential.
Metallization Mask Layout
HI-508
HI-509
+V SUP GND
OUT
IN 8
IN 7
IN 6
IN 5IN 3
IN 1EN A 0A 1
A 2
-V SUP IN 4IN 2+V SUP GND
OUT A
IN 4B
IN 3B
IN 2B
IN 1B IN 3A
IN 1A EN A 0A 1
-V SUP IN 4A IN 2A OUT B
C L E
e A
C
e B
e C
-B-E1
INDEX 123
N/2
N
AREA
SEATING BASE PLANE PLANE
-C-D1B1
B
e
D
D1
A
A2
L A 1
-A-0.010 (0.25)C A M
B S
NOTES:
1.Controlling Dimensions:INCH.In case of conflict between English and Metric dimensions, the inch dimensions control.
2.Dimensioning and tolerancing per ANSI Y14.5M -1982.
3.Symbols are defined in the “MO Series Symbol List”in Section 2.2 of Publication No. 95.
4.Dimensions A,A1and L are measured with the package seated in JEDEC seating plane gauge GS -3.
5.D, D1, and E1 dimensions do not include mold flash or protru-sions.Mold flash or protrusions shall not exceed 0.010inch (0.25mm).
6.E and are measured with the leads constrained to be per-pendicular to datum .
7.e B and e C are measured at the lead tips with the leads uncon-strained. e C must be zero or greater.
8.B1maximum dimensions do not include dambar protrusions.Dambar protrusions shall not exceed 0.010 inch (0.25mm).9.N is the maximum number of terminal positions.
10.Corner leads (1,N,N/2and N/2+1)for E8.3,E16.3,E18.3,
E28.3,E42.6will have a B1dimension of 0.030-0.045inch (0.76 - 1.14mm).
e A -C-E8.3(JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS NOTES MIN MAX MIN MAX A -0.210- 5.334A10.015-0.39-4A20.1150.195 2.93 4.95-B 0.0140.0220.3560.558-B10.0450.070 1.15 1.778, 10C 0.0080.0140.2040.355-D 0.3550.4009.0110.165D10.005-0.13-5E 0.3000.3257.628.256E10.240
0.280
6.10
7.11
5e 0.100 BSC 2.54 BSC -e A 0.300 BSC 7.62 BSC
6e B -0.430-
10.927L 0.115
0.150
2.93
3.814N
8
8
9
Rev. 0 12/93
NOTES:
1.Controlling Dimensions:INCH.In case of conflict between English and Metric dimensions, the inch dimensions control.
2.Dimensioning and tolerancing per ANSI Y14.5M -1982.
3.Symbols are defined in the “MO Series Symbol List”in Section 2.2of Publication No. 95.
4.Dimensions A,A1and L are measured with the package seated in JEDEC seating plane gauge GS -3.
5.D,D1,and E1dimensions do not include mold flash or protrusions.Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6.E and are measured with the leads constrained to be perpendic-ular to datum .
7.e B and e C are measured at the lead tips with the leads unconstrained.e C must be zero or greater.
8.B1maximum dimensions do not include dambar protrusions.Dambar protrusions shall not exceed 0.010 inch (0.25mm).9.N is the maximum number of terminal positions.
10.Corner leads (1,N,N/2and N/2+1)for E8.3,E16.3,E18.3,E28.3,
E42.6will have a B1dimension of 0.030-0.045inch (0.76-1.14mm).
e A -C-C L E
e A
C
e B
e C
-B-E1
INDEX 123
N/2
N
AREA
SEATING BASE PLANE PLANE
-C-D1B1
B
e
D
D1
A
A2
L A1
-A-0.010 (0.25)C A M
B S
E28.6(JEDEC MS-001-BF ISSUE D)
28 LEAD NARROW BODY DUAL-IN-LINE PLASTIC
PACKAGE
SYMBOL
INCHES
MILLIMETERS NOTES MIN MAX MIN MAX A -0.250- 6.354A10.015-0.39-4A20.1250.195 3.18 4.95-B 0.0140.0220.3560.558-B10.0300.0700.77 1.778C 0.0080.0150.2040.381-D 1.380 1.56535.139.75D10.005-0.13-5E 0.6000.62515.2415.876E10.485
0.580
12.32
14.73
5e 0.100 BSC 2.54 BSC -e A 0.600 BSC 15.24 BSC
6e B -0.700-
17.787L 0.115
0.200
2.93
5.084N
28
289
Rev. 0 12/93
NOTES:
1.Symbols are defined in the “MO Series Symbol List”in Section
2.2of Publication Number 95.
2.Dimensioning and tolerancing per ANSI Y14.5M -1982.
3.Dimension “D”does not include mold flash,protrusions or gate burrs.Mold flash,protrusion and gate burrs shall not exceed 0.15mm (0.006inch) per side.
4.Dimension “E”does not include interlead flash or protrusions.Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5.The chamfer on the body is optional.If it is not present,a visual index feature must be located within the crosshatched area.
6.“L” is the length of terminal for soldering to a substrate.
7.“N” is the number of terminal positions.
8.Terminal numbers are shown for reference only.
9.The lead width “B”,as measured 0.36mm (0.014inch)or greater above the seating plane,shall not exceed a maximum value of 0.61mm (0.024 inch).
10.Controlling dimension:MILLIMETER.Converted inch dimensions are
not necessarily exact.
INDEX AREA
E D
N
1
2
3
-B-0.25(0.010)C A M
B S
e
-A-L
B
M
-C-A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
0.25(0.010)B M
M
α
M16.15(JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS NOTES
MIN MAX MIN MAX A
0.05320.0688 1.35 1.75-A10.00400.00980.100.25-B 0.0130.0200.330.519C 0.00750.00980.190.25-D 0.38590.39379.8010.003E
0.14970.1574 3.80 4.004e 0.050 BSC 1.27 BSC
-H 0.22840.2440 5.80 6.20-h 0.00990.01960.250.505L 0.016
0.0500.40
1.276N
16167α
0o
8o
0o
8o
-Rev. 0 12/93
NOTES:
1.Symbols are defined in the “MO Series Symbol List”in Section
2.2of Publication Number 95.
2.Dimensioning and tolerancing per ANSI Y14.5M -1982.
3.Dimension “D”does not include mold flash,protrusions or gate burrs.Mold flash,protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4.Dimension “E” does not include interlead flash or protrusions. In-terlead flash and protrusions shall not exceed 0.25mm (0.010inch) per side.
5.The chamfer on the body is optional.If it is not present,a visual index feature must be located within the crosshatched area.
6.“L” is the length of terminal for soldering to a substrate.
7.“N” is the number of terminal positions.
8.Terminal numbers are shown for reference only.
9.The lead width “B”,as measured 0.36mm (0.014inch)or greater above the seating plane,shall not exceed a maximum value of 0.61mm (0.024 inch)
10.Controlling dimension:MILLIMETER. Converted inch dimen-sions are not necessarily exact.
INDEX AREA
E D
N
1
2
3
-B-0.25(0.010)C A M
B S
e
-A-L
B
M
-C-A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
0.25(0.010)B M
M
α
M28.3(JEDEC MS-013-AE ISSUE C )
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS NOTES
MIN MAX MIN MAX A 0.09260.1043 2.35 2.65-A1
0.00400.01180.100.30-B 0.0130.02000.330.519C 0.00910.01250.230.32-D 0.69690.712517.7018.103E 0.29140.29927.407.604e
0.05 BSC 1.27 BSC
-H 0.3940.41910.0010.65-h 0.010.0290.250.755L 0.016
0.0500.40
1.276N
28287α
0o
8o
0o
8o
-Rev. 0 12/93
A1A
SEATING PLANE
0.020 (0.51)MIN VIEW “A”
D2/E2
0.025 (0.64)
0.045 (1.14)
R
0.042 (1.07)
0.056 (1.42)
0.050 (1.27) TP
E
E10.042 (1.07)0.048 (1.22)
PIN (1) IDENTIFIER
C L
D1
D
0.020 (0.51) MAX 3 PLCS
0.026 (0.66)0.032 (0.81)
0.045 (1.14)MIN
0.013 (0.33)0.021 (0.53)
0.025 (0.64)MIN
VIEW “A” TYP.
0.004 (0.10)
C
-C-D2/E2
C L
NOTES:
1.Controlling dimension:INCH.Converted millimeter dimensions are not necessarily exact.
2.Dimensions and tolerancing per ANSI Y14.5M-1982.
3.Dimensions D1and E1do not include mold protrusions.Allowable mold protrusion is 0.010inch (0.25mm)per side.Dimensions D1and E1include mold mismatch and are measured at the extreme material condition at the body parting line.
4.To be measured at seating plane contact point.
5.Centerline to be determined where center leads exit plastic body.
6.“N” is the number of terminal positions.
-C-N20.35(JEDEC MS-018AA ISSUE A)
20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
SYMBOL
INCHES
MILLIMETERS NOTES
MIN MAX MIN MAX A 0.1650.180 4.20 4.57-A1
0.0900.120 2.29 3.04-D 0.3850.3959.7810.03-D10.3500.3568.899.043D20.1410.169 3.59 4.294, 5E 0.3850.3959.7810.03-E10.3500.3568.899.043E20.141
0.169
3.59
4.29
4, 5N
20
20
6
Rev. 211/97