Integrated Circuit
Systems, Inc.
ICS843001-21
F EMTO C LOCKS ? C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
G ENERAL D ESCRIPTION
The ICS843001-21 is a a highly versatile, low
phase noise LVPE CL Synthesizer which can generate low jitter reference clocks for a variety
of communications applications and is a member of the HiPerClocks TM family of high performance clock solutions from ICS. The dual
crystal interface allows the synthesizer to support up to two communications standards in a given application (i.e.1GB Ethernet with a 25MHz crystal and 1Gb Fibre Channel using a 25.5625MHz crystal). The rms phase jitter performance is typically less than 1ps, thus making the device acceptable for use in demanding applications such as OC48 SONET and 10Gb Ethernet. The ICS843001-21is packaged in a small 24-pin TSSOP package.
F EATURES
?One 3.3V LVPECL output pair and one L VCMOS output ?Selectable crystal oscillator interface or LVCMOS/L VTTL single-ended input ?VCO range: 560MHz - 700MHz ?Supports the following applications:
SONET , Ethernet, Fibre Channel, Serial A TA, and HDTV ?RMS phase jitter @ 622.08MHz (12kHz - 20MHz):0.80ps (typical)Offset Noise Power 100Hz...............-60.3 dBc/Hz 1kHz...............-88.5 dBc/Hz 10kHz.............-111.9 dBc/Hz 100kHz.............-113.0 dBc/Hz ?Full 3.3V supply mode
?0°C to 70°C ambient operating temperature
?Available in both standard and lead-free RoHS-compliant packages
P IN A SSIGNMENT
24-Lead TSSOP
package body G Package T op View
V CCO _CMOS
N0N1N2
V CCO _PECL
Q0nQ0V EE V CCA 123456789101112
REF_CLK V EE
REF_OE M2M1M0MR SEL1SEL0
TEST_CLK XTAL_IN0XTAL_OUT0
242322212019181716151413
B LOCK D IAGRAM
Q0nQ0
REF_CLK
Integrated Circuit
Systems, Inc.
ICS843001-21
F EMTO C LOCKS ? C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
T ABLE 1. P IN D ESCRIPTIONS
T ABLE 2. P IN C HARACTERISTICS
r
e b m u N e m a N e
p y T n
o i t p i r c s e D 1V S O M C _O C C r
e w o P .
t u p t u o S O M C V L r o f n i p y l p p u s t u p t u O 3,21N ,0N t u p n I p
u l l u P .
4÷t l u a f e D .s n i p t c e l e s r e d i v i d t u p t u O .
s l e v e l e c a f r e t n i L T T V L /S O M C V L 42N t u p n I n w o d l l u P 5V L C E P V L _O C C r e w o P .
t u p t u o L C E P V L r o f n i p y l p p u s t u p t u O 7,60Q n ,0Q t u p u O .s l e v e l e c a f r e t n i L C E P V L .r i a p t u p t u o l a i t n e r e f f i D 32,8V E E r e w o P .n i p y l p p u s e v i t a g e N 9V A
C C r e w o P .
n i p y l p p u s g o l a n A 01V C
C r e w o P .
n i p y l p p u s e r o C 1121,1T U O _L A T X 1N I _L A T X t u p n I ,t u p t u o e h t s i 1T U O _L A T X .e c a f r e t n i l a t s y r c t n a n o s e r l e l l a r a P .
t u p n i e h t s i 1N I _L A T X 3141,0T U O _L A T X 0N I _L A T X t u p n I ,t u p t u o e h t s i 0T U O _L A T X .e c a f r e t n i l a t s y r c t n a n o s e r l e l l a r a P .
t u p n i e h t s i 0N I _L A T X 51K L C _T S E T t u p n I n w o d l l u P .
t u p n i k c o l c L T T V L /S O M C V L 71,611
L E S ,0L E S t u p n I n w o d l l u P .
s l e v e l e c a f r e t n i L T T V L /S O M C V L .s n i p t c e l e s X U M t u p n I 81R M t u p n I n
w o d l l u P e r a s r e d i v i d l a n r e t n i e h t ,H G I H c i g o l n e h W .t e s e R r e t s a M H G I H e v i t c A 0
Q n t u p t u o d e t r e v n i e h t d n a w o l o g o t 0Q t u p t u o e u r t e h t g n i s u a c t e s e r e r a s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t ,W O L c i g o l n e h W .h g i h o g o t .
s l e v e l e c a f r e t n i L T T V L /S O M C V L .d e l b a n e 02,911M ,0M t u p n I n w o d l l u P .
23÷t l u a f e D .s n i p t c e l e s r e d i v i d k c a b d e e F .s l e v e l e c a f r e t n i L T T V L /S O M C V L 122M t u p n I p u l l u P 22E O _F E R t u p n I n
w o d l l u P .w o L t l u a f e D .e l b a n e t u p t u o k c o l c e c n e r e f e R .
s l e v e l e c a f r e t n i L T T V L /S O M C V L 4
2K
L C _F E R t u p t u O .
s l e v e l e c a f r e t n i L T T V L /S O M C V L .t u p t u o k c o l c e c n e r e f e R :E T O N n w o d l l u P d n a p u l l u P .
s e u l a v l a c i p y t r o f ,s c i t s i r e t c a r a h C n i P ,2e l b a T e e S .s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y S r e t e m a r a P s
n o i t i d n o C t s e T m
u m i n i M l a c i p y T m
u m i x a M s t i n U C N
I e c n a t i c a p a C t u p n I 4F p R N W O D L L U P r o t s i s e R n w o d l l u P t u p n I 15k ΩR P U L L U P r o t s i s e R p u l l u P t u p n I 15k ΩR t
u o e
c n a
d
e p m I t u p t u O 7
Ω
Integrated Circuit
Systems, Inc.
ICS843001-21
F EMTO C LOCKS ? C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
T ABLE 3A. C OMMON C ONFIGURATIONS T ABLE
t u p n I e
u l a V r e d i v i D M e
u l a V r e d i v i D N )
z H M (O C V y
c n e u q e r F t u p t u O )
z H M (n o i t a c i l p p A k
c o l C e c n e r e f e R 7222849552.47V T D H 57.4242849552.47V T D H 9461538.410486604.3955428571.47V T D H 44.9123480.22625.551T E N O S 44.9123880.22667.77T E N O S 44.9123180.22680.226T E N O S 44.9123280.22640.113T E N O S 52135.9123452652.651E g i G 0152525526521E g i G 152********.26E g i G 152426006001s
s e r p x E I C P 52424006051A T A S 5242800657A T A S 5265.624265.73652.6011l e n n a h C e r b i F 5265.624235.7365.212l e n n a h C e r b i F g i G 45265.624245.736573.951l e n n a h C e r b i F g i G 015
2.138
13
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e n r e h t E g i G 21s t u p n I r e d i v i D M e
u l a V y c n e u q e r F t u p n I 2M 1M 0M m u m i n i M m u m i x a M 000811.139.83001225.528.13010423.322.92011524.220.82100235.719.121
1
40
.415
.71T ABLE 3B.P ROGRAMMABLE M O UTPUT D IVIDER
F UNCTION T ABLE
T ABLE 3C.P ROGRAMMABLE N O UTPUT D IVIDER
F UNCTION T ABLE
s t u p n I e c n e r e f e R e d o M L L P 1L E S 0L E S 000L A T X e v i t c A 011L A T X e v i t c A 10K L C _T S E T e v i t c A 1
1
K
L C _T S E T s
s a p y B T ABLE 3D. B YPASS M ODE F UNCTION T ABLE
s t u p n I e
u l a V e d i v i D N 2N 1N 0N 00010012010301141005101611081
1
1
1
Integrated Circuit
Systems, Inc.
ICS843001-21
F EMTO C LOCKS ? C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
T ABLE 4A. P OWER S UPPL Y DC C HARACTERISTICS , V CC = V CCA = V CCO = 3.3V±5%, TA = 0°C TO 70°C
T ABLE 4B. LVCMOS / LVTTL DC C HARACTERISTICS , V CC = V CCA = V CCO = 3.3V±5%, TA = 0°C TO 70°C
l o b m y S r
e t e m a r a P s
n o i t i d n o C t s e T m u m i n i M l
a c i p y T m u m i x a M s t i n U V H I e
g a t l o V h g i H t u p n I 2V C C 3.0+V V L
I t u p n I e
g a t l o V w o L ,
F E R _E O ,1L E S ,0L E S 2N :0N ,2M :0M ,R M 3.0-8.0V K
L C _T S E T 3
.0-3.1V I H
I t u p n I t
n e r r u C h g i H ,
1L E S ,0L E S ,K L C _T S E T 2N ,1M ,0M ,R M ,F E R _E O V C C V =N I V 564.3=051A μ1N ,0N ,2M V C C V =N I V 564.3=5
A μI L I t
u p n I t
n e r r u C w o L ,1L E S ,0L E S ,K L C _T S E T 2N ,1M ,0M ,R M ,F E R _E O V C C V ,V 564.3=N I V 0=5-A μ1
N ,0N ,2M V C C V ,V 564.3=N I V
0=051-A μV H
O 1
E T O N ;e g a t l o V h g i H t u p t u O K
L C _F E R 6
.2V V L O 1e t o N :e g a t l o V w o L t u p t u O K
L C _F E R 5.0V
05h t i w d e t a n i m r e t t u p t u O :1E T O N ΩV o t S O M C _O C C ,n o i t c e S n o i t a m r o f n I t n e m e r u s a e M r e t e m a r a P e e S .2/.
"m a r g a i D t i u c r i C t s e T d a o L t u p t u O V 3.3"A BSOLUTE M AXIMUM R ATINGS
Supply Voltage, V CC 4.6V
Inputs, V I
-0.5V to V CC + 0.5V Outputs, I O (LVPECL) Continuous Current 50mA Surge Current 100mA
Outputs, V O (LVCMOS)
-0.5V to V CCO + 0.5V Package Thermal Impedance, θJA 70°C/W (0 mps)Storage Temperature, T STG
-65°C to 150°C
NOTE : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be-yond those listed in the DC Characteristics or AC Character-istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
l o b m y S r
e t e m a r a P s
n o i t i d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s t i n U V C C e g a t l o V y l p p u S e r o C 531.33.3564.3V V A
C C e g a t l o V y l p p u S g o l a n A 531.33.3564.3V V S O M C _,L C E P _O C C e g a t l o V y l p p u S t u p t u O 5
31.33
.3564.3V I E E t n e r r u C y l p p u S r e w o P 071A m I A
C C t n e r r u C y l p p u S g o l a n A 11A m I S
O M C _,L C E P _O C C t
n e r r u C y l p p u S t u p t u O 8
A
m
Integrated Circuit
Systems, Inc.
ICS843001-21
F EMTO C LOCKS ? C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
T ABLE 6. AC C HARACTERISTICS , V CC = V CCA = V CCO = 3.3V±5%, TA = 0°C TO 70°C
T ABLE 5. C RYSTAL C HARACTERISTICS
r e t e m a r a P s
n o i t i d n o C t s e T m
u m i n i M l
a c i p y T m
u m i x a M s t i n U n o i t a l l i c s O f o e d o M l
a t n e m a d n u F z H M y
c n e u q e r F 2
104z H M )R S E (e c n a t s i s e R s e i r e S t n e l a v i u q E 05Ωe
c n a t i c a p a C t n u h S 7
F
p .
l a t s y r c t n a n o s e r l e l l a r a p F p 81n a g n i s u d e z i r e t c a r a h C :E T O N T ABLE 4C. LVPECL DC C HARACTERISTICS , V CC = V CCA = V CCO = 3.3V±5%, TA = 0°C TO 70°C
l o b m y S r
e t e m a r a P s
n o i t i d n o C t s e T m u m i n i M l
a c i p y T m u m i x a M s t i n U V H O 1E T O N ;e g a t l o V h g i H t u p t u O V O C C 4.1-V O C C 9.0-V V L O 1E T O N ;e g a t l o V w o L t u p t u O V O C C 0.2-V O C C 7.1-V V G
N I W S g
n i w S e g a t l o V t u p t u O k a e P -o t -k a e P 6
.00
.1V
05h t i w d e t a n i m r e t s t u p t u O :1E T O N ΩV o t L C E P _O C C .
V 2-l o b m y S r
e t e m a r a P s
n o i t i d n o C t s e T m
u m i n i M l
a c i p y T m u m i x a M s t i n U f T U O y
c n e u q e r F t u p t u O 65007z H M t D P ,y a l e D n o i t a g a p o r P 1E T O N o t K L C _T S E T K L C _F E R 3
.28
.2s n t )?(t i j ;)m o d n a R (,r e t t i J e s a h P S M R 3
,2E T O N )
z H M 02-z H k 21(z H M 80.2260
8.0s p f O C V e g n a R k c o L O C V L L P 0
65007z H M t R t /F t
u p t u O e m i T l l a F /e s i R L C E P V L %08o t %02002005s p S
O M C V L %
08o t %02003008s p c
d o e
l c y C y t u D t u p t u O L C E P V L 5455%S
O M C V L 4
46
5%
V e h t m o r f d e r u s a e M :1E T O N C C V o t t u p n i e h t f o 2/S O M C _O C C .t u p t u o e h t f o 2/.
l a t s y r c z t r a u q z H M 44.91a g n i s u d e r u s a e m r e t t i j e s a h P :2E T O N .
56d r a d n a t S C E D E J h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h T :3E T O N
Integrated Circuit
Systems, Inc.
ICS843001-21
F EMTO C LOCKS ? C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
T YPICAL P HASE N OISE AT 622.08MH Z
622.08MHz
RMS Phase Jitter (Random)12kHz to 20MHz = 0.80ps (typical)
O FFSET F REQUENCY (H Z )
d B c H z
N O I S E P O W E R 0-10-20-30-40-50-60-70-80-90-100-110-120
-130-140-150-160-170-180-190
100
1k
10k
100k
1M
10M
100M
Phase Noise Result by adding Sonet OC-12 Filter to raw data Raw Phase Noise Data
OC-12 Filter
?
?
?
Integrated Circuit
Systems, Inc.
ICS843001-21
F EMTO C LOCKS ? C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
P ARAMETER M EASUREMENT I NFORMATION
Integrated Circuit
Systems, Inc.
ICS843001-21
F EMTO C LOCKS ? C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
C RYSTAL I NPUT I NTERFACE
The ICS843001-21 has been characterized with 18pF paral-lel resonant crystals. The capacitor values shown in Figure 2
below were determined using a 19.44MHz, 18pF parallel reso-nant crystal and were chosen to minimize the ppm error.
A PPLICATION I NFORMATION
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843001-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC , V CCA , and V CCO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance,power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each V CCA . The 10Ω resis-tor can also be replaced by a ferrite bead.
P OWER S UPPL Y F ILTERING T ECHNIQUES
F IGURE 1. P OWER S UPPL Y F
ILTERING
Integrated Circuit
Systems, Inc.
ICS843001-21
F EMTO C LOCKS ? C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
T ERMINATION FOR 3.3V LVPECL O UTPUT
The clock layout topology shown below is a typical ter-mination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.FOUT and nFOUT are low impedance follower outputs that generate E CL/LVPE CL compatible outputs. There-fore, terminating resistors (DC current path to ground)or current sources must be used for functionality. These
F IGURE 3B. L VPECL O UTPUT T ERMINATION
F IGURE 3A. LVPECL O UTPUT T ERMINATION outputs are designed to drive 50Ω transmission lines.Matched impedance techniques should be used to maxi-mize operating frequency and minimize signal distor-tion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compat-ibility across all printed circuit and clock component pro-cess variations.
I NPUTS :C RYSTAL I NPUT :
For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating.Though not required, but for additional protection, a 1k Ωresistor can be tied from XT AL_IN to ground.
TEST_CLK I NPUT :
For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k Ω resistor can be tied from the TEST_CLK to ground.
LVCMOS C ONTROL P INS :
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k Ω resistor can be used.
R ECOMMENDATIONS FOR U NUSED I NPUT AND O UTPUT P INS O UTPUTS :
LVCMOS O UTPUT :
All unused LVCMOS output can be left floating. We recommend that there is no trace attached.
LVPECL O UTPUT
All unused LVPE CL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
Integrated Circuit
Systems, Inc.
ICS843001-21
F EMTO C LOCKS ? C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
P OWER C ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843001-21.Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843001-21 is the sum of the core power plus the power dissipated in the load(s).The following is the power dissipation for V CC = 3.3V + 5% = 3.465V , which gives worst case results.NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
?Power (core)MAX = V CC_MAX * I EE_MAX = 3.465V * 170mA = 589.05mW ?
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power _MAX (3.465V , with all outputs switching) = 589.05mW + 30mW = 619.05mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)T A = Ambient T emperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per T able 7 below.Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.619W * 65°C/W = 110.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,and the type of board (single layer or multi-layer).
T ABLE 7. T HERMAL R ESISTANCE θJA FOR 24-PIN TSSOP, F ORCED C ONVECTION
θJA by Velocity (Meters per Second)
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
Integrated Circuit
Systems, Inc.
ICS843001-21
F EMTO C LOCKS ? C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.LVPECL output driver circuit and termination are shown in Figure 4.
T o calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V CC
- 2V .
?
For logic high, V OUT = V OH_MAX
= V
CC_MAX
– 0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
?
For logic low, V OUT = V OL_MAX
= V
CC_MAX
– 1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.Pd_L is the power dissipation when the output drives low.Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC _MAX
- V
OH_MAX
))/R L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC _MAX
- V
OL_MAX
))/R L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
Integrated Circuit
Systems, Inc.
ICS843001-21
F EMTO C LOCKS ? C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
R ELIABILITY I NFORMATION
T RANSISTOR C OUNT
The transistor count for ICS843001-21 is: 4057
T ABLE 8. θJA VS . A IR F LOW T ABLE FOR 24 L EAD TSSOP
θJA by Velocity (Meters per Second)
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
?
C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
P ACKAGE O UTLINE - G S UFFIX FOR 24 L EAD TSSOP
T ABLE 9. P ACKAGE D IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O B M Y S s
r e t e m i l l i M m
u m i n i M m
u m i x a M N 4
2A --02.11A 50.051.02A 08.050.1b 91.003.0c 90.002.0D 0
7.709.7E C
I S A B 04.61E 0
3.40
5.4e C
I S A B 56.0L 54.057.0α°0°8a
a a --0
1.0
Integrated Circuit
Systems, Inc.
ICS843001-21
F EMTO C LOCKS ? C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
T ABLE 10. O RDERING I NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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ICS843001-21
F EMTO C LOCKS ? C RYSTAL -TO -3.3V LVPECL
F REQUENCY S YNTHESIZER
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