TEXAS INSTRUMENTS-PRODUCTION DATA
Stellaris?LM3S9C97Microcontroller
DATA SHEET
Copyright?2007-2012 DS-LM3S9C97-11425
Copyright
Copyright?2007-2012Texas Instruments Incorporated All rights reserved.Stellaris and StellarisWare?are registered trademarks of Texas Instruments Incorporated.ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited.Other names and brands may be claimed as the property of others.
PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
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Austin,TX78746
https://www.doczj.com/doc/071660374.html,/stellaris
https://www.doczj.com/doc/071660374.html,/sc/technical-support/product-information-centers.htm
Stellaris?LM3S9C97Microcontroller
Table of Contents
Revision History (41)
About This Document (44)
Audience (44)
About This Manual (44)
Related Documents (44)
Documentation Conventions (45)
1Architectural Overview (47)
1.1Overview (47)
1.2Target Applications (49)
1.3Features (49)
1.3.1ARM Cortex-M3Processor Core (49)
1.3.2On-Chip Memory (51)
1.3.3Serial Communications Peripherals (52)
1.3.4System Integration (58)
1.3.5Advanced Motion Control (64)
1.3.6Analog (66)
1.3.7JTAG and ARM Serial Wire Debug (67)
1.3.8Packaging and Temperature (68)
1.4Hardware Details (68)
2The Cortex-M3Processor (69)
2.1Block Diagram (70)
2.2Overview (71)
2.2.1System-Level Interface (71)
2.2.2Integrated Configurable Debug (71)
2.2.3Trace Port Interface Unit(TPIU) (72)
2.2.4Cortex-M3System Component Details (72)
2.3Programming Model (73)
2.3.1Processor Mode and Privilege Levels for Software Execution (73)
2.3.2Stacks (73)
2.3.3Register Map (74)
2.3.4Register Descriptions (75)
2.3.5Exceptions and Interrupts (88)
2.3.6Data Types (88)
2.4Memory Model (88)
2.4.1Memory Regions,Types and Attributes (90)
2.4.2Memory System Ordering of Memory Accesses (91)
2.4.3Behavior of Memory Accesses (91)
2.4.4Software Ordering of Memory Accesses (92)
2.4.5Bit-Banding (93)
2.4.6Data Storage (95)
2.4.7Synchronization Primitives (96)
2.5Exception Model (97)
2.5.1Exception States (98)
2.5.2Exception Types (98)
2.5.3Exception Handlers (101)
Table of Contents
2.5.4Vector Table (101)
2.5.5Exception Priorities (102)
2.5.6Interrupt Priority Grouping (103)
2.5.7Exception Entry and Return (103)
2.6Fault Handling (105)
2.6.1Fault Types (106)
2.6.2Fault Escalation and Hard Faults (106)
2.6.3Fault Status Registers and Fault Address Registers (107)
2.6.4Lockup (107)
2.7Power Management (107)
2.7.1Entering Sleep Modes (108)
2.7.2Wake Up from Sleep Mode (108)
2.8Instruction Set Summary (109)
3Cortex-M3Peripherals (112)
3.1Functional Description (112)
3.1.1System Timer(SysTick) (112)
3.1.2Nested Vectored Interrupt Controller(NVIC) (113)
3.1.3System Control Block(SCB) (115)
3.1.4Memory Protection Unit(MPU) (115)
3.2Register Map (120)
3.3System Timer(SysTick)Register Descriptions (122)
3.4NVIC Register Descriptions (126)
3.5System Control Block(SCB)Register Descriptions (139)
3.6Memory Protection Unit(MPU)Register Descriptions (168)
4JTAG Interface (178)
4.1Block Diagram (179)
4.2Signal Description (179)
4.3Functional Description (180)
4.3.1JTAG Interface Pins (180)
4.3.2JTAG TAP Controller (182)
4.3.3Shift Registers (182)
4.3.4Operational Considerations (183)
4.4Initialization and Configuration (185)
4.5Register Descriptions (186)
4.5.1Instruction Register(IR) (186)
4.5.2Data Registers (188)
5System Control (190)
5.1Signal Description (190)
5.2Functional Description (190)
5.2.1Device Identification (191)
5.2.2Reset Control (191)
5.2.3Non-Maskable Interrupt (196)
5.2.4Power Control (196)
5.2.5Clock Control (197)
5.2.6System Control (205)
5.3Initialization and Configuration (206)
5.4Register Map (207)
5.5Register Descriptions (208)
Stellaris?LM3S9C97Microcontroller 6Hibernation Module (297)
6.1Block Diagram (298)
6.2Signal Description (298)
6.3Functional Description (299)
6.3.1Register Access Timing (299)
6.3.2Hibernation Clock Source (300)
6.3.3System Implementation (301)
6.3.4Battery Management (302)
6.3.5Real-Time Clock (302)
6.3.6Battery-Backed Memory (303)
6.3.7Power Control Using HIB (303)
6.3.8Power Control Using VDD3ON Mode (303)
6.3.9Initiating Hibernate (303)
6.3.10Waking from Hibernate (303)
6.3.11Interrupts and Status (304)
6.4Initialization and Configuration (304)
6.4.1Initialization (304)
6.4.2RTC Match Functionality(No Hibernation) (305)
6.4.3RTC Match/Wake-Up from Hibernation (305)
6.4.4External Wake-Up from Hibernation (306)
6.4.5RTC or External Wake-Up from Hibernation (306)
6.5Register Map (306)
6.6Register Descriptions (307)
7Internal Memory (324)
7.1Block Diagram (324)
7.2Functional Description (324)
7.2.1SRAM (325)
7.2.2ROM (325)
7.2.3Flash Memory (327)
7.3Register Map (332)
7.4Flash Memory Register Descriptions(Flash Control Offset) (334)
7.5Memory Register Descriptions(System Control Offset) (346)
8Micro Direct Memory Access(μDMA) (370)
8.1Block Diagram (371)
8.2Functional Description (371)
8.2.1Channel Assignments (372)
8.2.2Priority (373)
8.2.3Arbitration Size (373)
8.2.4Request Types (374)
8.2.5Channel Configuration (375)
8.2.6Transfer Modes (376)
8.2.7Transfer Size and Increment (385)
8.2.8Peripheral Interface (385)
8.2.9Software Request (385)
8.2.10Interrupts and Errors (386)
8.3Initialization and Configuration (386)
8.3.1Module Initialization (386)
8.3.2Configuring a Memory-to-Memory Transfer (387)
Table of Contents
8.3.3Configuring a Peripheral for Simple Transmit (388)
8.3.4Configuring a Peripheral for Ping-Pong Receive (390)
8.3.5Configuring Channel Assignments (392)
8.4Register Map (392)
8.5μDMA Channel Control Structure (394)
8.6μDMA Register Descriptions (401)
9General-Purpose Input/Outputs(GPIOs) (431)
9.1Signal Description (431)
9.2Functional Description (435)
9.2.1Data Control (437)
9.2.2Interrupt Control (438)
9.2.3Mode Control (439)
9.2.4Commit Control (439)
9.2.5Pad Control (440)
9.2.6Identification (440)
9.3Initialization and Configuration (440)
9.4Register Map (441)
9.5Register Descriptions (444)
10General-Purpose Timers (487)
10.1Block Diagram (487)
10.2Signal Description (488)
10.3Functional Description (491)
10.3.1GPTM Reset Conditions (491)
10.3.2Timer Modes (491)
10.3.3DMA Operation (498)
10.3.4Accessing Concatenated Register Values (498)
10.4Initialization and Configuration (499)
10.4.1One-Shot/Periodic Timer Mode (499)
10.4.2Real-Time Clock(RTC)Mode (500)
10.4.3Input Edge-Count Mode (500)
10.4.4Input Edge Timing Mode (501)
10.4.5PWM Mode (501)
10.5Register Map (502)
10.6Register Descriptions (503)
11Watchdog Timers (534)
11.1Block Diagram (535)
11.2Functional Description (535)
11.2.1Register Access Timing (536)
11.3Initialization and Configuration (536)
11.4Register Map (536)
11.5Register Descriptions (537)
12Analog-to-Digital Converter(ADC) (559)
12.1Block Diagram (560)
12.2Signal Description (561)
12.3Functional Description (563)
12.3.1Sample Sequencers (563)
12.3.2Module Control (564)
Stellaris?LM3S9C97Microcontroller 12.3.3Hardware Sample Averaging Circuit (566)
12.3.4Analog-to-Digital Converter (567)
12.3.5Differential Sampling (571)
12.3.6Internal Temperature Sensor (573)
12.3.7Digital Comparator Unit (574)
12.4Initialization and Configuration (578)
12.4.1Module Initialization (578)
12.4.2Sample Sequencer Configuration (579)
12.5Register Map (579)
12.6Register Descriptions (581)
13Universal Asynchronous Receivers/Transmitters(UARTs) (640)
13.1Block Diagram (641)
13.2Signal Description (641)
13.3Functional Description (643)
13.3.1Transmit/Receive Logic (643)
13.3.2Baud-Rate Generation (644)
13.3.3Data Transmission (645)
13.3.4Serial IR(SIR) (645)
13.3.5ISO7816Support (646)
13.3.6Modem Handshake Support (646)
13.3.7LIN Support (648)
13.3.8FIFO Operation (649)
13.3.9Interrupts (650)
13.3.10Loopback Operation (651)
13.3.11DMA Operation (651)
13.4Initialization and Configuration (651)
13.5Register Map (652)
13.6Register Descriptions (654)
14Synchronous Serial Interface(SSI) (704)
14.1Block Diagram (705)
14.2Signal Description (705)
14.3Functional Description (706)
14.3.1Bit Rate Generation (707)
14.3.2FIFO Operation (707)
14.3.3Interrupts (707)
14.3.4Frame Formats (708)
14.3.5DMA Operation (715)
14.4Initialization and Configuration (716)
14.5Register Map (717)
14.6Register Descriptions (718)
15Inter-Integrated Circuit(I2C)Interface (746)
15.1Block Diagram (747)
15.2Signal Description (747)
15.3Functional Description (748)
15.3.1I2C Bus Functional Overview (748)
15.3.2Available Speed Modes (750)
15.3.3Interrupts (751)
15.3.4Loopback Operation (752)
Table of Contents
15.3.5Command Sequence Flow Charts (753)
15.4Initialization and Configuration (760)
15.5Register Map (761)
15.6Register Descriptions(I2C Master) (762)
15.7Register Descriptions(I2C Slave) (775)
16Inter-Integrated Circuit Sound(I2S)Interface (784)
16.1Block Diagram (785)
16.2Signal Description (785)
16.3Functional Description (786)
16.3.1Transmit (788)
16.3.2Receive (792)
16.4Initialization and Configuration (794)
16.5Register Map (795)
16.6Register Descriptions (796)
17Controller Area Network(CAN)Module (821)
17.1Block Diagram (822)
17.2Signal Description (822)
17.3Functional Description (823)
17.3.1Initialization (824)
17.3.2Operation (825)
17.3.3Transmitting Message Objects (826)
17.3.4Configuring a Transmit Message Object (826)
17.3.5Updating a Transmit Message Object (827)
17.3.6Accepting Received Message Objects (828)
17.3.7Receiving a Data Frame (828)
17.3.8Receiving a Remote Frame (828)
17.3.9Receive/Transmit Priority (829)
17.3.10Configuring a Receive Message Object (829)
17.3.11Handling of Received Message Objects (830)
17.3.12Handling of Interrupts (832)
17.3.13Test Mode (833)
17.3.14Bit Timing Configuration Error Considerations (835)
17.3.15Bit Time and Bit Rate (835)
17.3.16Calculating the Bit Timing Parameters (837)
17.4Register Map (840)
17.5CAN Register Descriptions (841)
18Ethernet Controller (872)
18.1Block Diagram (873)
18.2Signal Description (874)
18.3Functional Description (875)
18.3.1MAC Operation (875)
18.3.2Internal MII Operation (879)
18.3.3PHY Operation (879)
18.3.4Interrupts (881)
18.3.5DMA Operation (882)
18.4Initialization and Configuration (882)
18.4.1Hardware Configuration (882)
Stellaris?LM3S9C97Microcontroller 18.4.2Software Configuration (883)
18.5Register Map (884)
18.6Ethernet MAC Register Descriptions (886)
18.7MII Management Register Descriptions (912)
19Universal Serial Bus(USB)Controller (933)
19.1Block Diagram (934)
19.2Signal Description (934)
19.3Functional Description (936)
19.3.1Operation as a Device (936)
19.3.2Operation as a Host (941)
19.3.3OTG Mode (945)
19.3.4DMA Operation (947)
19.4Initialization and Configuration (948)
19.4.1Pin Configuration (948)
19.4.2Endpoint Configuration (948)
19.5Register Map (949)
19.6Register Descriptions (960)
20Analog Comparators (1072)
20.1Block Diagram (1072)
20.2Signal Description (1073)
20.3Functional Description (1074)
20.3.1Internal Reference Programming (1074)
20.4Initialization and Configuration (1076)
20.5Register Map (1077)
20.6Register Descriptions (1077)
21Pulse Width Modulator(PWM) (1085)
21.1Block Diagram (1086)
21.2Signal Description (1087)
21.3Functional Description (1090)
21.3.1PWM Timer (1090)
21.3.2PWM Comparators (1090)
21.3.3PWM Signal Generator (1091)
21.3.4Dead-Band Generator (1092)
21.3.5Interrupt/ADC-Trigger Selector (1093)
21.3.6Synchronization Methods (1093)
21.3.7Fault Conditions (1094)
21.3.8Output Control Block (1095)
21.4Initialization and Configuration (1095)
21.5Register Map (1096)
21.6Register Descriptions (1098)
22Quadrature Encoder Interface(QEI) (1157)
22.1Block Diagram (1157)
22.2Signal Description (1158)
22.3Functional Description (1159)
22.4Initialization and Configuration (1161)
22.5Register Map (1162)
22.6Register Descriptions (1163)
Table of Contents
23Pin Diagram (1180)
24Signal Tables (1182)
24.1100-Pin LQFP Package Pin Tables (1183)
24.2108-Ball BGA Package Pin Tables (1215)
24.3Connections for Unused Signals (1248)
25Operating Characteristics (1251)
26Electrical Characteristics (1252)
26.1Maximum Ratings (1252)
26.2Recommended Operating Conditions (1252)
26.3Load Conditions (1253)
26.4JTAG and Boundary Scan (1253)
26.5Power and Brown-Out (1255)
26.6Reset (1256)
26.7On-Chip Low Drop-Out(LDO)Regulator (1257)
26.8Clocks (1257)
26.8.1PLL Specifications (1257)
26.8.2PIOSC Specifications (1258)
26.8.3Internal30-kHz Oscillator Specifications (1258)
26.8.4Hibernation Clock Source Specifications (1259)
26.8.5Main Oscillator Specifications (1259)
26.8.6System Clock Specification with ADC Operation (1260)
26.8.7System Clock Specification with USB Operation (1260)
26.9Sleep Modes (1260)
26.10Hibernation Module (1261)
26.11Flash Memory (1262)
26.12Input/Output Characteristics (1262)
26.13Analog-to-Digital Converter(ADC) (1263)
26.14Synchronous Serial Interface(SSI) (1265)
26.15Inter-Integrated Circuit(I2C)Interface (1266)
26.16Inter-Integrated Circuit Sound(I2S)Interface (1267)
26.17Ethernet Controller (1269)
26.18Universal Serial Bus(USB)Controller (1272)
26.19Analog Comparator (1272)
26.20Current Consumption (1272)
26.20.1Nominal Power Consumption (1272)
26.20.2Maximum Current Consumption (1273)
A Register Quick Reference (1275)
B Ordering and Contact Information (1326)
B.1Ordering Information (1326)
B.2Part Markings (1326)
B.3Kits (1327)
B.4Support Information (1327)
C Package Information (1328)
C.1100-Pin LQFP Package (1328)
C.1.1Package Dimensions (1328)
C.1.2Tray Dimensions (1330)
C.1.3Tape and Reel Dimensions (1330)
Stellaris?LM3S9C97Microcontroller C.2108-Ball BGA Package (1332)
C.2.1Package Dimensions (1332)
C.2.2Tray Dimensions (1334)
C.2.3Tape and Reel Dimensions (1335)
Table of Contents
List of Figures
Figure1-1.Stellaris LM3S9C97Microcontroller High-Level Block Diagram (48)
Figure2-1.CPU Block Diagram (71)
Figure2-2.TPIU Block Diagram (72)
Figure2-3.Cortex-M3Register Set (74)
Figure2-4.Bit-Band Mapping (95)
Figure2-5.Data Storage (96)
Figure2-6.Vector Table (102)
Figure2-7.Exception Stack Frame (104)
Figure3-1.SRD Use Example (118)
Figure4-1.JTAG Module Block Diagram (179)
Figure4-2.Test Access Port State Machine (182)
Figure4-3.IDCODE Register Format (188)
Figure4-4.BYPASS Register Format (188)
Figure4-5.Boundary Scan Register Format (189)
Figure5-1.Basic RST Configuration (193)
Figure5-2.External Circuitry to Extend Power-On Reset (193)
Figure5-3.Reset Circuit Controlled by Switch (194)
Figure5-4.Power Architecture (197)
Figure5-5.Main Clock Tree (200)
Figure6-1.Hibernation Module Block Diagram (298)
https://www.doczj.com/doc/071660374.html,ing a Crystal as the Hibernation Clock Source (301)
https://www.doczj.com/doc/071660374.html,ing a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode (301)
Figure7-1.Internal Memory Block Diagram (324)
Figure8-1.μDMA Block Diagram (371)
Figure8-2.Example of Ping-PongμDMA Transaction (378)
Figure8-3.Memory Scatter-Gather,Setup and Configuration (380)
Figure8-4.Memory Scatter-Gather,μDMA Copy Sequence (381)
Figure8-5.Peripheral Scatter-Gather,Setup and Configuration (383)
Figure8-6.Peripheral Scatter-Gather,μDMA Copy Sequence (384)
Figure9-1.Digital I/O Pads (436)
Figure9-2.Analog/Digital I/O Pads (437)
Figure9-3.GPIODATA Write Example (438)
Figure9-4.GPIODATA Read Example (438)
Figure10-1.GPTM Module Block Diagram (488)
Figure10-2.Timer Daisy Chain (493)
Figure10-3.Input Edge-Count Mode Example (495)
Figure10-4.16-Bit Input Edge-Time Mode Example (497)
Figure10-5.16-Bit PWM Mode Example (498)
Figure11-1.WDT Module Block Diagram (535)
Figure12-1.Implementation of Two ADC Blocks (560)
Figure12-2.ADC Module Block Diagram (561)
Figure12-3.ADC Sample Phases (565)
Figure12-4.Doubling the ADC Sample Rate (566)
Figure12-5.Skewed Sampling (566)
Figure12-6.Sample Averaging Example (567)
Stellaris?LM3S9C97Microcontroller Figure12-7.ADC Input Equivalency Diagram (568)
Figure12-8.Internal Voltage Conversion Result (569)
Figure12-9.External Voltage Conversion Result with3.0-V Setting (570)
Figure12-10.External Voltage Conversion Result with1.0-V Setting (570)
Figure12-11.Differential Sampling Range,V IN_ODD=1.5V (572)
Figure12-12.Differential Sampling Range,V IN_ODD=0.75V (572)
Figure12-13.Differential Sampling Range,V IN_ODD=2.25V (573)
Figure12-14.Internal Temperature Sensor Characteristic (574)
Figure12-15.Low-Band Operation(CIC=0x0and/or CTC=0x0) (576)
Figure12-16.Mid-Band Operation(CIC=0x1and/or CTC=0x1) (577)
Figure12-17.High-Band Operation(CIC=0x3and/or CTC=0x3) (578)
Figure13-1.UART Module Block Diagram (641)
Figure13-2.UART Character Frame (644)
Figure13-3.IrDA Data Modulation (646)
Figure13-4.LIN Message (648)
Figure13-5.LIN Synchronization Field (649)
Figure14-1.SSI Module Block Diagram (705)
Figure14-2.TI Synchronous Serial Frame Format(Single Transfer) (709)
Figure14-3.TI Synchronous Serial Frame Format(Continuous Transfer) (709)
Figure14-4.Freescale SPI Format(Single Transfer)with SPO=0and SPH=0 (710)
Figure14-5.Freescale SPI Format(Continuous Transfer)with SPO=0and SPH=0 (710)
Figure14-6.Freescale SPI Frame Format with SPO=0and SPH=1 (711)
Figure14-7.Freescale SPI Frame Format(Single Transfer)with SPO=1and SPH=0 (712)
Figure14-8.Freescale SPI Frame Format(Continuous Transfer)with SPO=1and SPH=0 (712)
Figure14-9.Freescale SPI Frame Format with SPO=1and SPH=1 (713)
Figure14-10.MICROWIRE Frame Format(Single Frame) (714)
Figure14-11.MICROWIRE Frame Format(Continuous Transfer) (715)
Figure14-12.MICROWIRE Frame Format,SSIFss Input Setup and Hold Requirements (715)
Figure15-1.I2C Block Diagram (747)
Figure15-2.I2C Bus Configuration (748)
Figure15-3.START and STOP Conditions (749)
https://www.doczj.com/doc/071660374.html,plete Data Transfer with a7-Bit Address (749)
Figure15-5.R/S Bit in First Byte (750)
Figure15-6.Data Validity During Bit Transfer on the I2C Bus (750)
Figure15-7.Master Single TRANSMIT (754)
Figure15-8.Master Single RECEIVE (755)
Figure15-9.Master TRANSMIT with Repeated START (756)
Figure15-10.Master RECEIVE with Repeated START (757)
Figure15-11.Master RECEIVE with Repeated START after TRANSMIT with Repeated
START (758)
Figure15-12.Master TRANSMIT with Repeated START after RECEIVE with Repeated
START (759)
Figure15-13.Slave Command Sequence (760)
Figure16-1.I2S Block Diagram (785)
Figure16-2.I2S Data Transfer (788)
Figure16-3.Left-Justified Data Transfer (788)
Figure16-4.Right-Justified Data Transfer (788)
Figure17-1.CAN Controller Block Diagram (822)
Table of Contents
Figure17-2.CAN Data/Remote Frame (824)
Figure17-3.Message Objects in a FIFO Buffer (832)
Figure17-4.CAN Bit Time (836)
Figure18-1.Ethernet Controller (873)
Figure18-2.Ethernet Controller Block Diagram (873)
Figure18-3.Ethernet Frame (875)
Figure18-4.Interface to an Ethernet Jack (883)
https://www.doczj.com/doc/071660374.html,B Module Block Diagram (934)
Figure20-1.Analog Comparator Module Block Diagram (1072)
Figure20-2.Structure of Comparator Unit (1074)
https://www.doczj.com/doc/071660374.html,parator Internal Reference Structure (1075)
Figure21-1.PWM Module Diagram (1087)
Figure21-2.PWM Generator Block Diagram (1087)
Figure21-3.PWM Count-Down Mode (1091)
Figure21-4.PWM Count-Up/Down Mode (1091)
Figure21-5.PWM Generation Example In Count-Up/Down Mode (1092)
Figure21-6.PWM Dead-Band Generator (1092)
Figure22-1.QEI Block Diagram (1158)
Figure22-2.Quadrature Encoder and Velocity Predivider Operation (1160)
Figure23-1.100-Pin LQFP Package Pin Diagram (1180)
Figure23-2.108-Ball BGA Package Pin Diagram(Top View) (1181)
Figure26-1.Load Conditions (1253)
Figure26-2.JTAG Test Clock Input Timing (1254)
Figure26-3.JTAG Test Access Port(TAP)Timing (1254)
Figure26-4.Power-On Reset Timing (1255)
Figure26-5.Brown-Out Reset Timing (1255)
Figure26-6.Power-On Reset and Voltage Parameters (1256)
Figure26-7.External Reset Timing(RST) (1256)
Figure26-8.Software Reset Timing (1256)
Figure26-9.Watchdog Reset Timing (1257)
Figure26-10.MOSC Failure Reset Timing (1257)
Figure26-11.Hibernation Module Timing with Internal Oscillator Running in Hibernation (1262)
Figure26-12.Hibernation Module Timing with Internal Oscillator Stopped in Hibernation (1262)
Figure26-13.ADC Input Equivalency Diagram (1264)
Figure26-14.SSI Timing for TI Frame Format(FRF=01),Single Transfer Timing
Measurement (1265)
Figure26-15.SSI Timing for MICROWIRE Frame Format(FRF=10),Single Transfer (1266)
Figure26-16.SSI Timing for SPI Frame Format(FRF=00),with SPH=1 (1266)
Figure26-17.I2C Timing (1267)
Figure26-18.I2S Master Mode Transmit Timing (1268)
Figure26-19.I2S Master Mode Receive Timing (1268)
Figure26-20.I2S Slave Mode Transmit Timing (1269)
Figure26-21.I2S Slave Mode Receive Timing (1269)
Figure26-22.External XTLP Oscillator Characteristics (1271)
Figure C-1.Stellaris LM3S9C97100-Pin LQFP Package Dimensions (1328)
Figure C-2.100-Pin LQFP Tray Dimensions (1330)
Figure C-3.100-Pin LQFP Tape and Reel Dimensions (1331)
Figure C-4.Stellaris LM3S9C97108-Ball BGA Package Dimensions (1332)
Stellaris?LM3S9C97Microcontroller Figure C-5.108-Ball BGA Tray Dimensions (1334)
Figure C-6.108-Ball BGA Tape and Reel Dimensions (1335)
Table of Contents
List of Tables
Table1.Revision History (41)
Table2.Documentation Conventions (45)
Table2-1.Summary of Processor Mode,Privilege Level,and Stack Use (74)
Table2-2.Processor Register Map (75)
Table2-3.PSR Register Combinations (80)
Table2-4.Memory Map (88)
Table2-5.Memory Access Behavior (91)
Table2-6.SRAM Memory Bit-Banding Regions (93)
Table2-7.Peripheral Memory Bit-Banding Regions (93)
Table2-8.Exception Types (99)
Table2-9.Interrupts (100)
Table2-10.Exception Return Behavior (105)
Table2-11.Faults (106)
Table2-12.Fault Status and Fault Address Registers (107)
Table2-13.Cortex-M3Instruction Summary (109)
Table3-1.Core Peripheral Register Regions (112)
Table3-2.Memory Attributes Summary (115)
Table3-3.TEX,S,C,and B Bit Field Encoding (118)
Table3-4.Cache Policy for Memory Attribute Encoding (119)
Table3-5.AP Bit Field Encoding (119)
Table3-6.Memory Region Attributes for Stellaris Microcontrollers (119)
Table3-7.Peripherals Register Map (120)
Table3-8.Interrupt Priority Levels (147)
Table3-9.Example SIZE Field Values (175)
Table4-1.JTAG_SWD_SWO Signals(100LQFP) (179)
Table4-2.JTAG_SWD_SWO Signals(108BGA) (180)
Table4-3.JTAG Port Pins State after Power-On Reset or RST assertion (181)
Table4-4.JTAG Instruction Register Commands (186)
Table5-1.System Control&Clocks Signals(100LQFP) (190)
Table5-2.System Control&Clocks Signals(108BGA) (190)
Table5-3.Reset Sources (191)
Table5-4.Clock Source Options (198)
Table5-5.Possible System Clock Frequencies Using the SYSDIV Field (201)
Table5-6.Examples of Possible System Clock Frequencies Using the SYSDIV2Field (201)
Table5-7.Examples of Possible System Clock Frequencies with DIV400=1 (202)
Table5-8.System Control Register Map (207)
Table5-9.RCC2Fields that Override RCC Fields (228)
Table6-1.Hibernate Signals(100LQFP) (298)
Table6-2.Hibernate Signals(108BGA) (299)
Table6-3.Hibernation Module Clock Operation (305)
Table6-4.Hibernation Module Register Map (307)
Table7-1.Flash Memory Protection Policy Combinations (328)
https://www.doczj.com/doc/071660374.html,er-Programmable Flash Memory Resident Registers (332)
Table7-3.Flash Register Map (333)
Table8-1.μDMA Channel Assignments (372)
Table8-2.Request Type Support (374)
Stellaris?LM3S9C97Microcontroller Table8-3.Control Structure Memory Map (375)
Table8-4.Channel Control Structure (375)
Table8-5.μDMA Read Example:8-Bit Peripheral (385)
Table8-6.μDMA Interrupt Assignments (386)
Table8-7.Channel Control Structure Offsets for Channel30 (387)
Table8-8.Channel Control Word Configuration for Memory Transfer Example (387)
Table8-9.Channel Control Structure Offsets for Channel7 (388)
Table8-10.Channel Control Word Configuration for Peripheral Transmit Example (389)
Table8-11.Primary and Alternate Channel Control Structure Offsets for Channel8 (390)
Table8-12.Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example (391)
Table8-13.μDMA Register Map (393)
Table9-1.GPIO Pins With Non-Zero Reset Values (432)
Table9-2.GPIO Pins and Alternate Functions(100LQFP) (432)
Table9-3.GPIO Pins and Alternate Functions(108BGA) (434)
Table9-4.GPIO Pad Configuration Examples (440)
Table9-5.GPIO Interrupt Configuration Example (441)
Table9-6.GPIO Pins With Non-Zero Reset Values (442)
Table9-7.GPIO Register Map (442)
Table9-8.GPIO Pins With Non-Zero Reset Values (455)
Table9-9.GPIO Pins With Non-Zero Reset Values (461)
Table9-10.GPIO Pins With Non-Zero Reset Values (463)
Table9-11.GPIO Pins With Non-Zero Reset Values (466)
Table9-12.GPIO Pins With Non-Zero Reset Values (473)
Table10-1.Available CCP Pins (488)
Table10-2.General-Purpose Timers Signals(100LQFP) (489)
Table10-3.General-Purpose Timers Signals(108BGA) (490)
Table10-4.General-Purpose Timer Capabilities (491)
Table10-5.Counter Values When the Timer is Enabled in Periodic or One-Shot Modes (492)
Table10-6.16-Bit Timer With Prescaler Configurations (493)
Table10-7.Counter Values When the Timer is Enabled in RTC Mode (494)
Table10-8.Counter Values When the Timer is Enabled in Input Edge-Count Mode (494)
Table10-9.Counter Values When the Timer is Enabled in Input Event-Count Mode (496)
Table10-10.Counter Values When the Timer is Enabled in PWM Mode (497)
Table10-11.Timers Register Map (502)
Table11-1.Watchdog Timers Register Map (537)
Table12-1.ADC Signals(100LQFP) (561)
Table12-2.ADC Signals(108BGA) (562)
Table12-3.Samples and FIFO Depth of Sequencers (563)
Table12-4.Differential Sampling Pairs (571)
Table12-5.ADC Register Map (579)
Table13-1.UART Signals(100LQFP) (642)
Table13-2.UART Signals(108BGA) (642)
Table13-3.Flow Control Mode (647)
Table13-4.UART Register Map (653)
Table14-1.SSI Signals(100LQFP) (706)
Table14-2.SSI Signals(108BGA) (706)
Table14-3.SSI Register Map (717)
Table of Contents
Table15-1.I2C Signals(100LQFP) (747)
Table15-2.I2C Signals(108BGA) (747)
Table15-3.Examples of I2C Master Timer Period versus Speed Mode (751)
Table15-4.Inter-Integrated Circuit(I2C)Interface Register Map (761)
Table15-5.Write Field Decoding for I2CMCS[3:0]Field (767)
Table16-1.I2S Signals(100LQFP) (786)
Table16-2.I2S Signals(108BGA) (786)
Table16-3.I2S Transmit FIFO Interface (789)
Table16-4.Crystal Frequency(Values from3.5795MHz to5MHz) (790)
Table16-5.Crystal Frequency(Values from5.12MHz to8.192MHz) (790)
Table16-6.Crystal Frequency(Values from10MHz to14.3181MHz) (791)
Table16-7.Crystal Frequency(Values from16MHz to16.384MHz) (791)
Table16-8.I2S Receive FIFO Interface (793)
Table16-9.Audio Formats Configuration (795)
Table16-10.Inter-Integrated Circuit Sound(I2S)Interface Register Map (796)
Table17-1.Controller Area Network Signals(100LQFP) (823)
Table17-2.Controller Area Network Signals(108BGA) (823)
Table17-3.Message Object Configurations (829)
Table17-4.CAN Protocol Ranges (836)
Table17-5.CANBIT Register Values (836)
Table17-6.CAN Register Map (840)
Table18-1.Ethernet Signals(100LQFP) (874)
Table18-2.Ethernet Signals(108BGA) (874)
Table18-3.TX&RX FIFO Organization (877)
Table18-4.Ethernet Register Map (884)
https://www.doczj.com/doc/071660374.html,B Signals(100LQFP) (934)
https://www.doczj.com/doc/071660374.html,B Signals(108BGA) (935)
Table19-3.Remainder(MAXLOAD/4) (947)
Table19-4.Actual Bytes Read (947)
Table19-5.Packet Sizes That Clear RXRDY (947)
Table19-6.Universal Serial Bus(USB)Controller Register Map (949)
Table20-1.Analog Comparators Signals(100LQFP) (1073)
Table20-2.Analog Comparators Signals(108BGA) (1073)
Table20-3.Internal Reference Voltage and ACREFCTL Field Values (1075)
Table20-4.Analog Comparators Register Map (1077)
Table21-1.PWM Signals(100LQFP) (1088)
Table21-2.PWM Signals(108BGA) (1089)
Table21-3.PWM Register Map (1096)
Table22-1.QEI Signals(100LQFP) (1158)
Table22-2.QEI Signals(108BGA) (1159)
Table22-3.QEI Register Map (1162)
Table24-1.GPIO Pins With Default Alternate Functions (1182)
Table24-2.Signals by Pin Number (1183)
Table24-3.Signals by Signal Name (1193)
Table24-4.Signals by Function,Except for GPIO (1202)
Table24-5.GPIO Pins and Alternate Functions (1210)
Table24-6.Possible Pin Assignments for Alternate Functions (1213)
Table24-7.Signals by Pin Number (1215)
Stellaris?LM3S9C97Microcontroller Table24-8.Signals by Signal Name (1226)
Table24-9.Signals by Function,Except for GPIO (1235)
Table24-10.GPIO Pins and Alternate Functions (1243)
Table24-11.Possible Pin Assignments for Alternate Functions (1246)
Table24-12.Connections for Unused Signals(100-Pin LQFP) (1248)
Table24-13.Connections for Unused Signals(108-Ball BGA) (1249)
Table25-1.Temperature Characteristics (1251)
Table25-2.Thermal Characteristics (1251)
Table25-3.ESD Absolute Maximum Ratings (1251)
Table26-1.Maximum Ratings (1252)
Table26-2.Recommended DC Operating Conditions (1252)
Table26-3.JTAG Characteristics (1253)
Table26-4.Power Characteristics (1255)
Table26-5.Reset Characteristics (1256)
Table26-6.LDO Regulator Characteristics (1257)
Table26-7.Phase Locked Loop(PLL)Characteristics (1257)
Table26-8.Actual PLL Frequency (1258)
Table26-9.PIOSC Clock Characteristics (1258)
Table26-10.30-kHz Clock Characteristics (1258)
Table26-11.Hibernation Clock Characteristics (1259)
Table26-12.HIB Oscillator Input Characteristics (1259)
Table26-13.Main Oscillator Clock Characteristics (1259)
Table26-14.Supported MOSC Crystal Frequencies (1259)
Table26-15.System Clock Characteristics with ADC Operation (1260)
Table26-16.System Clock Characteristics with USB Operation (1260)
Table26-17.Sleep Modes AC Characteristics (1260)
Table26-18.Hibernation Module Battery Characteristics (1261)
Table26-19.Hibernation Module AC Characteristics (1261)
Table26-20.Flash Memory Characteristics (1262)
Table26-21.GPIO Module Characteristics (1262)
Table26-22.ADC Characteristics (1263)
Table26-23.ADC Module External Reference Characteristics (1264)
Table26-24.ADC Module Internal Reference Characteristics (1264)
Table26-25.SSI Characteristics (1265)
Table26-26.I2C Characteristics (1266)
Table26-27.I2S Master Clock(Receive and Transmit) (1267)
Table26-28.I2S Slave Clock(Receive and Transmit) (1267)
Table26-29.I2S Master Mode (1268)
Table26-30.I2S Slave Mode (1268)
Table26-31.Ethernet Controller DC Characteristics (1269)
Table26-32.100BASE-TX Transmitter Characteristics (1269)
Table26-33.100BASE-TX Transmitter Characteristics(informative) (1269)
Table26-34.100BASE-TX Receiver Characteristics (1269)
Table26-35.10BASE-T Transmitter Characteristics (1270)
Table26-36.10BASE-T Transmitter Characteristics(informative) (1270)
Table26-37.10BASE-T Receiver Characteristics (1270)
Table26-38.Isolation Transformers (1270)
Table26-39.Ethernet Reference Crystal (1271)
Table of Contents
Table26-40.External XTLP Oscillator Characteristics (1271)
https://www.doczj.com/doc/071660374.html,B Controller Characteristics (1272)
Table26-42.Analog Comparator Characteristics (1272)
Table26-43.Analog Comparator Voltage Reference Characteristics (1272)
Table26-44.Nominal Power Consumption (1272)
Table26-45.Detailed Current Specifications (1273)
Table26-46.Hibernation Detailed Current Specifications (1274)
Table B-1.Part Ordering Information (1326)
VE 3511/3516/3521/4532/5020/5835/5845/7835/7850/1040/1054TYPE ● FEATURES: Various high power indrctors are superior To be high saturation for surface mounting ● 特性: 具有高功率、强力高饱和电流、低阻抗、 小型化之特性。 ● APPLICATIONS ： Powder supply for VTR,OA equipment Digital camera, LCD television set Notebook PC,portable communication Equipments, DC/DC converters ,ect. ● 用途: 录音机、OA 仪器、数码相机、液晶电视、 笔记型电脑、小型通信机器、DC/DC 变压器 之电源供应器等。 ● PART NUMBERING SUSTEM(品名系统): ● SHAPES AND DIMENSIONS(外形及尺寸):
VE3511-R47N 0.47 0.72 0.32 100KHz VE3511-R56N 0.56 0.85 0.20 100KHz VE3511-R68N 0.68 0.93 0.19 100KHz VE3511-R82N 0.82 1.02 0.185 100KHz VE3511-100K 10 1.15 0.18 100KHz VE3511-120K 12 1.28 0.175 100KHz VE3511-150K 15 1.32 0.172 100KHz VE3511-180K 18 1.45 0.17 100KHz VE3511-220K 22 1.55 0.162 100KHz VE3511-250K 25 1.62 0.160 100KHz VE3511-330K 33 1.70 0.150 100KHz VE3511-470K 47 1.75 0.150 100KHz VE3511-560K 56 1.82 0.145 100KHz VE3511-680K 68 1.88 0.142 100KHz VE3511-820K 82 1.92 0.140 100KHz VE3511-101K 100 2.00 0.138 100KHz VE3511-221K 220 2.10 0.136 100KHz VE3511-331K 330 2.18 0.132 100KHz VE3511-391K 390 2.45 0.130 100KHz VE3516 TYPE PART NUMBER. 品名INDUCTANCE 电感值(μH) DCR(max) 直流电阻(?) IDC(max) 定格电流(A) TEST FREQ. 测试频率 VE3516-2R2N 2.2 0.10 1.8 100KHz VE3516-3R3N 3.3 0.15 1.5 100KHz VE3516-4R7N 4.7 0.12 1.2 100KHz VE3516-5R6N 5.6 0.24 1.15 100KHz VE3516-6R8N 6.8 0.26 1.1 100KHz VE3516-100K 10 0.38 0.8 100KHz VE3516-220K 22 0.65 0.6 100KHz VE3516-330K 33 0.85 0.45 100KHz VE3516-470K 47 1.20 0.35 100KHz This indicates the value of current when the inductance is 10% lower than its initial value at D.C
XX项目 产品需求规格说明书模板
目录 1文档介绍 (2) 1.1文档目的 (2) 1.2文档范围 (2) 1.3读者对象 (2) 1.4参考文档 (3) 1.5术语与缩写解释 (3) 2综合描述 (3) 2.1产品介绍 (3) 2.2产品面向的用户群体（可选） (3) 2.3产品应当遵循的标准或规范 (4) 2.4产品范围 (4) 2.5产品涉众（涉及角色） (4) 2.6设计和实现的限制 (4) 2.7假设和约束（依赖） (5) 3产品需求 (5) 3.1需求分类 (5) 3.2用例图 (6) 3.3功能需求 (7) 3.3.1需求描述 (7) 3.3.2特殊需求 (8) 3.3.3数据规范 (8) 3.4非功能需求（包括但不限制于以下几项） (8) 3.4.1时间特性要求 (8) 3.4.2精度要求 (9) 3.4.3业务量估算 (9) 3.4.4灵活性 (9) 3.4.5可用性 (9) 3.4.6安全性 (10) 3.4.7兼容性 (10) 3.4.8易用性 (11) 3.4.9可维护性 (11) 3.5运行环境 (11) 3.5.1设备及分布 (11) 3.5.2支撑软件 (12) 3.6接口 (12) 3.6.1硬件接口 (12) 3.6.2软件接口 (12) 3.6.3通讯接口 (12) 3.6.4用户接口 (13) 4验收标准 (14) 4.1功能验收标准 (14) 4.2非功能性验收标准 (14) 附录A：需求建模与分析报告 (14) A.1需求模型1 (15) A.2需求模型N (15) 附录B：需求确认 (15)
【对本文档的说明： 本文档中黑色斜字体为说明性文字，黑色正常字体为需求规格说明书实际写作时必需部分。蓝色字体为举例说明文字。】 1文档介绍 1.1 文档目的 提示： 软件需求规格说明主要描述系统的概貌、功能要求、性能分析、运行要求和将来可能提出的要求。阐述一个软件系统必须提供的功能和性能以及它所要考虑的限制条件，它应该尽可能完整地描述系统预期的外部行为和用户可视化行为。 举例说明： 示例：本文档的主要目的是描述XXX项目中XXX模块的功能需求和非功能需求，功能需求采用用例的方式描述。以使所有涉众能够达成共识。本需求说明书，在需求固化之前，会有相应的变更。在文档历史中会详细记录变更的具体内容。 1.2 文档范围 提示： 文档范围包括：产品介绍，产品面向的用户群体，产品应当遵守的标准与规范，产品范围，产品中的角色，产品的功能性需求，产品的非功能性需求。 1.3 读者对象 提示： 1）各种管理人员及开发人员：专案经理、系统工程师、软件开发人员、硬件开发人员、测试人员、型态管理人员、品质保证人员、作业员和技术出版人员。 2）软件使用客户。
Wire Wound SMD Power Inductors – SWPA Series Operating temperature range: -40℃~+125℃ (Including self-heating) FEATURES ● Magnetic-resin shielded construction reduces buzz noise to ultra-low levels ● Metallization on ferrite core results in excellent shock resistance and damage-free durability ● Closed magnetic circuit design reduces leakage flux and Electro Magnetic Interference (EMI) ● 30% higher current rating than conventional inductors of equal size ● Takes up less PCB real estate and save more power APPLICATIONS ● Smart phone, smart TV, set top box, notebook ● Car navigation systems, telecomm base stations ● VR, AR ● LED lighting PRODUCT IDENTIFICATION SWPA 3012 S 1R0 N T □□□ ① ② ③ ④ ⑤ ⑥ ⑦ ② External Dimensions (L×W×H) [mm] 252010 2.5×2.0×1.0 252012 2.5×2.0×1.2 3010 3.0×3.0×1.0 3012 3.0×3.0×1.2 3015 3.0×3.0×1.5 4010 4.0×4.0×1.0 4012 4.0×4.0×1.2 4018 4.0×4.0×1.8 4020 4.0×4.0×2.0 4026 4.0×4.0×2.6 4030 4.0×4.0×3.0 5012 5.0×5.0×1.2 5020 5.0×5.0×2.0 5040 5.0×5.0×4.0 6020 6.0×6.0×2.0 6028 6.0×6.0×2.8 6040 6.0×6.0×4.0 6045 6.0×6.0×4.5 8040 8.0×8.0×4.0 8050 8.0×8.0×5.0 8060 8.0×8.0×6.0 8065 8.0×8.0×6.5 ① Type SWPA Wire Wound SMD Power Inductor ③ Feature Type S Standard ④ Nominal Inductance Example Nominal Value 1R0 1.0μH 100 10μH ⑤ Inductance Tolerance K ±10% M ±20% N ±30% ⑥ Packing T Tape Carrier Package ⑦ Design Code □□□ Standard product is blank https://www.doczj.com/doc/071660374.html,
审核: Reviewed by 陈伟东 日期： Date 2011-06-29 批准: Granted by 李叶来 日期： Date 2011-06-29 深圳市海鹏信电子股份有限公司 SHENZHEN HAIPENGXIN ELECTRONICS CO.,LTD. 版权所有 侵权必究 All rights reserved
2009-02-01 未经许可不得扩散 第2页,共8页Page 2 , Total8 修订记录 日期 修订版本 描述 编写 2009-02-01 V1.0 初版制订 韦耀峰 2010-08-12 V1.1 技术参数更新，添加认证 李韵晴 2010-12-10 V3.0 产品说明书版本同步 李韵晴 2011-06-29 V3.2 海拔高度和安规版本更改 曾维霞 2012-01-09 V3.3 尺寸图加标公差、更改大气压力 曾维霞
2009-02-01 未经许可不得扩散 第3页,共8页Page 3 , Total8 目 录 1 适用范围..........................................................................................................................5 2 规范性引用文件...............................................................................................................5 3 功能性能..........................................................................................................................5 3.1 简述.................................................................................................................................5 3.2 性能指标..........................................................................................................................5 4 防护原理（仅供参考）.....................................................................................................6 5 结构和外观.......................................................................................................................6 5.1 端口类型..........................................................................................................................6 5.2 结构.................................................................................................................................6 5.2.1 结构尺寸....................................................................................................................6 5.2.2 附件............................................................................................................................7 5.2.3 安装............................................................................................................................7 6 适用环境与安规...............................................................................................................7 7 环保.................................................................................................................................8 8 产品标签..........................................................................................................................8 9 产品照片.. (8)
MURS120T3G Series, SURS8120T3G Series, NRVUS120VT3G Series Surface Mount Ultrafast Power Rectifiers MURS105T3G, MURS110T3G, MURS115T3G, MURS120T3G, MURS140T3G, MURS160T3G, SURS8105T3G, SURS8110T3G, SURS8115T3G, SURS8120T3G, SURS8140T3G, SURS8160T3G, NRVUS110VT3G, NRVUS120VT3G, NRVUS160VT3G Ideally suited for high voltage, high frequency rectification, or as free wheeling and protection diodes in surface mount applications where compact size and weight are critical to the system. Features ?Small Compact Surface Mountable Package with J?Bend Leads ?Rectangular Package for Automated Handling ?High Temperature Glass Passivated Junction ?Low Forward V oltage Drop (0.71 to 1.05 V Max @ 1.0 A, T J = 150°C)?NRVUS and SURS8 Prefixes for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC?Q101 Qualified and PPAP Capable ?These Devices are Pb?Free, Halogen Free/BFR Free and are RoHS Compliant Mechanical Characteristics: ?Case: Epoxy, Molded ?Weight: 95 mg (Approximately) ?Finish: All External Surfaces Corrosion Resistant and Terminal Leads are Readily Solderable ?Lead and Mounting Surface Temperature for Soldering Purposes: 260°C Max. for 10 Seconds ?Polarity: Polarity Band Indicates Cathode Lead ?ESD Rating: ?Human Body Model = 3B (> 8 kV) ?Machine Model = C (> 400 V)See detailed ordering and shipping information in the table on page 2 of this data sheet. ORDERING INFORMATION MARKING DIAGRAM See general marking information in the device marking table on page 2 of this data sheet. DEVICE MARKING INFORMATION ULTRAFAST RECTIFIERS 1.0 AMPERE, 50?600 VOLTS SMB CASE 403A https://www.doczj.com/doc/071660374.html, A=Assembly Location* Y=Year WW=Work Week U1=Device Code x = A, B, C, D, G, or J G=Pb?Free Package AYWW U1x G G (Note: Microdot may be in either location) * The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package bottom (molding ejecter pin), the front side assembly code may be blank.
E12 SERIES SPECIFICATION 1/5
E12 SERIES SPECIFICATION 2/5
E12 SERIES SPECIFICATION
项目ITEM 7-1．Rotational life 回转寿命 在无负荷条件下轴以600～1000周/小时速度回转30000周。7-2.Damp heat 耐湿性 7-3、Dry heat 耐热性 7-4. Cold 低温特性 7-5. Solder ability 焊锡性 7-6.Resistance to Soldering heat 耐焊接热 Soldering:Solder temperature:260±5℃ or less Immersion time:within 3S 焊接:温度260±5℃或以下,时间3秒以内. 2.Preheating time:within 1 min.接触无异常. 预热:基板表面温度100℃以下,时间1分钟以内.使用基板:t=1.6mm的单面覆铜板. mechanical abnormality.Preheating:1.Surface temperature of board:100℃ or less.不得有绝缘体的破损、变形、Printed wiring board:single-sided copper clad laminate Electrical characteristics board with thickness of 1.6mm.shall be satisfied No 温度300℃以下,时间3秒以内.Dip soldering.槽焊 Manual soldering 手工焊接 Bit temperature of soldering iron:300℃ less than Application time of soldering iron:within 3s 端子在260℃±5℃温度的焊锡槽内浸锡3秒±0.5秒.surface being immersed. 浸渍面须有75%以上焊锡附着 The terminals shall be immersed into solder bath at 260℃ A new uniform coating of solder for 3s±0.5s in the same manner as para.shall cover 75% minimum of the 温度-25±3℃的恒温箱中放置96±4小时,常温、常湿放置1.5小时后测试. shall be subjected to standard atmospheric conditions for 所有项应满足初期规格 1.5H.After which measurements shall be made. The encoder shall be stored at a temperature of -25±3℃ Specifications in clause all for 96±4H in a thermostatic chamber.And then the encoder items is shall be satisfied.温度80±3℃的恒温箱中放置96±4小时,常温、常湿放置1.5小时后测试. shall be subjected to standard atmospheric conditions for 所有项应满足初期规格 1.5H,After which measurements shall be made. E12 SERIES SPECIFICATION E E121212系列规格书 系列规格书 4/5 7 7 耐久性能 耐久性能 耐久性能 ENDURANCE CHARACTERISTICS ENDURANCE CHARACTERISTICS 条件规格CONDITIONS SPECIFICATIONS The shaft of encoder shall be rotated to 30000 cycles at a ≤5mS Bounce t2≤3mS 突跳 t2≤Chattiring t1,t3≤5mS 振荡t1,t3speed of 600～1000 cycles/H without electrical load,after 3mSDetent feeling has to with measurements shall be made. remains 尚余有轻微定位感Specifications in clause all relative humidity of 90% to95% for96±4H in a thermostatic items is shall be satisfied.Contact resistance 200Ω Max 端子间接触阻抗200Ω以下The encoder shall be stored at temperature of 40±2℃ with shall be made.温度40±2℃,湿度90～95%的恒温恒湿槽中放置96±4小时后,在常温、常湿中放置1.5小时后测试. The encoder shall be stored at a temperature of 80±3℃ Specifications in clause all for 96±4H in a thermostatic chamber.And then the encoder items is shall be satisfied.chamber.And the encoder shall be subjected to standard at- 所有项应满足初期规格 mospheric conditions for 1.5H,After which measurements
LM393, LM393E, LM293, LM2903, LM2903E, LM2903V, NCV2903 Low Offset Voltage Dual Comparators The LM393 series are dual independent precision voltage comparators capable of single or split supply operation. These devices are designed to permit a common mode range?to?ground level with single supply operation. Input offset voltage specifications as low as 2.0 mV make this device an excellent selection for many applications in consumer, automotive, and industrial electronics. Features ?Wide Single?Supply Range: 2.0 Vdc to 36 Vdc ?Split?Supply Range: ±1.0 Vdc to ±18 Vdc ?Very Low Current Drain Independent of Supply V oltage: 0.4 mA ?Low Input Bias Current: 25 nA ?Low Input Offset Current: 5.0 nA ?Low Input Offset V oltage: 5.0 mV (max) LM293/393 ?Input Common Mode Range to Ground Level ?Differential Input V oltage Range Equal to Power Supply V oltage ?Output V oltage Compatible with DTL, ECL, TTL, MOS, and CMOS Logic Levels ?ESD Clamps on the Inputs Increase the Ruggedness of the Device without Affecting Performance ?NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC?Q100 Qualified and PPAP Capable ?These Devices are Pb?Free, Halogen Free/BFR Free and are RoHS Compliant Figure 1. Representative Schematic Diagram (Diagram shown is for 1 comparator)See detailed marking information and ordering and shipping information on pages 6 and 7 of this data sheet. DEVICE MARKING AND ORDERING INFORMATION PDIP?8 N SUFFIX CASE 626 8 SOIC?8 D SUFFIX CASE 751 1 PIN CONNECTIONS (Top View) Inputs A Inputs B Output B CC https://www.doczj.com/doc/071660374.html, Micro8E DM SUFFIX CASE 846A 1
FEATURES APPLICATIONS 150 M T HOW TO ORDER DIMENSIONS PS-D PS-D SERIES SMD POWER INDUCTORS , Low profile Magnetic shielded SMT type,suitable for reflow soldering. Portable communication equipment Notebook Computer DC/DC DC/DC converters etc. PS 5D28 (Unit)mm
ELECTRICAL CHARACTERISTICS Isat:Isat 35% Isat:Saturation Current,the current when the inductance becomes 35%lower than its initial value. Unit mm PS2D11Series PS2D14Series PS-D SERIES SHIELDED SMD POWER INDUCTORS PS-D PS2D18Series
PS3D18Series PS4D18Series PS4D28Series Isat:Isat35% Isat:Saturation Current,the current when the inductance becomes35%lower than its initial value.
Isat:Isat 35% Isat:Saturation Current,the current when the inductance becomes 35%lower than its initial value. PS5D28Series PS6D28Series PS-D SERIES SHIELDED SMD POWER INDUCTORS PS-D PS6D38Series
DFE201610E Inductance Range: 0.24~10μH (Unit: mm) (Unit: mm) ? Miniature size: 2016 footprint (2.0mm×1.6mm) and low profile(1.0mm Max. height) ? The use of magnetic iron powder ensure capability for large current. ? The use of Flat wire for Low DC resistance. ? Magnetically shielded, low audible core noise. ? Reflow solderable. ? Operating temperature : -40～+125°C ? 小型薄型構造 (2.0ｘ1.6ｍｍ角、高さ1.0mm Max.) ? 磁性材に鉄系磁性粉を用いた大電流対応 ? 平角線採用による低直流抵抗 ? 閉磁路構造、低コア鳴きノイズ ? リフロはんだ対応 ? 動作温度範囲：-40～+125°C (1) Inductance is measured with a LCR meter 4284A (Agilent Technologies ) or equivalent. Test frequency at 1MHz (2) DC resistance is measured with 34420A (Agilent Technologies) or 3541(HIOKI). (Reference ambient temperature 20°C) (3) Inductance Decrease Current based upon 30% inductance reduction from the initial value (4) Temperature Rise Current based upon 40°C temperature rise. (Reference ambient temperature 20°C) (1) インダクタンスはLCR メータ4284A (Agilent Technologies ) または同等品により測定する。測定周波数は1MHz 。 (2) 直流抵抗は測定器34420A （Agilent Technologies ）または3541（HIOKI ）と同等品により測定する。（周囲温度20°C ） (3) 直流重畳許容電流：直流重畳電流を流した時インダクタンスの値が初期値より30%減少する直流電流値 (4) 温度上昇許容電流：コイルの温度が40°C 上昇する値 （周囲温度20°C を基準とする。） Recommended patterns 推奨パターン図 Metal Alloy Inductors メタルアロイ? インダクタ
DSK32 THRU DSK310SURFACE MOUNT SCHOTTKY BARRIER RECTIFIER Reverse Voltage - 20 to 100 Volts Forward Current -3.0 Ampere 1of 2
RATINGS AND CHARACTERISTIC CURVES DSK32 THRU DSK310 FIG. 3-TYPICAL INSTANTANEOUS FORWARD CHARACTERISTICS NUMBER OF CYCLES AT 60 Hz FIG. 2-MAXIMUM NON-REPETITIVE PEAK FORWARD FIG. 1- FORWARD CURRENT DERATING CURVE A V E R A G E F O R W A R D R E C T I F I E D C U R R E N T ,A M P E R E S I N S T A N T A N E O U S F O R W A R D C U R R E N T ,A M P E R E S P E A K F O R W A R D S U R G E C U R R E N T ,A M P E R E S INSTANTANEOUS FORWARD VOLTAGE, VOLTS 100 10 1 0.1 0.010.001 PERCENT OF PEAK REVERSE VOLTAGE,% FIG. 4-TYPICAL REVERSE CHARACTERISTICS I N S T A N T A N E O U S R E V E R S E C U R R E N T ,M I L L I A M P E R E S AMBIENT TEMPERATURE, C 2of 2
1.一般事项 General requirements 1.1 适用范围Scope of Application 本插座适用于打印机、彩色液晶电视接收机、电脑以及网络等电子设备 外接数字信号装置之用。 This socket is used by color TV, component stereo, video disc players, computers and equivalent electronic equipment to connect with external audio and video device. 1.2 标准状态Standard State 除另规定外,测量应在以下状态进行: The test should be tested in the following state unless otherwise specified 温度: 15℃~ 35℃ Temperature: 15℃~ 35℃ 相对湿度: 45% ~ 70% Relative Humidity: 45% ~ 70% 气压: 86K pa ~ 106 K pa Air Pressure: 86K pa ~ 106 K pa 1.3 使用温度范围：-25℃~ +70℃ Operating Temperature Range：-25℃~ +70℃ 1.4 环保要求：符合欧盟RoHS 指令的环保要求。 Environmental Requirement：Comply with the EU environmental requirements ofRoHS directive 2. 额定规格 Rated voltage and current a.额定电压为：（AC、DC、34 V） Rated voltage: AC, DC, 34V b.额定电流为：2.0 A Rated current: 2.0 A 3. 测试要求 Test Requirements 3.1 外观、机械性能 Appearance & Mechanical Performance:
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KBP3005K THRU KBP310K SILICON BRIDGE RECTIFIERS Reverse Voltage - 50 to 1000 Volts Forward Current -3.0 Amperes
RATINGS AND CHARACTERISTIC CURVES KBP3005K THRU KBP310K 1.0 2.0 3.0 50 100 150 I ,A V E R A G E R E C T I F I E D C U R R E N T (A ) O T,TEMPERATURE (°C) 10 100 C , J U N C T I O N C A P A C I T A N C E (p F ) j V , REVERSE VOLTAGE (V) Fig. 4Typical Junction Capacitance R 00.1 1.0 10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 I ,I N S T A N T A N E O U S F W D C U R R E N T (A ) F V ,INSTANTANEOUS FWD VOL TAGE (V) Fig.2T ypical Fwd Characteristics F Fig. 1 Forward Current Derating Curve Fig.3Max Non-Repetitive P eak Fwd Surge Current 50 40 100 30 I F S M ,P E A K F W D S U R G E C U R R E N T (A ) 10 NUMBER OF CYCLES AT 60 Hz 60 100