Intel ? LXT9785 and Intel ? LXT9785E Advanced 8-Port 10/100Mbps PHY Transceivers
Datasheet
The Intel ? LXT9785 and Intel ? LXT9785E are 8-port Fast Ethernet PHY Transceivers
supporting IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices provide Serial/Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent port
applications. The LXT9785 and LXT9785E are identical except for the IP telephony features included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785 that detects Data Terminal Equipment (DTE) requiring power from the switch over a CAT5 cable. The system uses the information collected by the LXT97985E to apply power if the DTE at the far end requires power over the cable, such as an IP telephone.
Each network port can provide a twisted-pair (TP) or Low-V oltage Positive Emitter Coupled Logic (LVPECL) interface. The twisted-pair interface supports 10Mbps and 100Mbps (10BASE-T and 100BASE-TX) Ethernet over twisted-pair. The LVPECL interface supports 100Mbps (100BASE-FX) Ethernet over fiber-optic media.
The LXT9785/LXT9785E provides three discrete LED driver outputs for each port. The devices support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a single 2.5 V power supply.
Applications
Product Features
Enterprise switches
IP telephony switches
Storage Area Networks
Multi-port Network Interface Cards (NICs)
Eight IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports with integrated filters. 100BASE-FX fiber-optic capability on all ports.
2.5 V operation.
Low power consumption; 250 mW per port typical.
Multiple RMII or SMII/SS-SMII ports for independent PHY port operation.
Auto MDI/MDIX crossover capability.
Proprietary Optimal Signal Processing? architecture improves SNR by 3 dB over ideal analog filters.
Optimized for dual-high stacked RJ-45 applications.
MDIO sectionalization into 2x4 or 1x8 configurations.
Supports both auto-negotiation systems and legacy systems without auto-negotiation capability.
Robust baseline wander correction.
Configurable through the MDIO port or external control pins. JTAG boundary scan.
208-pin PQFP: LXT9785HC, LXT9785EHC, LXT9785HE. 241-ball BGA: LXT9785BC, LXT9785EBC.
196-ball BGA: LXT9785MBC
DTE detection for remote powering applications (LXT9785E only).
Extended temperature operation of -40o C to +85o C (LXT9785HE).
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
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Contents
Contents
1.0
Introduction ..................................................................................................................................181.1What You Will Find in This Document................................................................................181.2Related Documents (18)
2.0Block Diagram .............................................................................................................................19
3.0
Pin/Ball Assignments and Signal Descriptions ........................................................................203.1
PQFP Pin Assignments......................................................................................................203.1.1PQFP Pin Assignments – RMII Configuration.......................................................213.1.2PQFP Pin Assignments – SMII Configuration........................................................263.1.3PQFP Pin Assignments – SS-SMII Configuration..................................................313.2
PQFP Signal Descriptions..................................................................................................363.2.1Signal Name Conventions.....................................................................................363.2.2PQFP Signal Descriptions – RMII, SMII, and SS-SMII Configurations..................363.3
BGA23 Ball Assignments....................................................................................................513.3.1RMII BGA23 Ball List.............................................................................................523.3.2SMII BGA23 Ball List.............................................................................................623.3.3SS-SMII BGA23 Ball List.......................................................................................723.4
BGA23 Signal Descriptions ................................................................................................823.4.1Signal Name Conventions.....................................................................................823.4.2Signal Descriptions – RMII, SMII, and SS-SMII Configurations.............................823.5BGA15 Ball Assignments....................................................................................................983.5.1BGA15 Ball List......................................................................................................993.6
BGA15 Signal Descriptions ..............................................................................................1093.6.1Signal Name Conventions...................................................................................1093.6.2Signal Descriptions – SMII and SS-SMII Configurations.....................................1094.0Functional Description ..............................................................................................................1164.1
Introduction.......................................................................................................................1164.1.1OSP? Architecture .............................................................................................1164.1.2Comprehensive Functionality (117)
4.1.2.1Sectionalization (117)
4.2
Interface Descriptions.......................................................................................................1174.2.110/100 Network Interface. (117)
4.2.1.1Twisted-Pair Interface..........................................................................1184.2.1.2MDI Crossover (MDIX).........................................................................1194.2.1.3Fiber Interface.. (119)
4.3
Media Independent Interface (MII) Interfaces...................................................................1194.3.1Global MII Mode Select .......................................................................................1194.3.2Internal Loopback................................................................................................1204.3.3RMII Data Interface..............................................................................................1204.3.4Serial Media Independent Interface (SMII) and Source Synchronous-
Serial Media Independent Interface (SS-SMII)....................................................1214.3.4.1SMII Interface.......................................................................................1214.3.4.2Source Synchronous-Serial Media Independent Interface (121)
4.3.5Configuration Management Interface ..................................................................1214.3.6MII Isolate (121)
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Revision History
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Revision Date: August 28, 2003
Page Description
21Modified Figure 2 “Intel? LXT9785 and Intel? LXT9785E RMII 208-Pin PQFP Assignments”.22Modified Table 2 “Intel? LXT9785/LXT9785E RMII PQFP Pin List”.
26Modified Figure 3 “Intel? LXT9785/LXT9785E SMII 208-Pin PQFP Assignments”.27Modified Table 3 “Intel? LXT9785/LXT9785E SMII PQFP Pin List”.
31Modified Figure 4 “Intel? LXT9785/LXT9785E SS-SMII 208-Pin PQFP Assignments”.32Modified Table 4 “Intel? LXT9785/LXT9785 SS-SMII PQFP Pin List”.
36Modified Table 5 “Intel? LXT9785/LXT9785E RMII Signal Descriptions – PQFP”.
40Modified Table 8 “Intel? LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – PQFP”.43Modified Table 13 “Intel? LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP”.50Modified Table 16 “Intel? LXT9785/LXT9785E Unused/Reserved Pins – PQFP”.
51Replaced old Figures 5, 6, and 7 with Figure 5 “Intel? LXT9785/LXT9785E 241-Ball BGA23 Assignments (Top View)”.
52Modified Table 18 “Intel? LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Signal Name”.
57Modified Table 19 “Intel? LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball Location”.
62Modified Table 20 “Intel? LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Signal Name”.
67Modified Table 21 “Intel? LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball Location”
72Modified Table 22 “Intel? LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Signal Name”.
77Modified Table 23 “Intel? LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location”.
82Modified Table 23 “Intel? LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location”.
86Modified Table 27 “Intel? LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – BGA23”.90Modified Table 32 “Intel? LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23”.97Modified Table 35 “Intel? LXT9785/LXT9785E Unused/Reserved Pins – BGA23”.
98Added Section 3.5, “BGA15 Ball Assignments” (including Figure 6 “Intel? LXT9785MBC 196-Ball BGA15 Assignments (Top View)”, Table 37 “Intel? LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name” through Table 39 “Intel? LXT9785 BGA15 Signal Descriptions”.116Added second paragraph under Section 4.1, “Introduction”.117Added note under Section 4.1.2.1, “Sectionalization”.
119Added note under Table 40 “Intel? LXT9785/LXT9785E MDIX Selection”.119Added note under Section 4.3, “Media Independent Interface (MII) Interfaces”.120
Added note to Table 41 “Intel? LXT9785/LXT9785E MII Mode Select”.
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Document Number: 249241Revision Number: 007
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Document Number: 249241
Revision Number: 007
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Document Number: 249241Revision Number: 007
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Contents
LXT9785 and LXT9785E Advanced 8-Port 10/100Mbps PHY Transceivers
1.0Introduction
This document contains information on the Intel? LXT9785/LXT9785E Advanced 8-port
10/100Mbps Fast Ethernet transceivers.
1.1What You Will Find in This Document
This document contains the following sections:
?Section 3.0, “Pin/Ball Assignments and Signal Descriptions” on page20
This section contains pin/ball assignments and signal descriptions for the following:
—Section 3.1, “PQFP Pin Assignments” on page20
—Section 3.2, “PQFP Signal Descriptions” on page36
—Section 3.3, “BGA23 Ball Assignments” on page51
—Section 3.4, “BGA23 Signal Descriptions” on page82
—Section 3.5, “BGA15 Ball Assignments” on page98
—Section 3.6, “BGA15 Signal Descriptions” on page109
?Section 4.0, “Functional Description” on page116
?Section 5.0, “Application Information” on page164
?Section 6.0, “Test Specifications” on page173
?Section 7.0, “Register Definitions” on page199
?Section 8.0, “Package Specifications” on page221
?Section 9.0, “Ordering Information” on page227
1.2Related Documents
Document Document Number
Intel? LXT9785/LXT9785E Design and Layout Guide249509 Intel? LXT9785/LXT9785E Specification Update249357 Intel? LXT9785/LXT9785E 100BASE-FX Fiber Optic Transceivers: Connecting a PECL/
LVPECL Interface
250781 IP Telephony and DTE Discovery Using Intel Ethernet? PHYs249611
LXT9785 and LXT9785E Advanced 8-Port 10/100
Mbps PHY Transceivers
2.0Block Diagram
Figure 1 provides the LXT9785/LXT9785E block diagram.
Figure 1. Intel ? LXT9785/LXT9785E Block Diagram
Intel? LXT9785 and Intel? LXT9785E Advanced 8-Port 10/100Mbps PHY Transceivers 3.0Pin/Ball Assignments and Signal Descriptions 3.1PQFP Pin Assignments
The following sections show PQFP pin assignments and signal descriptions:
?Section 3.1.1, “PQFP Pin Assignments – RMII Configuration” on page21
?Section 3.1.2, “PQFP Pin Assignments – SMII Configuration” on page26
?Section 3.1.3, “PQFP Pin Assignments – SS-SMII Configuration” on page31
Table1 lists the acronyms and descriptions for signal types.
Table 1. Intel? LXT9785/LXT9785E Signal Type Descriptions
Acronym Description
AI Analog Input
AO Analog Output
I Input
O Output
OD Open Drain Output
ST Schmitt Triggered Input
TS Three-State-able Output
Limited Output
SL Slew-rate
IP Weak Internal Pull-Up
ID Weak Internal Pull-Down
Intel ? LXT9785 and Intel ? LXT9785E Advanced 8-Port 10/100Mbps PHY Transceivers
CRS_DV6.......1RxER6/LINKHOLD..2
TxEN6.......3TxData6_0.......4TxData6_1.......5REFCLK1.......6RxData5_1.......7RxData5_0.......8GNDIO.......9CRS_DV5.......10RxER5/FIFOSEL1.. (11)
TxEN5.......12TxData5_0.......13TxData5_1.......14RxData4_1.......15RxData4_0.......16CRS_DV4.......17VCCIO.......18GNDIO. (19)
RxER4/FIFOSEL0 (20)
TxEN4.......21TxData4_0.......22TxData4_1. (23)
MDC1.......24MDIO1.......25MDINT1.......26RxData3_1.......27RxData3_0.......28VCCIO.......29GNDIO.......30CRS_DV3.......31RxER3.......32TxEN3.......33TxData3_0.......34TxData3_1.......35RxData2_1.......36RxData2_0.......37GNDIO.......38CRS_DV2.......39RxER2/PREASEL.. (40)
TxEN2.......41TxData2_0.......42TxData2_1.......43REFCLK0.......44RxData1_1.......45RxData1_0.......46VCCIO.......47GNDIO.......48CRS_DV1.......49RxER1/PAUSE. (50)
TxEN1.......51TxData1_0. (52)
156.........TPFIN7155.........GNDR7154.........TPFOP7153.........TPFON7152.........VCCT6/7151.........TPFON6150.........TPFOP6149.........GNDR6148.........GNDT6/7147.........TPFIN6146.........TPFIP6145.........VCCR6144.........VCCR5143.........TPFIP5142.........TPFIN5141.........GNDR5140.........TPFOP5139.........TPFON5138.........VCCT4/5137.........TPFON4136.........TPFOP4135.........GNDR4134.........GNDT4/5133.........TPFIN4132.........TPFIP4131.........VCCR4130.........VCCR3129.........TPFIP3128.........TPFIN3127.........GNDT2/3126.........GNDR3125.........TPFOP3124.........TPFON3123.........VCCT2/3122.........TPFON2121.........TPFOP2120.........GNDR2119.........TPFIN2118.........TPFIP2117.........VCCR2116.........VCCR1115.........TPFIP1114.........TPFIN1113.........GNDT0/1112.........GNDR1111.........TPFOP1110.........TPFON1109.........VCCT0/1108.........TPFON0107.........TPFOP0106.........GNDR0105.........TPFIN0
208........ V C C I O 207........ G N D I O 206........ R x D a t a 6_0205........ R x D a t a 6_1204........ T x D a t a 7_1203........ T x D a t a 7_0202........ T x E N 7201........ R x E R 7200........ C R S _D V 7199........ G N D I O 198........ R x D a t a 7_0197........R x D a t a 7_1196........V C C D 195........ G N D D 194........ L E D 7_3193........ L E D 7_2192........ L E D 7_1191........ L E D 6_3190........ L E D 6_2189........ L E D 6_1188........ G N D I O 187........ L E D 5_3186........ L E D 5_2185........ L E D 5_1184........ V C C D 183........ G N D D 182........ L E D 4_3181........ L E D 4_2180........ L E D 4_1179........ S G N D 178........ M o d e S e l 1177........ M o d e S e l 0176........ S e c t i o n 175........ R E S E T 174........ P W R D W N 173........ G _F X /T P 172........ N /C 171....... T R S T 170........ T C K 169........ T M S 168........ T D O 167........ T D I 166........ S D 7165........ S D 6164........ V C C P E C L 163........ G N D P E C L 162........ S D 5161........ S D 4160........ N /C 159........ N /C 158........ V C C R 7157........ T P F I P 7
T x D a t a 1_1......53R x D a t a 0_1......54R x D a t a 0_0......55V C C I O ......56G N D I O ......57C R S _D V 0......58R x E R 0/M D I X ......59T x E N 0......60T x D a t a 0_0......61T x D a t a 0_1......62M D C 0......63M D I O 0......64V C C D ......65G N D D ......66M D I N T 0......67L E D 3_3......68L E D 3_2......69L E D 3_1......70L E D 2_3......71L E D 2_2......72L E D 2_1......73G N D I O ......74L E D 1_3......75L E D 1_2......76L E D 1_1......77V C C D ......78G N D D ......79L E D 0_3......80L E D 0_2......81L E D 0_1......82A M D I X _E N ......83M D D I S ......84C F G _3......85C F G _2......86C F G _1......87A D D _4......88A D D _3......89A D D _2......90A D D _1......91A D D _0......92T x S l e w _1......93T x S l e w _0......94S D _2P 5V ......95S D 0......96S D 1......97V C C P E C L ......98G N D P E C L ......99S D 2......100S D 3......101N /C ......102V C C R 0......103T P F I P 0 (104)
LXT9785/9785E XX XXXXXX XXXXXXXX
Part #LOT #FPO #Rev #
Intel? LXT9785 and Intel? LXT9785E Advanced 8-Port 10/100Mbps PHY Transceivers
OD, TS,
SL, IP
Table8 (page40)
27RxData3_1O, TS,
ID
Table5 (page36)
28RxData3_0O, TS Table5 (page36) 29VCCIO–Table15 (page48)30GNDIO–Table15 (page48) 31CRS_DV3
O, TS,
SL
Table5 (page36) 32RxER3
O, TS,
SL, ID
Table5 (page36) 33TxEN3I, ID Table5 (page36) 34TxData3_0I, ID Table5 (page36) 35TxData3_1I, ID Table5 (page36) 36RxData2_1
O, TS,
ID
Table5 (page36) 37RxData2_0O, TS Table5 (page36) 38GNDIO–Table15 (page48) 39CRS_DV2
O, TS,
SL
Table5 (page36) 40
RxER2
(PREASEL)
O, TS,
SL, ID,
I, ST
Table5 (page36) 41TxEN2I, ID Table5 (page36) 42TxData2_0I, ID Table5 (page36) 43TxData2_1I, ID Table5 (page36) 44REFCLK0I Table5 (page36) 45RxData1_1
O, TS,
ID
Table5 (page36) 46RxData1_0O, TS Table5 (page36) 47VCCIO–Table15 (page48) 48GNDIO–Table15 (page48) 49CRS_DV1
O, TS,
SL
Table5 (page36) 50
RxER1/
PAUSE
O, TS,
SL, ID,
I, ST
Table5 (page36) 51TxEN1I, ID Table5 (page36) 52TxData1_0I, ID Table5 (page36) 53TxData1_1I, ID Table5 (page36) 54RxData0_1
O, TS,
ID
Table5 (page36) 55RxData0_0O, TS Table5 (page36) 56VCCIO–Table15 (page48) 57GNDIO–Table15 (page48) 58CRS_DV0
O, TS,
SL
Table5 (page36) Pin Symbol Type
Reference for Full
Description